The Direct Rambus RIMM module is a general-purpose high-performance memory module subsystem suitable for
use in a broad range of applications including computer memory, personal computers, workstations, and other
applications where high bandwidth and low latency are required.
MC-4R256CPE6C modules consists of sixteen 128M Direct Rambus DRAM (Direct RDRAM™) devices
(
µ
PD488448). These are extremely high-speed CMOS DRAMs organized as 8M words by 16 bits. The use of
Rambus Signaling Level (RSL) technology permits 600MHz, 711MHz or 800MHz transfer rates while using
conventional system and board design technologies.
Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes).
The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous,
randomly addressed memory transactions. The separate control and data buses with independent row and column
control yield over 95 % bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions
per device.
Features
• 184 edge connector pads with 1mm pad spacing
• 256 MB Direct RDRAM storage
• Each RDRAM
• Gold plated contacts
• RDRAMs use Chip Scale Package (CSP)
• Serial Presence Detect support
• Operates from a 2.5 V supply
• Low power and powerdown self refresh modes
• Separate Row and Column buses for higher efficiency
• Over Drive Factor (ODF) support
has 32 banks, for 512 banks total on module
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14809EJ2V0DS00 (2nd edition)
Date Published August 2000 NS CP (K)
Printed in Japan
LCFM, LCFMN,
RCFM, RCFMN : Clock from master
LCTM, LCTMN,
RCTM, RCTMN : Clock to master
LCMD, RCMD: Serial Command Pad
LROW2 - LROW0,
RROW2 - RROW0 : Row bus
LCOL4 - LCOL0,
RCOL4 - RCOL0: Column bus
LDQA8 - LDQA0,
RDQA8 - RDQA0: Data bus A
LDQB8 - LDQB0,
RDQB8 - RDQB0: Data bus B
LSCK, RSCK : Clock input
SA0 - SA2: Serial Presence Detect Address
SCL, SDA: Serial Presence Detect Clock
SIN, SOUT: Serial I/O
DD
SV
: SPD Voltage
SWP: Serial Presence Detect Write Protect
CMOS
V
DD
V
REF
V
: Supply voltage for serial pads
: Supply voltage
: Logic threshold
GND: Ground reference
NC: These pads are not connected
Preliminary Data Sheet M14809EJ2V0DS00
3
MC-4R256CPE6C
Module Pad Names
PadSignal NamePadSignal NamePadSignal NamePadSignal Name
SignalI/OTypeDescription
GND——Ground reference for RDRAM core and interface. 72 PCB connector pads.
LCFMIRSLClock from mas ter. Interface clock used for receiving RSL signals f rom the
Channel. Positive polarity.
LCFMNIRSLClock from master. Interface clock used for receiving RSL signal s from the
Channel. Negative polarity.
LCMDIV
LCOL4..LCOL0IRSLColumn bus. 5-bit bus c ontaining control and address information for column
LCTMIRSLCl ock to master. I nterface clock used for transmitting RSL s i gnal s to the
LCTMNIRSLClock to master. Interface clock used for transmitti ng RSL signals to the
LDQA8..LDQA0I/ORSLData bus A. A 9-bit bus carrying a byte of read or write data between the Channel
LDQB8..LDQB0I/ORSLData bus B. A 9-bit bus carrying a byte of read or write data between the Channel
LROW2..LROW0IRSLRow bus. 3-bi t bus containing control and address i nformation for row accesses .
LSCKIV
NC——These pads are not connected. These 24 connec t or pads are reserved for future
RCFMIRSLClock from master. Interface clock used for receiving RSL signals from the
RCFMNIRSLCl ock from mast er. Interface clock used for receiving RSL signals f rom the
RCMDIV
RCOL4..RCOL0IRSLCol umn bus. 5-bit bus contai ni ng control and address informat i on for column
RCTMIRSLClock to master. Interface clock used for transmitting RSL signals to the
RCTMNIRSLCl ock to master. I nterface clock used for transmitting RSL s i gnal s to the
RDQA8..RDQA0I/ORSLData bus A. A 9-bit bus carrying a byte of read or write data between the Channel
RDQB8..RDQB0I/ORSLData bus B. A 9-bit bus carrying a byte of read or write data between the Channel
RROW2..RROW0IRSLRow bus. 3-bit bus containing control and address informat i on for row accesses.
CMOS
CMOS
CMOS
Serial Command used t o read from and write to the control regis t ers. Also used
for power management.
accesses.
Channel. Positive polarity.
Channel. Negative polarity.
and the RDRAM. LDQA8 is non-functi onal on modules with x16 RDRAM devices.
and the RDRAM. LDQB8 is non-functi onal on modules with x16 RDRAM devices.
Serial clock input. Cl ock source used to read from and write t o the RDRAM
control registers.
use.
Channel. Positive polarity.
Channel. Negative polarity.
Serial Command Input used to read from and write to the control regi sters. Also
used for power management.
accesses.
Channel. Positive polarity.
Channel. Negative polarity.
and the RDRAM. RDQA8 is non-functi onal on modules with x16 RDRAM
devices.
and the RDRAM. RDQB8 is non-functi onal on modules with x16 RDRAM
devices.
(1/2)
Preliminary Data Sheet M14809EJ2V0DS00
5
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