PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-45D16CA721
16 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-45D16CA721 is a 16,777,216 words by 72 bits DDR synchronous dynamic RAM module on which 9 pieces
of 128M DDR SDRAM: µPD45D128842 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 16,777,216 words by 72 bits organization (ECC type)
• Clock frequency
Part number /CAS latency Clock frequency Module type
(MAX.)
MC-45D16CA721KF-C75 CL = 2.5 133 MHz DDR SDRAM
CL = 2 100 MHz Unbuffered DIMM
MC-45D16CA721KF-C80 CL = 2.5 125 MHz Design specificati on
CL = 2 100 MHz Rev.0.9 compliant
• Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge
• Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
• Quad internal banks operation
• Possible to assert random column address in every clock cycle
• Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• 2.5 V ± 0.2 V Power supply for V
• 2.5 V ± 0.2 V Power supply for VDDQ
• SSTL_2 compatible with all signals
• 4,096 refresh cycles / 64 ms
• Burst termination by Precharge command and Burst stop command
• 184-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
DD
Document No. M14898EJ2V0DS00 (2nd edition)
Date Published June 2000 NS CP(K)
Printed in Japan
The mark
shows major revised points.
★★★★
©
2000
Ordering Information
MC-45D16CA721
Part number Clock frequency
(MAX.)
MC-45D16CA721KF-C75 133 MHz 184-pin Dual In-line Memory Module 9 pieces of µPD45D128842G5 (Rev. K)
(Socket Type) (10.16 mm (400) TSOP (II))
MC-45D16CA721KF-C80 125 MHz Edge c onnector: Gold plated
31.75 mm height
Package Mounted devices
2
Preliminary Data Sheet M14898EJ2V0DS00
Pin Configuration
184-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
V
DQ0
V
DQ1
DQS0
DQ2
V
DQ3
NC
/RESET
V
DQ8
DQ9
DQS1
DD
V
CK1
/CK1
V
DQ10
DQ11
CKE0
DD
V
DQ16
DQ17
DQS2
V
DQ18
DD
V
DQ19
DQ24
V
DQ25
DQS3
V
DQ26
DQ27
V
CB0
CB1
V
DQS8
CB2
V
CB3
BA1
DQ32
V
DD
DQ33
DQS4
DQ34
V
BA0
DQ35
DQ40
DD
V
/WE
DQ41
/CAS
V
DQS5
DQ42
DQ43
V
NC
DQ48
DQ49
V
CK2
/CK2
DD
V
DQS6
DQ50
DQ51
V
VDDID
DQ56
DQ57
V
DQS7
DQ58
DQ59
V
NC
SDA
SCL
REF
SS
DD
SS
Q
SS
Q
SS
A9
A7
Q
A5
SS
A4
DD
A2
SS
A1
DD
A0
SS
Q
SS
Q
SS
DD
SS
Q
SS
DD
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
/xxx indicates acti ve low signal.
A0 - A11 : Address Inputs
[Row: A0 - A11, Column: A0 - A9]
BA0, BA1 : SDRAM Bank Select
DQ 0 - D Q63 , C B 0 - C B 7: Data Inputs/Outputs
CK0 - CK2 : Clock Input
(positive line of differential pair)
/CK0 - /CK2 : Clock Input
(negative line of differential pair)
CKE0 : Clock Enable Input
/S0 : Chip Select Input
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQS0 - DQS8 : Low Data Strobe
DM (0 - 8 ) / D QS ( 9 - 1 7 ) : Low Data Masks /
SA0 - SA2 : Address Input for EEPROM
SDA : Serial Data I/O for PD
SCL : Clock Input for PD
DD
V
SS
V
DD
V
DD
V
REF
V
DD
V
NC : No Connection
/RESET : Reset Input
•
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
V
93
94
95
96
97
98
99
SS
DQ4
DQ5
DD
Q
V
DM0/DQS9
DQ6
DQ7
SS
V
NC
NC
NC
DD
Q
V
DQ12
DQ13
DM1/DQS10
DD
V
DQ14
DQ15
NC
DD
Q
V
NC
DQ20
NC
SS
V
DQ21
A11
DM2/DQS11
DD
V
DQ22
A8
DQ23
SS
V
A6
DQ28
DQ29
DD
Q
V
DM3/DQS12
A3
DQ30
SS
V
DQ31
CB4
CB5
DD
Q
V
CK0
/CK0
SS
V
DM8/DQS17
A10
CB6
DD
Q
V
CB7
SS
V
DQ36
DQ37
DD
V
DM4/DQS13
DQ38
DQ39
SS
V
DQ44
/RAS
DQ45
DD
Q
V
/S0
NC
DM5/DQS14
SS
V
DQ46
DQ47
NC
DD
Q
V
DQ52
DQ53
NC
DD
V
DM6/DQS15
DQ54
DQ55
DD
Q
V
NC
DQ60
DQ61
SS
V
DM7/DQS16
DQ62
DQ63
DD
Q
V
SA0
SA1
SA2
DD
SPD
V
MC-45D16CA721
High Data Strobe
: Power Supply
: Ground
ID : VDD Identification Flag
Q : Power Supply for DQ and DQS
: Input Reference
SPD : Power supply for EEPROM
Preliminary Data Sheet M14898EJ2V0DS00
3
•
Block Diagram
/S0
DQS0
DM0/DQS9
DM
DQS
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQS1
DM1/DQS10
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQS2
DM2/DQS11
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQS3
DM3/DQS12
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQS8
DM8/DQS17
CB 0
CB 1
CB 2
CB 3
CB 4
CB 5
CB 6
CB 7
BA0 - BA1 BA0 - BA1 : SDRAMs D0 - D8
A0 - A11 A0 - A11 : SDRAMs D0 - D8
/RAS /RAS : SDRAMs D0 - D8
/CAS /CAS : SDRAMs D0 - D8
CKE0 CKE0 : SDRAMs D0 - D8
/WE /WE : SDRAMs D0 - D8
CK0, /CK0 CK, /CK : SDRAMs D3, D4, D8
CK1, /CK1 CK, /CK : SDRAMs D0, D1, D2
CK2, /CK2 CK, /CK : SDRAMs D5, D6, D7
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DM
DM
DM
DM
/S
D0
DQS
/S
D1
DQS
/S
D2
DQS
/S
D3
DQS
/S
D8
DQS4
DM4/DQS13
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQS5
DM5/DQS14
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQS6
DM6/DQS15
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQS7
DM7/DQS16
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
SCL
V
DD
V
V
V
V
DD
MC-45D16CA721
DM
DQS
/S
DQ 7
DQ 6
D4
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DM
DQS
/S
DQ 7
DQ 6
D5
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DM
DQS
/S
DQ 7
DQ 6
D6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DM
DQS
/S
DQ 7
DQ 6
D7
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
SERIAL PD
SDA
A1 A2
A0
SA1 SA2
SA0
Q
DD
REF
SS
ID
D0 - D8
D0 - D8
D0 - D8
D0 - D8
Remarks 1.
4
The value of all resistors of DQs, DQSs, DM/DQSs is 22 Ω.
2.
D0 – D8:
µ
PD45D128842 (4M words × 8 bits × 4 banks)
Preliminary Data Sheet M14898EJ2V0DS00
MC-45D16CA721
Electrical Specifications
•All voltages are referenced to VSS (GND).
•After power up, wait more than 1 ms and then, execute
proper device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on power supply pin relative to V
Voltage on input pin relative to V
Short circuit output c urrent I
Power dissipation P
Storage temperature T
SS
VDD, VDDQ –0.5 to +3.6 V
SS
T
V
O
D
stg
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Power on sequence and CBR (auto) refresh
–0.5 to +3.6 V
50 mA
12 W
–55 to +125
before
C
°
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage V
Supply voltage for DQ, DQS VDDQ 2.3 2.5 2.7 V
Input reference voltage V
Termination voltage V
High level dc input voltage VIH (DC) V
Low level dc input voltage V
Input differential volt age (CLK and /CLK) VID (DC) 0.36 VDDQ + 0.6 V
Input crossing point voltage (CLK and /CLK) V
Operating ambient tem perature T
Capacitance (TA = 25
C, f = 100 MHz)
°°°°
Parameter Symbol Test condition MIN. TYP. MAX. Unit
Input capacitance C
Data input/output capaci t ance C
DD
REF
TT
IL
(DC)
IX
A
I1
A0 - A11, BA0, BA1, /RAS,
2.3 2.5 2.7 V
0.49 × VDDQ 0.51 × VDDQV
REF
V
− 0.04 V
REF
+ 0.15 VDD + 0.3 V
0.3 V
−
REF
0.5 × VDDQ–0.2 0.5 × VDDQ+0.2 V
070
TBD TBD pF
/CAS, /WE
I2
C
CK0 - CK2, /CK0 - /CK2 TBD TBD
I3
C
CKE0 TBD TBD
I4
C
/S0 TBD TBD
I/O1
DM(0-8)/DQS(9-17),
TBD TBD pF
DQS0 - DQS8
I/O2
C
DQ0 - DQ63, CB0 - CB7 TBD TBD
REF
V
+ 0.04 V
REF
− 0.15 V
C
°
Preliminary Data Sheet M14898EJ2V0DS00
5
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition /CAS
(ACT-PRE)
•
Operating current
(ACT-READ-PRE)
Precharge power down
standby current
Idle standby current I
Active power down
standby current
Active standby current I
Operating current
(Burst read)
Operating current
(Burst write)
CBR (auto) refresh current I
Self refresh current I
RC(MIN.)
tRC = t
DD0
I
, tCK = t
CK (MIN.)
, One bank,
Active-precharge, DQ, DM and DQS
inputs changing twice per clock cycle,
Address and control inputs changing
once per clock cycle
RC(MIN.)
tRC = t
DD1
I
, tCK = t
CK (MIN.)
, One
bank, Active-read-precharge,
O
I
= 0 mA, Burst lengt h = 2,
Address and control inputs
changing once per clock cyc l e
DD2P
I
CKE ≤ V
IL(MAX.)
, tCK = t
CK(MIN.)
,
All banks idle, Power down mode
DD2N
CKE ≥ V
IH(MIN.)
, tCK = t
CK(MIN.)
, /CS ≥ V
All banks idle, Addres s and other control inputs
changing once per clock cyc l e
DD3P
I
CKE ≤ V
IL(MAX.)
, tCK = t
CK(MIN.)
, One bank active,
Power down mode
DD3N
IH(MIN.)
/CS ≥ V
RAS(MAX.)
t
, CKE ≥ V
, One bank, Active-precharge, DQ, DM
IH(MIN.)
, tCK = t
and DQS inputs changing twice per clock
cycle, Address and other c ontrol inputs
changing once per clock cyc l e
CK(MIN.)
tCK = t
DD4R
I
read, Burst length = 2, I
, Continuous burst
O
=
0mA, One bank active,
Address and control inputs
changing once per clock cyc l e
DD4W
I
tCK = t
, Continuous burst
CK(MIN.)
write, Burst length = 2, One
bank active, Address and
control inputs changing once
per clock cycle
RFC
RFC(MIN.)
t
DD5
DD6
= t
CKE ≤ 0.2 V
latency
CL = 2 -C75 TBD mA
CL = 2.5 -C75 TBD
CL = 2 -C75 TBD mA
CL = 2.5 -C75 TBD
CL = 2 -C75 TBD mA
CL = 2.5 -C75 TBD
Grade MIN. MAX. Unit
-C75 TBD mAOperating current
-C80 TBD
-C80 TBD
-C80 TBD
IH(MIN.)
,
CK(MIN.)
, tRC =
-C80 TBD
-C80 TBD
-C80 TBD
-C80 TBD
-C75 TBD mA
-C80 TBD
MC-45D16CA721
Notes
1
TBD mA
TBD mA
TBD mA
TBD mA
2
2
TBD mA
Notes 1.
DD1
I
depends on output loading and cycle rates. Specified values are obtained with the output open.
DD4R
2.
I
and I
DD4W
depend on output loading and cycle rates. Specified values are obtained with the output
open.
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test conditi on MIN. MAX. Unit Notes
Input leakage current I
Output leakage current I
Output high current I
Output low current I
6
I(L)VI
= 0 to 3.6 V, all other pins not under test = 0 V TBD TBD
O(L)DOUT
OHVOUT
OLVOUT
is disabled, VO = 0 to VDDQ + 0.3 V TBD TBD
= VDDQ − 0.43 V TBD mA
= 0.35 V TBD mA
Preliminary Data Sheet M14898EJ2V0DS00
A
µ
A
µ
MC-45D16CA721
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter Symbol Value Unit Notes
Input Reference voltage (Input t i ming measurement reference level) V
Termination voltage (Output timing measurement reference level) V
High level ac input voltage VIH(ac) V
Low level ac input voltage VIL(ac) V
Input differential vol tage (CK0 - CK2 and /CK0 - /CK2) VID(ac) 0.7 V
Input signal slew rate SLEW 1 V/ns 2
Notes 1.
Output waveform timing is measured where the output signal crosses through the V
2.
Slew rate is to be maintained in the VIL (ac) to VIH(ac) range of the input signal swing. SLEW = (VIH(ac)-
IL
(ac))/ ∆t
V
REF
TT
TT
V
VDDQ x 0.5 V
REF
V
REF
+ 0.31 V
REF
− 0.31 V
TT
level.
V1
Output
RT = 50 Ω
C
LOAD = 30 pF
Preliminary Data Sheet M14898EJ2V0DS00
7
Synchronous Characteristics
Parameter Symbol -C75 (PC266B) -C80 (PC200) Unit Note
Clock cycle time CL = 2.5 t
CL = 2 10151015
CLK high-level width t
CLK low-level width t
DQ output access time from CLK, /CLK t
DQS output access t i me from CLK, /CLK t
DQS-DQ skew (for DQS and associated DQ
signals)
DQS-DQ skew (for DQS and all DQ signals) t
Data out low-impedance tim e from CLK, /CLK t
Data out high-impedance time from CLK, /CLK t
Half clock period t
DQS read preamble t
DQS read postamble t
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
DQ and DM input setup time t
DQ and DM input hold time t
DQ and DM input pulse width (for each input) t
DQS write preamble setup time t
DQS write preamble t
Write postamble t
Write command to first DQS l atching transition t
DQS input high pulse width t
DQS input low pulse width t
DQS falling edge to CLK setup t i me t
DQS falling edge hold time from CLK t
Address and control input s etup time t
Address and control input hold time t
Address and control input pulse width t
Internal write to read command delay t
CK
CH
CL
AC
DQSCK
DQSQ
t
DQSQA
LZ
HZ
HP
RPRE
RPST
QH
t
DS
DH
DIPW
WPRES
WPRE
WPST
DQSS
DQSH
DQSL
DSS
DSH
IS
IH
IPW
WTR
MC-45D16CA721
MIN. MAX. MIN. MAX.
7.515815ns
0.45 0.55 0.45 0.55 t
0.45 0.55 0.45 0.55 t
–0.75 0.75 –0.8 0.8 ns
–0.75 0.75 –0.8 0.8 ns
–0.5 0.5 –0.6 0.6 ns
–0.5 0.5 –0.6 0.6 ns
–0.75 0.75 –0.8 0.8 ns
–0.75 0.75 –0.8 0.8 ns
tCH, t
CL
tCH, t
CL
0.9 1.1 0.9 1.1 t
0.4 0.6 0.4 0.6 t
tHP – 0.75 tHP – 1 ns
0.5 0.6 ns
0.5 0.6 ns
1.75 2 ns
00ns
0.25 0.25 t
0.4 0.6 0.4 0.6 t
0.75 1.25 0.75 1.25 t
0.35 0.35 t
0.35 0.35 t
0.2 0.2 t
0.2 0.2 t
0.9 1.1 ns
0.9 1.1 ns
2.2 2.5 ns
11t
CK
CK
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Remark
8
These specifications are applied to the monolithic device.
Preliminary Data Sheet M14898EJ2V0DS00
Asynchronous Characteristics
Parameter Symbol -C75(PC266B) -C80(PC200) Unit
ACT to REF/ACT comm and peri od (operat i on) t
REF to REF/ACT command period (refresh) t
ACT to PRE command period t
PRE to ACT command period t
ACT to READ/WRITE delay t
ACT(one) to ACT(another) command period t
Write recovery t ime t
Auto precharge write recovery time + precharge time t
Mode register set command cycle time t
Exit self refresh to command t
Refresh time (4,096 refres h cycles) t
RC
RFC
RAS
RP
RCD
RRD
WR
DAL
MRD
XSNR
REF
MC-45D16CA721
MIN. MAX. MIN. MAX.
65 70 ns
75 80 ns
45 120,000 50 120,000 ns
20 20 ns
20 20 ns
15 15 ns
15 15 ns
35 35 ns
15 15 ns
75 80 ns
64 64 ms
Preliminary Data Sheet M14898EJ2V0DS00
9
MC-45D16CA721
Serial PD (1/2)
Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
0 Defines the number of bytes written into
serial PD memory
1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes
2 Fundamental memory type 07H 0 0 0 0 0 1 1 1 DDR SDRAM
3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows
4 Number of columns 0AH 0 0 0 0 1 0 1 0 10 colum ns
5 Number of banks 01H 0 0 0 0 0 0 0 1 1 bank
6 Data width 48H 0 1 0 0 1 0 0 0 72 bits
7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0
8 Voltage interf ac e 04H 0 0 0 0 0 1 0 0 SSTL2
9 CL = 2.5 Cycle time -C75 75H 0 1 1 1 0 1 0 1 7.5 ns
-C80 80H 1 0 0 0 0 0 0 0 8 ns
10 CL = 2.5 Access time -C75 75H 0 1 1 1 0 1 0 1 0.75 ns
-C80 80H 1 0 0 0 0 0 0 0 0.8 ns
11 DIMM configuration type 02H 0 0 0 0 0 0 1 0 ECC
12 Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal
13SDRAM width 08H00001000x8
14 Error checking SDRAM width 08H 0 0 0 0 1 0 0 0 x8
15 Minimum clock del ay 01H 0 0 0 0 0 0 0 1 1 clock
16 Burst length supported 0EH 0 0 0 0 1 1 1 0 2, 4, 8
17 Number of banks on each SDRA M 04H 0 0 0 0 0 1 0 0 4 banks
18 /CAS latency support ed 0CH 0 0 0 0 1 1 0 0 2, 2.5
19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0
20 /WE latency supported 02H 0 0 0 0 0 0 1 0 1
21 SDRAM module attributes 20H 0 0 1 0 0 0 0 0
22 SDRAM device attributes : General 00H 0 0 0 0 0 0 0 0 VDD ± 0.2 V
23 CL = 2 Cycle time -C75 A0H 1 0 1 0 0 0 0 0 10 ns
-C80 A0H 1 0 1 0 0 0 0 0 10 ns
24 CL = 2 Access time -C75 75H 0 1 1 1 0 1 0 1 0.75 ns
-C80 80H 1 0 0 0 0 0 0 0 0.8 ns
25-26
RP(MIN.)
27 t
-C75 50H 0 1 0 1 0 0 0 0 20 ns
-C80 50H 0 1 0 1 0 0 0 0 20 ns
RRD(MIN.)
28 t
-C75 3CH 0 0 1 1 1 1 0 0 15 ns
-C80 3CH 0 0 1 1 1 1 0 0 15 ns
RCD(MIN.)
29 t
-C75 50H 0 1 0 1 0 0 0 0 20 ns
-C80 50H 0 1 0 1 0 0 0 0 20 ns
RAS(MIN.)
30 t
-C75 2DH 0 0 1 0 1 1 0 1 45 ns
-C80 32H 0 0 1 1 0 0 1 0 50 ns
31 Module bank density 20H 0 0 1 0 0 0 0 0 128M bytes
80H 1 0 0 0 0 0 0 0 128 bytes
Differential Clock
10
Preliminary Data Sheet M14898EJ2V0DS00
MC-45D16CA721
Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
32 Command and address si gnal -C75 90H 1 0 0 1 0 0 0 0 0.9 ns
input setup time -C80 B0H 1 0 1 1 0 0 0 0 1.1 ns
33 Command and address si gnal -C75 90H 1 0 0 1 0 0 0 0 0.9 ns
input hold time -C80 B0H 1 0 1 1 0 0 0 0 1.1 ns
34 Data signal input setup ti me -C75 50H 0 1 0 1 0 0 0 0 0.5 ns
-C80 60H 0 1 1 0 0 0 0 0 0.6 ns
35 Data signal input hold time -C75 50H 0 1 0 1 0 0 0 0 0.5 ns
-C80 60H 0 1 1 0 0 0 0 0 0.6 ns
36-61
62SPD revision 00H00000000
63 Checksum for bytes 0 - 62 -C75 AEH 1 0 1 0 1 1 1 0
-C8034H00110100
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91 Revision Code
93-94 Manufacturing date
95-99 Assembly serial number
100-127 Mfg specific 00H 0 0 0 0 0 0 0 0
(2/2)
Timing Chart
Refer to the µPD45D128442, 45D128842, 45D128164 Data sheet (M13852E).
Preliminary Data Sheet M14898EJ2V0DS00
11
Package Drawing
184-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
J1 (AREA B)
M
M
I
U
MC-45D16CA721
K
J
H
J2 (AREA A)
G
detail of A part
C1
E
C2
A
B
N
(OPTIONAL HOLES)
D
P
Q
C
A1 (AREA A)
ITEM MILLIMETERS
A
133.35
A1
133.35±0.13
B
64.77
C
6.35
C1
1.80
C2
3.80
D
49.53
E
S
R
T
G
H
J
J1
J2
K
M
N
P
Q
R
S
T
U
I
1.27 (T.P.)
6.35
10.00
17.80
31.75±0.13
23.38
19.80
4.0 MAX.
4.0
φ
2.50
1.27±0.1
4.0 MIN.
0.2±0.15
1.0±0.05
2.50±0.15
3.0 MIN.
12
Preliminary Data Sheet M14898EJ2V0DS00
[MEMO]
MC-45D16CA721
Preliminary Data Sheet M14898EJ2V0DS00
13
[MEMO]
MC-45D16CA721
14
Preliminary Data Sheet M14898EJ2V0DS00
MC-45D16CA721
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
DD
pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
or GND with a resistor, if it is considered to have a possibility of
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Data Sheet M14898EJ2V0DS00
15
MC-45D16CA721
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
•
The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
•
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
•
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
•
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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