NEC MC-4564EC726PFB-A80, MC-4564EC726PFB-A10, MC-4564EC726EFB-A10, MC-4564EC726EFB-A80 Datasheet
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4564EC726
64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4564EC726 is a 67,108,864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of
µ
128 M SDRAM:
These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 67,108,864 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK
PD45128441 are assembled.
Part number /CAS latency Clock frequency Access time from CLK Module type
(MAX.) (MAX.)
MC-4564EC726EFB-A80 CL = 3 125 MHz 6 ns PC100 Registered DIMM
CL = 2 100 MHz 6 ns Rev. 1.2 Compliant
MC-4564EC726EFB-A10 CL = 3 100 MHz 6 ns
CL = 2 77 MHz 7 ns
MC-4564EC726PFB-A80 CL = 3 125 MHz 6 ns
★
CL = 2 100 MHz 6 ns
MC-4564EC726PFB-A10 CL = 3 100 MHz 6 ns
★
CL = 2 77 MHz 7 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
/
• Programmable wrap sequence (Sequential
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10
• Single 3.3
• LVTTL compatible
• 4,096 refresh cycles / 64
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27
• Registered type
• Serial PD
• Stacked monolithic technology
Ω ± 10 % of series resistor
V ± 0.3 V power supply
ms
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Interleave)
mm)
Document No. M14460EJ2V0DS00 (2nd edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark
★★★★
shows major revised points.
©
1999
Ordering Information
Part number Clock frequency
MC-4564EC726EFB-A80 125 MHz 168-pin Dual In-line Memory Module 36 pieces of µPD45128441G5 (Rev. E)
MC-4564EC726EFB-A10 100 MHz (Socket Type)
★
★
MC-4564EC726PFB-A80 125 MHz Edge connector: Gold plated 36 pieces of µPD45128441G5 (Rev. P)
MC-4564EC726PFB-A10 100 MHz 43.18 mm height
MC-4564EC726
Package Mounted devices
(MAX.)
(10.16 mm (400) TSOP (II ))
(10.16 mm (400) TSOP (II ))
2
Data Sheet M14460EJ2V0DS00
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
MC-4564EC726
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
★
★
★
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SS
V
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
/CS1
/RAS
V
SS
A1
A3
A5
A7
A9
BA0
(A13)
A11
Vcc
CLK1
NC
V
SS
CKE0
/CS3
DQMB6
DQMB7
NC
Vcc
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
NC
SA0
SA1
SA2
Vcc
V
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
V
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
V
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
V
A10
BA1(A12)
Vcc
Vcc
CLK0
V
NC
/CS2
DQMB2
DQMB3
NC
Vcc
NC
NC
CB2
CB3
V
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
V
DQ21
DQ22
DQ23
V
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
V
CLK2
NC
WP
SDA
SCL
Vcc
SS
SS
SS
SS
A0
A2
A4
A6
A8
SS
SS
SS
SS
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
/xxx indica tes active low signal.
A0 - A11 : Address Inputs
[Row: A0 - A11, Column: A0 - A9, A11]
BA0
(A13), BA1 (A12) : SDRAM Bank Select
DQ 0 - D Q63 , C B 0 - C B 7: Data Inputs/Outputs
CLK0 - CLK3 : Clock Input
CKE0 : Clock Enable Input
WP : Write Protect
/CS0 - /CS3 : Chip Select Input
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQ MB 0 - D Q MB 7 : DQ Mask Enable
SA0 - SA2 : Address Input for EEPROM
SDA : Serial Data I/O for PD
SCL : Clock Input for PD
CC
V
SS
V
: Power Supply
: Ground
REGE : Register / Buffer Enable
NC : No Connection
Data Sheet M14460EJ2V0DS00
3
MC-4564EC726
Block Diagram (1/2)
/RCS1
/RCS0
RDQMB0
DQ 3
DQ 2
DQ 1
DQ 0
DQ 6
DQ 5
DQ 4
RDQMB1
DQ11
DQ10
DQ 9
DQ 8
DQ14
DQ13
DQ12
CB 2
CB 1
CB 0
/RCS3
/RCS2
RDQMB2
DQ19
DQ18
DQ17
DQ16
DQ22
DQ21
DQ20
RDQMB3
DQ27
DQ26
DQ25
DQ24
DQ30
DQ29
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D0
DQM /CS
D1
DQM /CS
D2
DQM /CS
D3
DQM /CS
D4
DQM /CS
D5
DQM /CS
D6
DQM /CS
D7
DQM /CS
D8
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D18
DQM /CSDQ 7
D19
DQM /CS
D20
DQM /CSDQ15
D21
DQM /CSCB 3
D22
DQM /CS
D23
DQM /CSDQ23
D24
DQM /CS
D25
DQM /CSDQ31
D26
RDQMB4
DQ32
DQ33
DQ34
DQ35
DQ37
DQ38
DQ39
RDQMB5
DQ40
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
CB 5
CB 6
CB 7
RDQMB6
DQ48
DQ49
DQ50
DQ51
DQ53
DQ54
DQ55
RDQMB7
DQ56
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D9
DQM /CS
D10
DQM /CS
D11
DQM /CS
D12
DQM /CS
D13
DQM /CS
D14
DQM /CS
D15
DQM /CS
D16
DQM /CS
D17
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D27
DQM /CSDQ36
D28
DQM /CS
D29
DQM /CSDQ44
D30
DQM /CSCB 4
D31
DQM /CS
D32
DQM /CSDQ52
D33
DQM /CS
D34
DQM /CSDQ60
D35
CLK0
10 Ω
PLL
CLK: D0, D18, D9, D27
CLK: D1, D19, D10, D28
CLK: D2, D20, D11, D29
CLK: D3, D21, D12, D30
CLK: D4, D22, D13, D31
CLK: D5, D23, D14, D32
CLK1 - CLK3
10 Ω
12 pF
CLK: D6, D24, D15, D33
★
★
V
CC
V
SS
D0 - D35, REGISTER1 - REGISTER3, PLL
C
D0 - D35, REGISTER1 - REGISTER3, PLL
4
CLK: D7, D25, D16, D34
CLK: D8, D26, D17, D35
CLK: Register1- Register3
Data Sheet M14460EJ2V0DS00
SCL
SERIAL PD
A1 A2
A0
SA1 SA2
SA0
SDA
WP
47 kΩ
MC-4564EC726
Block Diagram (2/2)
REGE
10 kΩ
/RAS
/CAS
BA0
/CS1
DQMB4
DQMB5
A10
/WE
BA0
/CS0
DQMB0
DQMB1
A1
A3
A5
A7
A9
A0
A2
A4
A6
A8
Register 1
/LE
Register 2
/LE
R1A1: D0-D4, D9-D12, D18-D22, D27-D30
R2A1: D5-D8, D13-D17, D23-D26, D31-D35
R1A3: D0-D4, D9-D12, D18-D22, D27-D30
R2A3: D5-D8, D13-D17, D23-D26, D31-D35
R1A5: D0-D4, D9-D12, D18-D22, D27-D30
R2A5: D5-D8, D13-D17, D23-D26, D31-D35
R1A7: D0-D4, D9-D12, D18-D22, D27-D30
R2A7: D5-D8, D13-D17, D23-D26, D31-D35
R1A9: D0-D4, D9-D12, D18-D22, D27-D30
R2A9: D5-D8, D13-D17, D23-D26, D31-D35
R1RAS: D0-D4, D9-D12, D18-D22, D27-D30
R2RAS: D5-D8, D13-D17, D23-D26, D31-D35
R1CAS: D0-D4, D9-D12, D18-D22, D27-D30
R2CAS: D5-D8, D13-D17, D23-D26, D31-D35
R1BA0: D0-D4, D9-D12, D18-D22, D27-D30
RCS1
RDQMB4
RDQMB5
R1A0: D0-D4, D9-D12, D18-D22, D27-D30
R2A0: D5-D8, D13-D17, D23-D26, D31-D35
R1A2: D0-D4, D9-D12, D18-D22, D27-D30
R2A2: D5-D8, D13-D17, D23-D26, D31-D35
R1A4: D0-D4, D9-D12, D18-D22, D27-D30
R2A4: D5-D8, D13-D17, D23-D26, D31-D35
R1A6: D0-D4, D9-D12, D18-D22, D27-D30
R2A6: D5-D8, D13-D17, D23-D26, D31-D35
R1A8: D0-D4, D9-D12, D18-D22, D27-D30
R2A8: D5-D8, D13-D17, D23-D26, D31-D35
R1A10: D0-D4, D9-D12, D18-D22, D27-D30
R2A10: D5-D8, D13-D17, D23-D26, D31-D35
R1WE: D0-D4, D9-D12, D18-D22, D27-D30
R2WE: D5-D8, D13-D17, D23-D26, D31-D35
R2BA0: D5-D8, D13-D17, D23-D26, D31-D35
RCS0
RDQMB4
RDQMB5
Remarks 1.
A11
BA1
CKE0
/CS2
/CS3
DQMB2
DQMB3
DQMB6
DQMB7
The value of all resistors of DQs is 10 Ω.
2.
D0 – D35:
3.
REGE ≤ V
REGE ≥ V
4.
Register: HD74ALVC16835
µ
PD45128441 (8M words × 4 bits × 4 banks)
IL
: Buffer mode
IH
: Register mode
PLL: HD74CDC2510B
Register 3
/LE
R1A11: D0-D4, D9-D12, D18-D22, D27-D30
R2A11: D5-D8, D13-D17, D23-D26, D31-D35
R1BA1: D0-D4, D9-D12, D18-D22, D27-D30
R2BA1: D5-D8, D13-D17, D23-D26, D31-D35
R1CKE0: D0-D2, D9-D10, D18-D20, D27-D28
R2CKE0: D5-D6, D14-D15, D23-D24, D32-D33
R3CKE0: D3-D4, D11-D13, D21-D22, D29-D31
R4CKE0: D7-D8, D16-D17, D23-D24, D34-D35
RCS2
RCS3
RDQMB2
RDQMB3
RDQMB6
RDQMB7
Data Sheet M14460EJ2V0DS00
5
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