NEC MC-4564EC726PFB-A80, MC-4564EC726PFB-A10, MC-4564EC726EFB-A10, MC-4564EC726EFB-A80 Datasheet
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4564EC726
64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4564EC726 is a 67,108,864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of
µ
128 M SDRAM:
These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 67,108,864 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK
PD45128441 are assembled.
Part number /CAS latency Clock frequency Access time from CLK Module type
(MAX.) (MAX.)
MC-4564EC726EFB-A80 CL = 3 125 MHz 6 ns PC100 Registered DIMM
CL = 2 100 MHz 6 ns Rev. 1.2 Compliant
MC-4564EC726EFB-A10 CL = 3 100 MHz 6 ns
CL = 2 77 MHz 7 ns
MC-4564EC726PFB-A80 CL = 3 125 MHz 6 ns
★
CL = 2 100 MHz 6 ns
MC-4564EC726PFB-A10 CL = 3 100 MHz 6 ns
★
CL = 2 77 MHz 7 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
/
• Programmable wrap sequence (Sequential
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10
• Single 3.3
• LVTTL compatible
• 4,096 refresh cycles / 64
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27
• Registered type
• Serial PD
• Stacked monolithic technology
Ω ± 10 % of series resistor
V ± 0.3 V power supply
ms
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Interleave)
mm)
Document No. M14460EJ2V0DS00 (2nd edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark
★★★★
shows major revised points.
©
1999
Ordering Information
Part number Clock frequency
MC-4564EC726EFB-A80 125 MHz 168-pin Dual In-line Memory Module 36 pieces of µPD45128441G5 (Rev. E)
MC-4564EC726EFB-A10 100 MHz (Socket Type)
★
★
MC-4564EC726PFB-A80 125 MHz Edge connector: Gold plated 36 pieces of µPD45128441G5 (Rev. P)
MC-4564EC726PFB-A10 100 MHz 43.18 mm height
MC-4564EC726
Package Mounted devices
(MAX.)
(10.16 mm (400) TSOP (II ))
(10.16 mm (400) TSOP (II ))
2
Data Sheet M14460EJ2V0DS00
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
MC-4564EC726
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
★
★
★
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SS
V
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
/CS1
/RAS
V
SS
A1
A3
A5
A7
A9
BA0
(A13)
A11
Vcc
CLK1
NC
V
SS
CKE0
/CS3
DQMB6
DQMB7
NC
Vcc
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
NC
SA0
SA1
SA2
Vcc
V
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
V
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
V
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
V
A10
BA1(A12)
Vcc
Vcc
CLK0
V
NC
/CS2
DQMB2
DQMB3
NC
Vcc
NC
NC
CB2
CB3
V
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
V
DQ21
DQ22
DQ23
V
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
V
CLK2
NC
WP
SDA
SCL
Vcc
SS
SS
SS
SS
A0
A2
A4
A6
A8
SS
SS
SS
SS
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
/xxx indica tes active low signal.
A0 - A11 : Address Inputs
[Row: A0 - A11, Column: A0 - A9, A11]
BA0
(A13), BA1 (A12) : SDRAM Bank Select
DQ 0 - D Q63 , C B 0 - C B 7: Data Inputs/Outputs
CLK0 - CLK3 : Clock Input
CKE0 : Clock Enable Input
WP : Write Protect
/CS0 - /CS3 : Chip Select Input
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQ MB 0 - D Q MB 7 : DQ Mask Enable
SA0 - SA2 : Address Input for EEPROM
SDA : Serial Data I/O for PD
SCL : Clock Input for PD
CC
V
SS
V
: Power Supply
: Ground
REGE : Register / Buffer Enable
NC : No Connection
Data Sheet M14460EJ2V0DS00
3
MC-4564EC726
Block Diagram (1/2)
/RCS1
/RCS0
RDQMB0
DQ 3
DQ 2
DQ 1
DQ 0
DQ 6
DQ 5
DQ 4
RDQMB1
DQ11
DQ10
DQ 9
DQ 8
DQ14
DQ13
DQ12
CB 2
CB 1
CB 0
/RCS3
/RCS2
RDQMB2
DQ19
DQ18
DQ17
DQ16
DQ22
DQ21
DQ20
RDQMB3
DQ27
DQ26
DQ25
DQ24
DQ30
DQ29
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D0
DQM /CS
D1
DQM /CS
D2
DQM /CS
D3
DQM /CS
D4
DQM /CS
D5
DQM /CS
D6
DQM /CS
D7
DQM /CS
D8
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D18
DQM /CSDQ 7
D19
DQM /CS
D20
DQM /CSDQ15
D21
DQM /CSCB 3
D22
DQM /CS
D23
DQM /CSDQ23
D24
DQM /CS
D25
DQM /CSDQ31
D26
RDQMB4
DQ32
DQ33
DQ34
DQ35
DQ37
DQ38
DQ39
RDQMB5
DQ40
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
CB 5
CB 6
CB 7
RDQMB6
DQ48
DQ49
DQ50
DQ51
DQ53
DQ54
DQ55
RDQMB7
DQ56
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D9
DQM /CS
D10
DQM /CS
D11
DQM /CS
D12
DQM /CS
D13
DQM /CS
D14
DQM /CS
D15
DQM /CS
D16
DQM /CS
D17
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D27
DQM /CSDQ36
D28
DQM /CS
D29
DQM /CSDQ44
D30
DQM /CSCB 4
D31
DQM /CS
D32
DQM /CSDQ52
D33
DQM /CS
D34
DQM /CSDQ60
D35
CLK0
10 Ω
PLL
CLK: D0, D18, D9, D27
CLK: D1, D19, D10, D28
CLK: D2, D20, D11, D29
CLK: D3, D21, D12, D30
CLK: D4, D22, D13, D31
CLK: D5, D23, D14, D32
CLK1 - CLK3
10 Ω
12 pF
CLK: D6, D24, D15, D33
★
★
V
CC
V
SS
D0 - D35, REGISTER1 - REGISTER3, PLL
C
D0 - D35, REGISTER1 - REGISTER3, PLL
4
CLK: D7, D25, D16, D34
CLK: D8, D26, D17, D35
CLK: Register1- Register3
Data Sheet M14460EJ2V0DS00
SCL
SERIAL PD
A1 A2
A0
SA1 SA2
SA0
SDA
WP
47 kΩ
MC-4564EC726
Block Diagram (2/2)
REGE
10 kΩ
/RAS
/CAS
BA0
/CS1
DQMB4
DQMB5
A10
/WE
BA0
/CS0
DQMB0
DQMB1
A1
A3
A5
A7
A9
A0
A2
A4
A6
A8
Register 1
/LE
Register 2
/LE
R1A1: D0-D4, D9-D12, D18-D22, D27-D30
R2A1: D5-D8, D13-D17, D23-D26, D31-D35
R1A3: D0-D4, D9-D12, D18-D22, D27-D30
R2A3: D5-D8, D13-D17, D23-D26, D31-D35
R1A5: D0-D4, D9-D12, D18-D22, D27-D30
R2A5: D5-D8, D13-D17, D23-D26, D31-D35
R1A7: D0-D4, D9-D12, D18-D22, D27-D30
R2A7: D5-D8, D13-D17, D23-D26, D31-D35
R1A9: D0-D4, D9-D12, D18-D22, D27-D30
R2A9: D5-D8, D13-D17, D23-D26, D31-D35
R1RAS: D0-D4, D9-D12, D18-D22, D27-D30
R2RAS: D5-D8, D13-D17, D23-D26, D31-D35
R1CAS: D0-D4, D9-D12, D18-D22, D27-D30
R2CAS: D5-D8, D13-D17, D23-D26, D31-D35
R1BA0: D0-D4, D9-D12, D18-D22, D27-D30
RCS1
RDQMB4
RDQMB5
R1A0: D0-D4, D9-D12, D18-D22, D27-D30
R2A0: D5-D8, D13-D17, D23-D26, D31-D35
R1A2: D0-D4, D9-D12, D18-D22, D27-D30
R2A2: D5-D8, D13-D17, D23-D26, D31-D35
R1A4: D0-D4, D9-D12, D18-D22, D27-D30
R2A4: D5-D8, D13-D17, D23-D26, D31-D35
R1A6: D0-D4, D9-D12, D18-D22, D27-D30
R2A6: D5-D8, D13-D17, D23-D26, D31-D35
R1A8: D0-D4, D9-D12, D18-D22, D27-D30
R2A8: D5-D8, D13-D17, D23-D26, D31-D35
R1A10: D0-D4, D9-D12, D18-D22, D27-D30
R2A10: D5-D8, D13-D17, D23-D26, D31-D35
R1WE: D0-D4, D9-D12, D18-D22, D27-D30
R2WE: D5-D8, D13-D17, D23-D26, D31-D35
R2BA0: D5-D8, D13-D17, D23-D26, D31-D35
RCS0
RDQMB4
RDQMB5
Remarks 1.
A11
BA1
CKE0
/CS2
/CS3
DQMB2
DQMB3
DQMB6
DQMB7
The value of all resistors of DQs is 10 Ω.
2.
D0 – D35:
3.
REGE ≤ V
REGE ≥ V
4.
Register: HD74ALVC16835
µ
PD45128441 (8M words × 4 bits × 4 banks)
IL
: Buffer mode
IH
: Register mode
PLL: HD74CDC2510B
Register 3
/LE
R1A11: D0-D4, D9-D12, D18-D22, D27-D30
R2A11: D5-D8, D13-D17, D23-D26, D31-D35
R1BA1: D0-D4, D9-D12, D18-D22, D27-D30
R2BA1: D5-D8, D13-D17, D23-D26, D31-D35
R1CKE0: D0-D2, D9-D10, D18-D20, D27-D28
R2CKE0: D5-D6, D14-D15, D23-D24, D32-D33
R3CKE0: D3-D4, D11-D13, D21-D22, D29-D31
R4CKE0: D7-D8, D16-D17, D23-D24, D34-D35
RCS2
RCS3
RDQMB2
RDQMB3
RDQMB6
RDQMB7
Data Sheet M14460EJ2V0DS00
5
MC-4564EC726
Electrical Specifications
•
All voltages are referenced to V
•
After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on power supply pin relative to GND V
Voltage on input pin relative to GND V
Short circuit output c urrent I
Power dissipation P
Operating ambient tem perature T
Storage temperature T
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
SS
(GND).
CC
T
O
D
A
stg
–0.5 to +4.6 V
–0.5 to +4.6 V
50 mA
40 W
0 to 70
–55 to +125
°
C
°
C
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage V
High level input voltage V
Low level input voltage V
Operating ambient tem perature T
Capacitance (TA = 25 °°°°C, f = 1 MHz)
Parameter Symbol Test c ondi t i on MIN. TYP. MAX. Unit
Input capacitance C
★
Data input/output capaci t ance C
CC
IH
IL
A
I1
A0 - A11, BA0 (A13), BA1 (A12),
3.0 3.3 3.6 V
2.0 V
–0.3 +0.8 V
070
TBD TBD pF
/RAS, /CAS, /WE
I2
C
CLK0 TBD TBD
I3
C
CKE0 TBD TBD
I4
C
/CS0 - /CS3 TBD TBD
I5
C
DQMB0 - DQMB7 TBD TBD
I/O
DQ0 - DQ63, CB0 - CB7 TBD TBD pF
CC +
0.3 V
°
C
6
Data Sheet M14460EJ2V0DS00
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition Grade MIN. MAX. Unit Notes
MC-4564EC726
Operating current I
CC1
Burst length = 1 /CAS latency = 2 -A80 2,640 mA 1
≥
tRC (MIN.)
tRC
, IO = 0 mA -A10 2,640
/CAS latency = 3 -A80 2,640
-A10 2,640
Precharge standby current in I
★
power down mode I
Precharge standby current in I
CC2
P CKE ≤ V
CC2
PS CKE ≤ V
CC2
N CKE
IL (MAX.)
IL (MAX.)
≥
VIH (MIN.)
, tCK = 15 ns 286 mA
∞
, tCK =
, tCK = 15 ns, /CS
≥ VIH (MIN.)
, 970 mA
116
non power down mode Input signals are changed one time during 30 ns.
CC2
I
NS CKE
≥
VIH (MIN.)
, tCK = ∞ , 368
Input signals are stable.
Active standby current i n I
power down mode I
Active standby current i n I
CC3
P CKE ≤ V
CC3
PS CKE ≤ V
CC3
N CKE
≥
VIH (MIN.)
IL (MAX.)
, tCK = 15 ns 430 mA
IL (MAX.)
∞
, tCK =
, tCK = 15 ns, /CS
≥
VIH (MIN.)
, 1,330 mA
224
non power down mode Input signals are changed one time during 30 ns.
CC3
I
NS CKE
≥
VIH (MIN.)
, tCK = ∞ , 800
Input signals are stable.
Operating current I
CC4tCK
≥
tCK (MIN.)
, IO = 0 mA /CAS latency = 2 -A 80 2,730 m A 2
(Burst mode) -A10 2,370
/CAS latency = 3 -A80 3,180
-A10 2,820
★
CBR (Auto) Refresh current I
CC5tRC
★
★
★
Self refresh current I
Input leakage current I
CC6
I (L)
≥
tRC (MIN.)
/CAS latency = 2 -A80 4,980 mA 3
-A10 4,980
/CAS latency = 3 -A80 4,980
-A10 4,980
CKE ≤ 0.2 V 322 mA
VI = 0 to 3.6 V, All other pins not under test = 0 V –20 +20
µ
A
Input leakage current (CKE0) –40 +40
Input leakage current
(/CS0-/CS3, DQMB0-DQMB7)
Output leakage current I
High level output voltage V
Low level output voltage V
O (L)DOUT
OHIO
= –4.0 mA 2.4 V
OLIO
= +4.0 mA 0.4 V
is disabled, VO = 0 to 3.6 V–3+3
–10 +10
µ
A
Notes 1.
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open.
I
In addition to this, I
CC4
2
.I
depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, I
CC5
3.
I
is measured on condition that addresses are changed only one time during t
CC1
is measured on condition that addresses are changed only one time during t
CC4
is measured on condition that addresses are changed only one time during t
CK (MIN.)
Data Sheet M14460EJ2V0DS00
CK (MIN.)
.
CK (MIN.)
.
.
7
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
★
Parameter Value Unit
AC high level input voltage / low level input vol t age 2.4 / 0.4 V
Input timing m easurement reference level 1.4 V
Transition time (Input rise and fall time) 1 ns
Output timing m easurement reference level 1.4 V
t
CK
t
CH
2.4 V
CLK
Input
1.4 V
0.4 V
2.4 V
1.4 V
0.4 V
t
SETUPtHOLD
t
AC
t
OH
MC-4564EC726
t
CL
Output
8
Data Sheet M14460EJ2V0DS00
MC-4564EC726
Synchronous Characteristics
Parameter Symbol -A80 -A10 Unit Note
MIN. MAX. MIN. MAX.
Clock cycle time
/CAS latency = 3
/CAS latency = 2
Access time from CLK
/CAS latency = 3
/CAS latency = 2
Input clock frequency 50 125 50 100 MHz
Input CLK duty cycle 40 60 40 60 %
Data-out hold time
/CAS latency = 3
/CAS latency = 2
Data-out low-impedance tim e t
Data-out high- impedance time
/CAS latency = 3
/CAS latency = 2
Data-in setup time t
Data-in hold time t
Address setup time t
Address hold time t
CKE setup time t
CKE hold time t
CKE setup time (P ower down exit) t
Command (/CS0 - /CS 3, /RAS, /CAS, /WE, t
DQMB0 - DQMB7) setup time
Command (/CS0 - /CS 3, /RAS, /CAS, /WE, t
DQMB0 - DQMB7) hold time
CK3
t
CK2
t
AC3
t
AC2
t
OH3
t
OH2
t
LZ
HZ3
t
HZ2
t
DS
DH
AS
AH
CKS
CKH
CKSP
CMS
CMH
8 (125 MHz) 10 (100 MHz) ns
10 (100 MHz) 13 (77 MHz) ns
66ns1
67ns1
33ns1
33ns1
00ns
3636ns
3637ns
22ns
11ns
22ns
11ns
22ns
11ns
22ns
22ns
11ns
Note 1.
Remark
Output load
Z = 50 Ω
Output
These specifications are applied to the monolithic device.
Data Sheet M14460EJ2V0DS00
50 pF
9
Asynchronous Characteristics
Parameter Symbol -A80 -A10 Unit Note
ACT to REF/ACT comm and peri od (Operat i on) t
REF to REF/ACT command period (Refresh) t
ACT to PRE command period t
PRE to ACT command period t
Delay time ACT to READ/WRITE command t
ACT(one) to ACT(another) command period t
Data-in to PRE command period t
Data-in to ACT(REF) command
period (Auto precharge)
Mode register set cycle time t
Transition time t
Refresh time (4,096 refres h cycles) t
/CAS latency = 3
/CAS latency = 2
t
t
RC
RC1
RAS
RP
RCD
RRD
DPL
DAL3
DAL2
RSC
T
REF
MC-4564EC726
MIN. MAX. MIN. MAX.
70 70 ns
70 78 ns
48 120,000 50 120,000 ns
20 20 ns
20 20 ns
16 20 ns
−
1CLK+8
20 20 ns
20 20 ns
22CLK
0.530130ns
−
1CLK+10 ns
64 64 ms
10
Data Sheet M14460EJ2V0DS00
MC-4564EC726
Serial PD (1/2)
Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
0 Defines the num ber of bytes written into
serial PD memory
1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes
2 Fundamental memory type 04H 0 0 0 0 0 1 0 0 SDRAM
3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows
4 Number of columns 0BH 0 0 0 0 1 0 1 1 11 columns
5 Number of banks 02H 0 0 0 0 0 0 1 0 2 bank
6 Data width 48H 0 1 0 0 1 0 0 0 72 bit s
7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0
8 Voltage interface 01H 0 0 0 0 0 0 0 1 LVTTL
9 CL = 3 Cycle time -A80 80H 1 0 0 0 0 0 0 0 8 ns
-A10 A0H 1 0 1 0 0 0 0 0 10 ns
10 CL = 3 Ac c ess time -A80 60H 0 1 1 0 0 0 0 0 6 ns
-A10 60H 0 1 1 0 0 0 0 0 6 ns
11 DIMM confi gurat i on type 02H 0 0 0 0 0 0 1 0 ECC
12 Refres h rat e/type 80H 1 0 0 0 0 0 0 0 Normal
13SDRAM width 04H00000100x4
14 Error c hecking SDRAM width 04H 0 0 0 0 0 1 0 0 x4
15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 cl ock
16 Burs t l ength supported 8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F
17 Num ber of banks on each SDRAM 04H 0 0 0 0 0 1 0 0 4 banks
18 /CAS latency supported 06H 0 0 0 0 0 1 1 0 2, 3
19 /CS l atency supported 01H 0 0 0 0 0 0 0 1 0
20 /WE latency support ed 01H 0 0 0 0 0 0 0 1 0
21 SDRAM module attributes 1FH 0 0 0 1 1 1 1 1 Registered
22 SDRAM device attributes : General 0EH 0 0 0 0 1 1 1 0
23 CL = 2 Cycle time -A80 A0H 1 0 1 0 0 0 0 0 10 ns
-A10 D0H 1 1 0 1 0 0 0 0 13 ns
24 CL = 2 Ac c ess time -A80 60H 0 1 1 0 0 0 0 0 6 ns
-A10 70H 0 1 1 1 0 0 0 0 7 ns
25-26 00H 0 0 0 0 0 0 0 0
RP(MIN.)
27 t
-A80 14H 0 0 0 1 0 1 0 0 20 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
RRD(MIN.)
28 t
-A80 10H 0 0 0 1 0 0 0 0 16 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
RCD(MIN.)
29 t
-A80 14H 0 0 0 1 0 1 0 0 20 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
RAS(MIN.)
30 t
-A80 30H 0 0 1 1 0 0 0 0 48 ns
-A10 32H 0 0 1 1 0 0 1 0 50 ns
31 Module bank dens i t y 40H 0 1 0 0 0 0 0 0 256M bytes
80H 1 0 0 0 0 0 0 0 128 bytes
Data Sheet M14460EJ2V0DS00
11
MC-4564EC726
Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
32 Com mand and address signal input
setup time
33 Com mand and address signal input hold
time
34 Data s i gnal i nput setup time 20H 0 0 1 0 0 0 0 0 2 ns
35 Data s i gnal i nput hol d time 10H 0 0 0 1 0 0 0 0 1 ns
36-61 00H 0 0 0 0 0 0 0 0
62 SPD revi sion 12H 0 0 0 1 0 0 1 0 1.2 A
63 Checksum for bytes 0 - 62 -A80 3BH 0 0 1 1 1 0 1 1
-A10A1H10100001
64-71 Manufacture’s JEDEC ID code
72 Manufact uri ng l ocation
73-90 Manufacture’s P/N
91 Revis i on Code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126 Intel specification frequency 64H 0 1 1 0 0 1 0 0 100 MHz
127 Intel specification /CAS -A80 87H 1 0 0 0 0 1 1 1
latency support -A10 85H 1 0 0 0 0 1 0 1
20H001000002 ns
10H000100001 ns
(2/2)
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E).
12
Data Sheet M14460EJ2V0DS00
★
Package Drawing
168-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
M1 (AREA B)
Y
MC-4564EC726
Z
N
R
M2 (AREA A)
Q
M
L
A
J
B
I
H
K
C
G
B
(OPTIONAL HOLES)
S
T
U
E
D
A1 (AREA A)
ITEM MILLIMETERS
A
133.35
133.35±0.13
A1
11.43
B
C 36.83
6.35D
D1
detail of A part
W
V
detail of B part
D2
P
X
D1
2.0
D2
3.125
E 54.61
G 6.35
H 1.27 (T.P.)
I
8.89
J
24.495
42.18
K
17.78
L
M 43.18±0.13
23.40M1
M2
19.78
N
6.35 MAX.
P 1.0
Q R2.0
R 4.0±0.10
S
φ
3.0
T
1.27±0.1
U 4.0 MIN.
V 0.2±0.15
W 1.0±0.05
X
2.54±0.10
Y
3.0 MIN.
Z
3.0 MIN.
M168S-50A112
Data Sheet M14460EJ2V0DS00
13
[MEMO]
MC-4564EC726
14
Data Sheet M14460EJ2V0DS00
MC-4564EC726
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
DD
pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
or GND with a resistor, if it is considered to have a possibility of
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M14460EJ2V0DS00
15
MC-4564EC726
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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