
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
2SK3307
DESCRIPTION
The 2SK3307 is N-channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
•Super low on-state resistance:
= 9.5 mΩ MAX. (VGS = 10 V, ID = 35 A)
DS(on)1
R
= 14 mΩ MAX. (VGS = 4.0 V, ID = 35 A)
RDS(on)2
: C
•Low Ciss
= 4650 pF TYP.
iss
•Built-in gate protection diode
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage V
Gate to Source Voltage V
Drain Current (DC) I
Drain Current (pulse)
Total Power Dissipation (T
Total Power Dissipation (T
Channel Temperature T
Storage Temperature T
Single Avalanche Current
Single Avalanche Energy
Note1
C
= 25°C) P
A
= 25°C) P
Note2
Note2
DSS
GSS(AC)
D(DC)
D(pulse)
I
stg
AS
I
AS
E
±20 V
±70 A
±280 A
T1
T2
ch
120 W
3.0 W
150 °C
–55 to +150 °C
202 mJ
ORDERING INFORMATION
PART NUMBER PACKAGE
2SK3307 TO-3P
(TO-3P)
60 V
45 A
s, Duty cycle ≤ 1%
Notes 1. PW ≤ 10
2. Starting T
µ
= 25°C, RG = 25 Ω, VGS = 20 V → 0 V
ch
THERMAL RESISTANCE
Channel to Case R
Channel to Ambient R
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D14129EJ3V0DS00 (3rd edition)
Date Published March 2001 NS CP(K)
Printed in Japan
th(ch-C)
th(ch-A)
1.04 °C/W
41.7 °C/W
The mark ★ shows major revised points.
©
1999, 2000

ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
2SK3307
Zero Gate Voltage Drain Current I
Gate Leakage Current I
Gate Cut-off Voltage V
DSS
VDS = 60 V, VGS = 0 V10
GSS
VGS = ±20 V, VDS = 0 V ±10
GS(off)VDS
= 10 V, ID = 1 mA 1.5 2.0 2.5 V
A
µ
A
µ
Forward Transfer Admittance | yfs |VDS = 10 V, ID = 35 A3047S
Drain to Source On-state Resi stance R
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DS(on)1VGS
DS(on)2VGS
R
iss
oss
rss
d(on)ID
r
d(off)
f
G
GS
GD
F(S-D)IF
rr
rr
= 10 V, ID = 35 A7.59.5mΩ
= 4.0 V, ID = 35 A 10.5 14 mΩ
VDS = 10 V, VGS = 0 V, f = 1 MHz 4650 pF
780 pF
380 pF
= 35 A, V
RG = 10
GS(on)
= 10 V, VDD = 30 V, 90 ns
Ω 1260 ns
270 ns
370 ns
ID = 70 A , VDD = 48 V, VGS = 10 V90nC
14 nC
24 nC
= 70 A, VGS = 0 V1.0V
IF = 70 A, VGS = 0 V, 60 ns
di/dt = 100 A/µs 110 nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
L
V
DD
PG.
RG = 25 Ω
50 Ω
VGS = 20 → 0 V
DSS
BV
I
AS
V
I
D
V
DD
DS
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
IG = 2 mA
50 Ω
R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
R
R
PG.
V
GS
0
τ = 1 s
Duty Cycle ≤ 1%
G
V
DD
τ
µ
V
GS
Wave Form
I
D
Wave Form
V
GS
10%
0
I
90%
D
10%
0
t
d(on)
r
t
on
t
90%
V
GS
(on)
90%
I
D
10%
t
d(off)
t
f
t
off
2
Data Sheet D14129EJ3V0DS

TYPICAL CHARACTERISTICS (TA = 25°C )
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
T
ch
- Channel Temperature -
˚C
dT - Percentage of Rated Power - %
04020 60 100 14080 120 160
100
80
60
40
20
0
TC - Case Temperature - ˚C
P
T
- Total Power Dissipation - W
0
0
8020 40 60 100 140120 160
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
25
50
75
100
125
175
150
FORWARD BIAS SAFE OPERATING AREA
1 10 100
I
D
- Drain Current - A
0.1
V
DS
- Drain to Source Voltage - V
1000
100
10
1
0.1
DC
R
DS(on)
Limited
(at V
GS
= 10 V)
TC = 25˚C
Single Pulse
Power Dissipation
Limited
10
ms
1
ms
100
µs
PW
=
10
µs
ID(pulse)
★
2SK3307
1000
100
10
1
0.1
- Transient Thermal Resistance - ˚C/W
th(t)
r
0.01
µ
10
100
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1 m 10 m 100 m 1 10 100 1000
µ
PW - Pulse Width - s
Data Sheet D14129EJ3V0DS
Single Pulse
R
R
th(ch-A)
th(ch-C)
= 41.7 ˚C/W
= 1.04 ˚C/W
3

2SK3307
FORWARD TRANSFER CHARACTERISTICS
V
GS
- Gate to Source Voltage - V
I
D
- Drain Current - A
Pulsed
1234
5
6
V
DS
= 10 V
10
1
0.1
100
1000
TA = −50˚C
25˚C
75˚C
150˚C
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
V
DS
- Drain to Source Voltage - V
I
D
- Drain Current - A
4
300
250
200
150
100
50
0
2
Pulsed
0
3
1
V
GS
=10 V
4.0 V
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
I
D
- Drain Current - A
| y
fs
| - Forward Transfer Admittance - S
0.1
1
10
100
10 100
0.1
1
Pulsed
TA = 150˚C
75˚C
25˚C
−50˚C
V
DS
= 10 V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
V
GS
- Gate to Source Voltage - V
R
DS(on)
- Drain to Source On-state Resistance - mΩ
0
0
5101015 20
Pulsed
20
ID = 35 A
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
I
D
- Drain Current - A
R
DS(on)
- Drain to Source On-state Resistance - mΩ
10
10
0.1 1
20
30
100
1000
Pulsed
0
10 V
V
GS
= 4.0 V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
T
ch
- Channel Temperature - ˚C
V
GS(off)
- Gate Cut-off Voltage - V
0.5
VDS = 10 V
I
D = 1 mA
1
1.5
2
2.5
3
−50
0 50 100 150
0
4
Data Sheet D14129EJ3V0DS

2SK3307
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
T
ch
- Channel Temperature - ˚C
R
DS(on)
- Drain to Source On-state Resistance - mΩ
0
−50
5
10
15
0
50
100 150
I
D
= 35 A
20
25
10 V
V
GS
= 4.0 V
Pulsed
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
0.8 1.2 1.6
I
SD
- Diode Forward Current - A
0
2.0
VSD - Source to Drain Voltage - V
0.4
Pulsed
1
10
100
1000
V
GS
= 10 V
V
GS
= 0 V
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
VDS - Drain to Source Voltage - V
C
iss
, C
oss
, C
rss
- Capacitance - pF
100
0.1
1000
10000
100000
1
10
100
VGS = 0 V
f = 1 MHz
C
oss
C
rss
C
iss
SWITCHING CHARACTERISTICS
I
D
- Drain Current - A
t
d(on)
, t
r
, t
d(off)
, t
f
- Switching Time - ns
100
10
10.1
1000
10000
10 100
t
f
t
r
t
d(on)
t
d(off)
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
I
F
- Drain Current - A
t
rr
- Reverse Recovery Time - ns
di/dt = 100 A/ s
V
GS
= 0 V
1
0.1
10
1.0 10 100
1000
100
µ
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
V
GS
- Gate to Source Voltage - V
Q
G
- Gate Charge - nC
V
DS
- Drain to Source Voltage - V
00
0
40 6020 80 100 120 140 160
20
40
60
80
100
2
4
V
DS
6
10
8
V
GS
V
DD
= 48 V
30 V
12 V
I
D
= 70 A
Data Sheet D14129EJ3V0DS
5

2SK3307
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
L - Inductive Load - H
I
AS
- Single Avalanche Current - A
10
100
1000
1
m10
m
V
DD
= 30 V
R
G
= 25 Ω
V
GS
= 20 V → 0 V
IAS = 45 A
10
µ
100
µ
1
E
AS
=
202
mJ
SINGLE AVALANCHE ENERGY
DERATING FACTOR
Starting T
ch - Starting Channel Temperature - ˚C
Energy Derating Factor - %
25 50
75 100
160
140
120
100
80
60
40
20
0
125 150
VDD = 30 V
R
G
= 25 Ω
V
GS
= 20 V → 0 V
I
AS
≤ 45 A
6
Data Sheet D14129EJ3V0DS

PACKAGE DRAWING (Unit: mm)
TO-3P (MP-88)
2SK3307
Remark
15.7 MAX. 3.2±0.2
6.0 1.03.0±0.2
20.0±0.219 MIN.
2.2±0.2
1 2 3
5.45 5.45
4
1.0±0.2
4.7 MAX.
1.5
7.0
4.5±0.2
2.8±0.10.6±0.1
1.Gate
2.Drain
3.Source
4.Fin (Drain)
EQUIVALENT CIRCUIT
Drain
Body
Gate
Gate
Protection
Diode
Source
Diode
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
Data Sheet D14129EJ3V0DS
7

2SK3307
•
The information in this document is current as of March, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
•
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
•
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
•
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M8E 00. 4