DATA SHEET
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
MOS FIELD EFFECT TRANSISTOR
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
2SK3296
DESCRIPTION
The 2SK3296 is N-Channel MOS FET device that features a
low on-state resistance and excellent switching characteristics,
designed for low voltage high current applications such as
DC/DC converter with synchronous rectifier.
FEATURES
• 4.5 V drive available
• Low on-state resistance
DS(on)1
= 12 mΩ MAX. (VGS = 10 V, ID = 18 A)
R
• Low gate charge
QG = 30 nC TYP. (ID = 35 A, VDD = 16 V, VGS = 10 V)
• Built-in gate protection diode
• Surface mount device available
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V) V
DS
Gate to Source Voltage (V
Drain Current (DC) (T
Drain Current (Pulse)
= 0 V) V
C
= 25°C) I
Note
DSS
GSS
D(DC)
D(pulse)
I
20 V
±20 V
±35 A
±140 A
ORDERING INFORMATION
PART NUMBER PACKAGE
2SK3296 TO-220AB
2SK3296-S TO-262
2SK3296-ZK TO-263(MP-25ZK)
2SK3296-ZJ TO-263(MP-25ZJ)
A
Total Power Dissipation (T
= 25°C) P
Total Power Dissipation (TC = 25°C) P
Channel Temperature T
Storage Temperature T
Note
PW ≤ 10 µs, Duty Cycle ≤ 1%
Document No. D14063EJ2V0DS00 (2nd edition)
Date Published May 2001 NS CP(K)
Printed in Japan
T1
T2
ch
stg
The mark
1.5 W
40 W
150 °C
−55 to +150 °C
shows major revised points.
©
1999, 2000
ELECTRICAL CHARACTERISTICS(TA = 25°C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Drain Leakage Current I
Gate Leakage Current I
DSS
GSS
2SK3296
VDS = 20 V, VGS = 0 V 10
VGS = ±20 V, VDS = 0 V
±
10
A
µ
A
µ
R
d(on)
r
d(off)
f
rr
GS(off)
DS(on)1
DS(on)2
iss
oss
rss
G
GS
GD
F(S-D)
rr
VDS = 10 V, ID = 1 mA 1.0 2.5 V
DS
= 10 V, ID = 18 A 9.0 S
VGS = 10 V, ID = 18 A 8.5 12
VGS = 4.5 V, ID = 18 A 12 19
VDS = 10 V 1300 pF
VGS = 0 V 570 pF
f = 1 MHz 300 pF
VDD = 10 V , ID = 18 A 70 ns
GS(on)
V
= 10 V 1220 ns
RG = 10
Ω
VDD = 16 V 30 nC
VGS = 10 V 4.5 nC
ID = 35 A 8.0 nC
IF = 35 A, VGS = 0 V 1.0 V
IF = 35 A, VGS = 0 V 35 ns
di/dt = 100 A/µs
Gate Cut-off Voltage V
Forward Transfer Admittance | yfs |V
Drain to Source On-state Resistance R
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
m
m
100 ns
180 ns
23 nC
Ω
Ω
TEST CIRCUIT 1 SWITCHING TIME
D.U.T.
L
R
G
PG.
V
GS
0
τ = 1 s
Duty Cycle ≤ 1%
R
V
DD
τ
µ
GS
V
Wave Form
I
D
Wave Form
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
V
GS
10%
0
I
D
90%
10%
0
t
d(on)
r
t
on
t
90%
V
GS
(on)
PG.
90%
I
D
t
d(off)
10%
t
f
t
off
IG = 2 mA
50 Ω
R
L
V
DD
2
Data Sheet D14063EJ2V0DS
TYPICAL CHARACTERISTICS (TA = 25°C)
2SK3296
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
160
140
V
GS
120
=10 V
7.0 V
100
80
60
- Drain Current - A
D
40
I
20
0
0
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
1
V
DS
- Drain to Source Voltage - V
2
3.0
2.5
2.0
1.5
4.5 V
Pulsed
VDS = 10 V
ID = 1 mA
FORWARD TRANSFER CHARACTERISTICS
1000
100
T
ch
= −50˚C
10
0.1
- Drain Current - A
D
I
−25˚C
25˚C
75˚C
125˚C
1
150˚C
0.01
V
DS
= 10 V
0.001
3
012 3
V
GS
- Gate to Source Voltage - V
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
Pulsed
4
56
100
T
ch
= −50˚C
−25˚C
25˚C
75˚C
10
150˚C
1.0
0.5
- Gate to Source Cut-off Voltage - V
0
GS(off)
−50
V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
50
40
0 50 100 150
T
ch
- Channel Temperature - ˚C
Pulsed
ID = 28 A
18 A
30
7 A
20
10
- Drain to Source On-state Resistance - mΩ
DS(on)
R
0
0
V
GS
- Gate to Source Voltage - V
1051520
1
| - Forward Transfer Admittance - S
fs
0.1
| y
0.1
50
Pulsed
1 10 100
D
- Drain Current - A
I
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
40
30
20
V
GS
= 4.5 V
7.0 V
10 V
10
- Drain to Source On-state Resistance - mΩ
DS(on)
R
0
101
I
D
- Drain Current - A
DS
= 10 V
V
Pulsed
1000100
Data Sheet D14063EJ2V0DS
3
2SK3296
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
25
I
D
= 18 A
Pulsed
20
V
GS
= 4.5 V
15
7.0 V
10
10 V
5
0
- Drain to Source On-state Resistance - mΩ
DS(on)
R
−50
0
T
ch
- Channel Temperature - ˚C
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
50
100 150
10000
1000
- Capacitance - pF
rss
, C
oss
, C
iss
C
100
0.1
1 10 100
VDS - Drain to Source Voltage - V
VGS = 0 V
f = 1 MHz
C
iss
C
oss
C
rss
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
1000
Pulsed
V
GS
100
= 10 V
4.5 V
10
0 V
1
0.1
- Diode Forward Current - A
SD
I
0.01
0
0.6 0.80.40.2
VSD - Source to Drain Voltage - V
SWITCHING CHARACTERISTICS
10000
1000
- Switching Time - ns
f
, t
d(off)
, t
r
, t
d(on)
t
100
10
5
t
d(off)
t
d(on)
10.1
I
D
- Drain Current - A
t
f
VDD = 10 V
V
GS
= 10 V
G
= 10 Ω
R
1.6
1.2 1.41
t
r
10 100
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
1000
100
10
- Reverse Recovery Time - ns
rr
t
1
0.1
I
4
di/dt = 100 A/ s
GS
V
1 10 100
SD
- Diode Forward Current - A
µ
= 0 V
Data Sheet D14063EJ2V0DS
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
20
15
V
DD
= 16 V
10 V
4 V
ID = 35 A
10
V
GS
5
- Drain to Source Voltage - V
DS
V
0
0
V
DS
10 20 30 40
Q
G
- Gate Charge - nC
16
12
8
4
- Gate to Source Voltage - V
GS
V
0
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
T
ch
- Channel Temperature -
˚C
dT - Percentage of Rated Power - %
04020 60
100
14080 120 160
0
20
40
60
80
100
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
50
40
30
20
- Total Power Dissipation - W
10
T
P
0
0
TC - Case Temperature - ˚C
2SK3296
8020 40 60 100 140120 160
1000
100
10
- Drain Current - A
D
I
1
FORWARD BIAS SAFE OPERATING AREA
I
DS(on)
R
@V
(
TC = 25°C
ited
Lim
= 10V)
GS
I
D(DC)
Power Dissipation Limited
D(pulse)
10ms
PW = 10 s
µ
1
0
0
µ
s
300 s
µ
1ms
3m
s
DC
Single Pulse
1 10 1000.1
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
100
10
1
R
R
th(ch-A)
th(ch-C)
= 83.3˚C/W
= 3.13˚C/W
0.1
- Transient Thermal Resistance - ˚C/W
th(t)
r
0.01
10
µ
100
Single Pulse
1 m 10 m 100 m 1 10 100 1000
µ
PW - Pulse Width - sec
Data Sheet D14063EJ2V0DS
5
PACKAGE DRAWINGS (Unit : mm)
2SK3296
1)TO-220AB (MP-25)
10.6 MAX.
10.0
3.0±0.3
4
2 3
1
1.3±0.2
0.75±0.1
2.54 TYP.
3)TO-263 (MP-25ZK)
10.0±0.2
No plating
0.4
8.4 TYP.
φ
3.6±0.2
5.9 MIN.6.0 MAX.
2.54 TYP.
4
15.5 MAX.12.7 MIN.
0.5±0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
1.35±0.3
4.8 MAX.
4.45±0.2
1.3±0.2
2.8±0.2
1.3±0.2
2)TO-262
(10)
4
2 3
1
1.3±0.2
0.75±0.3
2.54 TYP. 2.54 TYP.
4)TO-263 (MP-25ZJ)
(10)
4
1.0±0.5
8.5±0.2
12.7 MIN.
4.8 MAX.
0.5±0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
4.8 MAX.
1.3±0.2
2.8±0.2
1.3±0.2
8.0 TYP.
2.54
123
EQUIVALENT CIRCUIT
Drain
Body
Gate
Gate
Protection
Diode
Source
Diode
0.7±0.15
9.15±0.2
2.5
15.25±0.5
0.5±0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
Remark
0.025 to
0 to 8
0.25
0.25
1.0±0.5
8.5±0.2
1.4±0.2
2.45±0.25
o
0.7±0.2
2.54 TYP. 2.54 TYP.
123
(0.5R)
5.7±0.4
(0.8R)
1.Gate
2.Drain
3.Source
4.Fin (Drain)
2.8±0.2
The diode connected between the gate and source of the transistor
serves as a protector against ESD.
When this device actually used, an additional protection circuit is
externally required if a voltage exceeding the rated voltage may be
applied to this device.
0.5±0.2
6
Data Sheet D14063EJ2V0DS
[MEMO]
2SK3296
Data Sheet D14063EJ2V0DS
7
2SK3296
•
The information in this document is current as of May, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
•
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third parties by or arising from the use of NEC semiconductor products listed in this document or any other
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•
Descriptions of circuits, software and other related information in this document are provided for illustrative
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parties arising from the use of these circuits, software and information.
•
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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redundancy, fire-containment, and anti-failure features.
•
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M8E 00. 4
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