NEC 2SJ495 Datasheet
DATA SHEET
Gate
Drain
Body
Diode
Gate Protection
Diode
Source
MOS FIELD EFFECT POWER TRANSISTORS
2SJ495
SWITCHING P-CHANNEL POWER MOS FET INDUSTRIAL USE
DESCRIPTION
This product is P-Channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
• Super Low On-State Resistance
DS(on)1 = 30 mΩ MAX. (VGS = –10 V, ID = –15 A)
R
RDS(on)2 = 56 mΩ MAX. (VGS = –4 V, ID = –15 A)
• Low Ciss Ciss = 4120 pF TYP.
• Built-in Gate Protection Diode
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage VDSS –60 V
Gate to Source Voltage* VGSS(AC) m20 V
Gate to Source Voltage VGSS(DC) –20, 0 V
Drain Current (DC) I
Drain Current (pulse)** ID(pulse) m120 A
Total Power Dissipation (TC = 25°C) PT 35 W
Total Power Dissipation (T
Channel Temperature Tch 150 °C
Storage Temperature Tstg –55 to +150 °C
*f = 20 kHz, Duty Cycle ≤ 10% (+Side)
µ
**PW ≤ 10
s, Duty Cycle ≤ 1%
A = 25°C) PT 2.0 W
D(DC) m30 A
PACKAGE DIMENSIONS
(in millimeter)
10.0 ± 0.3 4.5 ± 0.2
15.0 ± 0.3
0.7 ± 0.1
2.54 2.54
3.2 ± 0.2
3 ± 0.1
4 ± 0.2
1.3 ± 0.2
1.5 ± 0.2
213
2.7 ± 0.2
12.0 ± 0.213.5 MIN.
2.5 ± 0.1
0.65 ± 0.1
1. Gate
2. Drain
3. Source
Document No. D11267EJ2V0DS00 (2nd edition)
Date Published November 1997 N
Printed in Japan
THERMAL RESISTANCE MP-45F (ISOLATED TO-220)
Channel to Case Rth(ch-c) 3.57 °C/W
Channel to Ambient Rth(ch-A) 62.5 °C/W
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this deveice
acutally used, an addtional protection circiut is externally required if a voltage exceeding the rated voltage may be applied
to this device.
©
1997
ELECTRICAL CHARACTERISTICS (TA = 25°C)
2SJ495
CHARACTERISTICS
SYMBOL
TEST CONDITIONS MIN. TYP. MAX. UNIT
Drain to Source On–state Resistance RDS(on)1 VGS = –10 V, ID = –15 A 24 30 mΩ
RDS(on)2 VGS = –4 V, ID = –15 A 38 56 mΩ
Gate to Source Cutoff Voltage VGS(off) VDS = –10 V, ID = –1 mA –1.0 –1.5 –2.0 V
Forward Transfer Admittance | yfs |VDS = –10 V, ID = –15 A 12 24 S
Drain Leakage Current IDSS VDS = –60 V, VGS = 0 –10
Gate to Source Leakage Current IGSS VGS = m 20 V, VDS = 0 m10
µ
µ
Input Capacitance Ciss VDS = –10 V 4120 pF
Output Capacitance COSS VGS = 0 1750 pF
Reverse Transfer Capacitance Crss f = 1 MHz 580 pF
Turn-On Delay Time td(on) ID = –15 A 40 ns
Rise Time tr VGS(on) = –10 V 220 ns
Turn-Off Delay Time td(off) VDD = –30 V 600 ns
Fall Time tf RG = 10 Ω 380 ns
Total Gate Charge QG ID = –30 A 140 nC
Gate to Source Charge QGS VDD = –48 V 12 nC
Gate to Drain Charge QGD VGS = –10 V 46 nC
Body Diode Forward Voltage VF(S-D) IF = 30 A, VGS = 0 0.8 1.5 V
Reverse Recovery Time trr IF = 30 A, VGS = 0 160 ns
Reverse Recovery Charge Qrr di/dt = 100 A/µs 400 nC
A
A
Test Circuit 1 Switching Time Test Circuit 2 Gate Charge
D.U.T.
G
= 2 mA
I
50 Ω
PG.
GS
V
0
t
t = 1 s
µ
Duty Cycle ≤ 1%
D.U.T.
G
R
RG = 10 Ω
R
L
DD
V
V
GS
Wave Form
D
I
Wave Form
V
GS
V
90 %
t
on
trt
D
I
GS(on)
d(off)
10 %
D
I
D
10 % 10 %
0
t
d(on)
90 %
t
off
90 %
t
f
PG.
R
L
DD
V
2
2SJ495
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
dT - Percentage of Rated Power - %
0
20 40 60 80 100 120 140 160
T
C
- Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
–1000
–100
–10
- Drain Current - A
D
I
TC = 25°C
Single Pulse
–1
–0.1
Limited
=10 V)
DS(on)
GS
R
(at V
I
D(DC)
Power Dissipation Limited
–1 –10 –100
V
DS -
Drain to Source Voltage - V
I
D(pulse)
DC
1 ms
10 ms
100 ms
500 s
µ
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
35
30
25
20
15
10
- Total Power Dissipation - W
T
5
P
0
20
40 60 80 100 120 140 160
T
C
- Case Temperature - °C
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
–125
V
GS
–100
–75
–50
- Drain Current - A
D
I
–25
0
V
V
GS
= –4 V
–2
DS
- Drain to Source Voltage - V
= –10 V
–4
–6
Pulsed
–8
FORWARD TRANSFER CHARACTERISTICS
–1000
T
ch
= –25°C
–100
25°C
125°C
–10
- Drain Current - A
D
I
–1
0
–2
GS
- Gate to Source Voltage - V
V
–4
Pulsed
V
DS
= –10 V
–6 –8
3
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