NEC 2SJ494 Datasheet
DATA SHEET
MOS FIELD EFFECT POWER TRANSISTORS
2SJ494
SWITCHING P-CHANNEL POWER MOS FET INDUSTRIAL USE
DESCRIPTION
This product is P-Channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
• Super Low On-State Resistance
DS(on)1
R
= 50 m: Max. (VGS = –10 V, ID = –10 A)
DS(on)2
R
= 88 m: Max. (VGS = –4 V, ID = –10 A)
• Low C
issCiss
= 2360 pF Typ.
• Built-in Gate Protection Diode
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage V
Gate to Source Voltage* V
Gate to Source Voltage V
Drain Current (DC) I
Drain Current (pulse)** I
Total Power Dissipation (TC = 25 °C) P
Total Power Dissipation (TA = 25 °C) P
Channel Temperature T
Storage Temperature T
* f = 20 kHz, Duty Cycle d 10% (+Side)
** PW d 10 Ps, Duty Cycle d 1%
DSS
GSS (AC)
GSS (DC)
D (DC)
D (pulse)
T
T
ch
stg
THERMAL RESISTANCE
Channel to Case R
Channel to Ambient R
th (ch-C)
th (ch-A)
3.57 °C/W
62.5 °C/W
–60 V
–
+20 V
–20, 0 V
–
+20 A
–
+80 A
35 W
2.0 W
150 °C
–55 to +150 °C
PACKAGE DIMENSIONS
(in millimeter)
10.0±0.3
15.0±0.3
2.54
123
3.2±0.2
3±0.1
4±0.2
13.5 MIN. 12.0±0.2
1.3±0.20.7±0.1
1.5±0.2
2.54
ISOLATED TO-220 (MP-45F)
Gate
Gate Protection
Diode
4.5±0.2
2.7±0.2
2.5±0.1
0.65±0.1
1. Gate
2. Drain
3. Source
Drain
Body
Diode
Source
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this
device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage
may be applied to this device.
Document No. D11266EJ2V0DS00 (2nd edition)
Date Published January 1998 N CP(K)
Printed in Japan
1998©
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
2SJ494
R
DSS
GSS
d(on)
r
d(off)
f
rr
DS(on)1
DS(on)2
GS (off)
iss
oss
rss
G
GS
GD
F(S-D)
rr
VGS = –10 V, ID = –10 A 39 50 m:
VGS = –4 V, ID = –10 A 61 88 m:
VDS = –10 V, ID = –1 mA –1.0 –1.5 –2.0 V
DS
= –10 V, ID = –10 A 8.0 15 S
VDS = –60 V, VGS = 0 –10
VGS = +20 V, VDS = 0 +10
VDS = –10 V
GS
V
= 0
f = 1 MHz
D
= –10 A
I
GS(on)
V
= –10 V
DD
V
= –30 V
G
R
= 10 :
D
= –20 A
I
DD
V
= –48 V
GS
V
= –10 V
IF = 20 A, VGS = 0 1.0 1.5 V
F
= 20 A, VGS = 0
I
di/dt = 100 A/
Drain to Source On-state Resistance R
Gate to Source Cutoff Voltage V
Forward Transfer Admittance | yfs |V
Drain Leakage Current I
Gate to Source Leakage Current I
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
P
A
P
A
2360 pF
1060 pF
350 pF
25 ns
160 ns
310 ns
240 ns
74 nC
12 nC
16 nC
130 ns
P
s
290 nC
Test Circuit 1 Switching Time Test Circuit 2 Gate Charge
PG.
VGS
0
t
µ
t = 1 s
Duty Cycle ≤ 1 %
RG
G = 10 Ω
R
D.U.T.
R
VDD
VGS
Wave Form
ID
Wave Form
VGS
10 %
0
ID
90 %
10 %
0
td (on) tr td (off) tf
ton toff
VGS (on)
ID
90 %
PG.
90 %
10 %
L
G
= 2 mA
I
50 Ω
D.U.T.
R
L
V
DD
2
2SJ494
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
dT - Percentage of Rated Power - %
0
20 40 60 80 100 120 140 160
C
- Case Temperature - ˚C
T
FORWARD BIAS SAFE OPERATING AREA
–1000
–100
RDS(on) Limited
(at VGS =10 V)
–10
- Drain Current - A
D
I
Tc = 25 ˚C
Single Pulse
–1
–0.1
DS
- Drain to Source Voltage - V
V
ID(pulse)
ID(DC)
Power Dissipation Limited
–1 –10 –100
500 s
µ
10 ms
100 ms
1 ms
DC
300 s
µ
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
35
30
25
20
15
10
- Total Power Dissipation - W
5
T
P
0
20
40 60 80 100 120 140 160
C
- Case Temperature - ˚C
T
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
–100
–80
VGS= –10 V
–60
–40
- Drain Current - A
D
I
–20
0
–4
DS
- Drain to Source Voltage - V
V
–8
V
GS
= –4 V
–12
Pulsed
–16
FORWARD TRANSFER CHARACTERISTICS
–1 000
T
ch
= –25 ˚C
–100
125 ˚C
–10
- Drain Current - A
D
I
–1
0
–5
GS
- Gate to Source Voltage - V
V
–10
25 ˚C
V
DS
Pulsed
= –10 V
–15
3
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