NEC 2SJ492-ZJ, 2SJ492-S, 2SJ492 Datasheet
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
SWITCHING
P-CHANNEL POWER MOS FET
INDUSTRIAL USE
2SJ492
DESCRIPTION
This product is P-Channel MOS Field Effect Transistor
designed for DC/DC converters and motor/lamp driver
circuits.
FEATURES
• Low on-state resistance
DS(on)1
R
= 100 mΩ (MAX.) (VGS = –10 V, ID = –10 A)
DS(on)2
R
= 185 mΩ (MAX.) (VGS = –4 V, ID = –10 A)
iss
• Low C
iss
: C
= 1210 pF (TYP.)
• Built-in gate protection diode
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
GSS(AC)
GSS(DC)
V
D(DC)
D(pulse)
I
I
E
DSS
T
T
ch
stg
AS
AS
Drain to Source Voltage (VGS = 0 V) V
Gate to Source Voltage (V
Gate to Source Voltage (VDS = 0 V)
DS
= 0 V) V
Note1
Drain Current (DC) I
Drain Current (pulse)
Total Power Dissipation (T
Total Power Dissipation (T
Note2
A
= 25°C) P
C
= 25°C) P
Channel Temperature T
Storage Temperature T
Single Avalanche Current
Single Avalanche Energy
Note3
Note3
ORDERING INFORMATION
PART NUMBER PACKAGE
2SJ492 TO-220AB
2SJ492-S TO-262
2SJ492-ZJ TO-263
–60 V
# 20
–20, 0 V
# 20
# 80
1.5 W
70 W
150 °C
–55 to +150 °C
–20 A
40 mJ
V
A
A
Notes 1.
2.
3.
kHz, Duty Cycle ≤ 10% (+Side)
f = 20
PW ≤ 10 µs, Duty Cycle ≤ 1 %
Starting Tch = 25 °C, RA = 25 Ω, VGS = –20 V → 0
THERMAL RESISTANCE
Channel to Case R
Channel to Ambient R
The information in this document is subject to change without notice.
Document No. D11264EJ1V0DS00 (1st edition)
Date Published December 1998 NS CP(K)
Printed in Japan
th(ch-C)
th(ch-A)
1.79 °C/W
83.3 °C/W
©
1998
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
2SJ492
Drain to Source On-state Resi stance R
Gate to Source Cut-off Voltage V
DS(on)1VGS
DS(on)2VGS
R
GS(off)VDS
= –10 V, ID = –10 A 70 100 m
= –4 V, ID = –10 A 120 185 m
= –10 V, ID = –1 mA –1.0 –1.5 –2.0 V
Forward Transfer Admittance | yfs |VDS = –10 V, ID = –10 A 5.0 12 S
Drain Leakage Current I
Gate to Source Leakage Current I
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DSS
VDS = –60 V, VGS = 0 V –10
VGS = #20 V, VDS = 0 V
GSS
iss
VDS = –10 V 1210 pF
oss
VGS = 0 V 520 pF
rss
f = 1 MHz 180 pF
d(on)ID
d(off)
GS
GD
F(S-D)IF
rr
= –10 A16ns
r
GS(on)
V
= –10 V 140 ns
VDD = –30 V90ns
f
G
RG = 10
Ω
80 ns
ID = –20 A42nC
VDD = –48 V8.0nC
VGS = –10 V10nC
= –20 A, VGS = 0 V1.0V
IF = –20 A, VGS = 0 V 125 ns
rr
di/dt = 50 A /
s 280 nC
µ
10
#
Ω
Ω
A
µ
A
µ
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
L
V
DD
PG
RG = 25 Ω
50 Ω
VGS = –20 → 0 V
DSS
BV
I
AS
V
I
D
DD
V
DS
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
IG = 2 mA
50 Ω
R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
R
G
τ
µ
R
RG = 10 Ω
V
DD
PG.
GS
V
0
τ = 1 s
Duty Cycle ≤ 1 %
V
GS
Wave Form
I
D
Wave Form
V
GS
10 %
0
90 %
D
I
10 %
0
t
r
t
d(on)
t
on
V
GS(on)
I
D
t
d(off)
t
off
90 %
90 %
10 %
t
f
2
Data Sheet D11264EJ1V0DS00
TYPICAL CHARACTERISTICS (TA = 25 °C)
2SJ492
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
dT - Percentage of Rated Power - %
0
20 40 60 80 100 120 140 160
T
C
- Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
−1000
−100
Limited
=10 V)
I
D(DC)
GS
DS(on)
R
(at V
−10
- Drain Current - A
D
I
TC = 25
˚C
Single Pulse
−1
−0.1
V
DS
- Drain to Source Voltage - V
Power Dissipation Limited
−1 −10 −100
I
1 ms
10 ms
DC
D(pulse)
100 µs
P
w
= 10 µs
100ms
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
35
30
25
20
15
10
- Total Power Dissipation - W
T
5
P
0
20 40 60 80 100 120 140 160
T
C
- Case Temperature - °C
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
−100
−80
−60
−40
- Drain Current - A
D
I
−20
0
−4
V
DS
- Drain to Source Voltage - V
−8
Pulsed
VGS = −10 V
−4 V
−12
−16
FORWARD TRANSFER CHARACTERISTICS
−1000
Tch = −25˚C
25˚C
−100
125˚C
−10
- Drain Current - A
D
I
−1
0 −5 −10
V
GS
- Gate to Source Voltage - V
Pulsed
VDS = −10 V
−15
−20
Data Sheet D11264EJ1V0DS00
3
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