NCE RFORM P4C1981-15DM, P4C1981-20DM, P4C1981-20LMB, P4C1981-45LMB, P4C1981-45DMB Datasheet
...
81
P4C1981/1981L, P4C1982/1982L
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
– 715 mW Active – 12/15
– 550/660 mW Active – 20/25/35/45
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C1981/1981L
– 5.5 mW Standby (CMOS Input)
P4C1981L/82L (Military)
Output Enable and Dual Chip Enable Functions
5V ± 10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C1981L/1982L (Military)
Separate Inputs and Outputs
– P4C1981/L Input Data at Outputs during Write
– P4C1982/L Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
1Q97
Means Quality, Service and Speed
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4)
ultra high-speed static RAMs similar to the P4C198, but
with separate data I/O pins. The P4C1981/L feature a
transparent write operation when OE is low; the outputs of
the P4C1982/L are in high impedance during the write
cycle. All devices have low power standby modes. The
RAMs operate from a single 5V ± 10% tolerance power
supply. With battery backup, data integrity is maintained
for supply voltages down to 2.0V. Current drain is typically
10 µA from 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
DESCRIPTION
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby. For the P4C1982L and
P4C1981L, power is only 5.5 mW standby with CMOS
input levels. The P4C1981/L and P4C1982/L are members of a family of PACE RAM™ products offering fast
access times.
The P4C1981/L and P4C1982/L are available in 28-pin
300 mil DIP and SOJ, and in 28-pin 350x550 mil LCC
packages providing excellent board level densities.
DIP (P5, D5-2), SOJ (J5)
TOP VIEW
LCC (L5)
TOP VIEW
P4C1981/P4C1981L, P4C1982/P4C1982L
ULTRA HIGH SPEED 16K x 4
CMOS STATIC RAMS
A
0
A
3
A
4
A
5
A
6
A
7
A
8
I
1
O
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
12
CE
1
I
GND
A
13
A
11
V
CC
2
O
3
O
2
O
1
WE
CE
2
A
1
A
2
OE
A
10
A
9
I
4
I
3
P4C1981/ 1982
A
INPUT
DATA
CONTROL
ROW
SELECT
65,536-BIT
MEMORY
ARRAY
COLUMN I/O
A
AA
(8)
(6)
I
1
I
2
I
3
I
4
COLUMN
SELECT
P4C1982
P4C1981
CE2
O
1
O
2
O
3
O
4
WE
CE1
OE
A
2
A
3
A
5
A
6
A
7
A
8
I
1
I
2
O
4
A
12
A11A
10
A
9
GND
A
0
A
1
V
CC
26
25
24
23
22
21
20
4
5
6
7
8
9
10
11
12
19
18
13 17
327
1
152142816
CE
1
I
3
I
4
O
3
O
2
A
13
OE
CE
2
WE
O
1
A
4
82
P4C1981/1981L, P4C1982/1982L
CE
1
, CE2 ≥ V
HC,
Mil.
V
CC
= Max., Ind./Com’l.
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ V
HC
MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
V
CC
Power Supply Pin with –0.5 to +7 V
Respect to GND
Terminal Voltage with –0.5 to
V
TERM
Respect to GND VCC +0.5 V
(up to 7.0V)
T
A
Operating Temperature –55 to +125 °C
Symbol Parameter Value Unit
T
BIAS
Temperature Under –55 to +125 °C
Bias
T
STG
Storage Temperature –65 to +150 °C
P
T
Power Dissipation 1.0 W
I
OUT
DC Output Current 50 mA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM ratingconditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE
1
, CE2 ≥ VIH, Mil.
VCC = Max., Ind./Com’l.
f = Max., Outputs Open
___
___
40
35
___
___
___
___
20
15
40
n/a
1.0
n/a
mA
mA
___
___
Standby Power Supply
Current
(CMOS Input Levels)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
V
OUT
= 0V
5
7
Unit
pF
pF
CAPACITANCES
(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
n/a = Not Applicable
Symbol
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
Test Conditions
VCC = Min., IIN = –18 mA
IOL = +8 mA, VCC = Min.
IOH = –4 mA, VCC = Min.
VCC = Max. Mil.
VIN = GND to VCC Com’l.
P4C1981 / 1982
Min
2.2
–0.5
(3)
VCC –0.2
–0.5
(3)
2.4
–10
–5
–10
–5
Max
VCC +0.5
0.8
VCC +0.5
0.2
–1.2
0.4
+10
+5
+10
+5
P4C1981L / 82L
Min Max
2.2
–0.5
(3)
VCC –0.2
–0.5
(3)
2.4
–5
n/a
–5
n/a
VCC +0.5
0.8
VCC +0.5
0.2
0.4
–1.2
+5
n/a
+5
n/a
Unit
V
V
V
V
V
V
V
µA
µA
Typ.
Industrial
Commercial
Grade(2)
Ambient
Temperature
GND
V
CC
–40°C to +85°C
0°C to +70°C
0V0V5.0V ± 10%
5.0V ± 10%
0V
5.0V ± 10%
–55°C to +125°C
Military
I
SB1
VCC = Max., Mil.
CE
1
, CE2 = VIH Ind./Com’l.
V
OUT
= GND to V
CC
83
P4C1981/1981L, P4C1982/1982L
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
1
= VIL, CE2 = VIL, OE = V
IH
I
CC
Symbol Parameter
Temperature
Range
Dynamic Operating Current*
Commercial
Industrial
Military
–10
N/A
–12 –15 –20 –25 –35 –45
Unit
N/AmAmA
mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
N/A 150155160170180
N/A 170 160 155 150 145
180 170 160 155 150 N/A N/A
DATA RETENTION CHARACTERISTICS (P4C1981L/P4C1982L Military Temperature Only)
Typ.* Max
Symbol Parameter Test Condition Min VCC=V
CC
= Unit
2.0V 3.0V 2.0V 3.0V
V
DR
VCC for Data Retention 2.0 V
I
CCDR
Data Retention Current 10 15 600 900 µA
t
CDR
Chip Deselect to CE1 or CE
2
≥ V
CC
– 0.2V, 0 ns
Data Retention Time V
IN
≥ V
CC
– 0.2V or
t
R
†
Operation Recovery Time t
RC
§
ns
*T
A
= +25°C
§
tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
V
IN
≤ 0.2V
DATA RETENTION WAVEFORM
V
CC
DATA RETENTION WAVEFORM
V
IH
t
CDR
4.5V
V
DR
≥ 2V
4.5V
t
R
V
DR
V
IH
1348 07
DATA RETENTION MODE
CE1 or CE
2
84
P4C1981/1981L, P4C1982/1982L
Sym. Parameter Unit
-10 -12 -15 -20 -25 -35 -45
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tRCRead Cycle Time 10 12 15 20 25 35 45 ns
tAAAddress Access 10 12 15 20 25 35 45 ns
Time
tACChip Enable 10 12 15 20 25 35 45 ns
Access Time
tOHOutput Hold from 2 2 22222ns
Address Change
tLZChip Enable to 2 2 22222ns
Output in Low Z
tHZChip Disable to 6 7 8 10 10 15 15 ns
Output in High Z
tOEOutput Enable 6 7 8 12 15 21 27 ns
Low to Data Valid
t
OLZ
Output Enable to 2 2 22222ns
Output in Low Z
t
OHZ
Output Disable to 6 7 9 9 10 14 15 ns
Output in High Z
tPUChip Enable to 0 0 00000ns
Power Up Time
tPDChip Disable to 10 12 15 20 25 25 30 ns
Power Down Time
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)
(2)
READ CYCLE NO.1 (
OEOE
OEOE
OE controlled)
(5)
OLZ
ADDRESS
OE
t
RC
DA TA OUT
(10)
t
AA
t
OE
t
OH
CE1, CE
2
t
LZ
t
AC
t
HZ
t
OHZ
t
(9)
(9) (9)
(9)
Notes:
5. WE is HIGH for READ cycle.
6. CE1, CE2 and OE are LOW for READ Cycle.
7. OE is LOW for the cycle.
8. ADDRESS must be valid prior to or coincident with, CE1, and
CE2 transition LOW.
9. Transition is measured ±200mV from steady state voltage
prior to change, with loading as specified in Figure 1.
10. Read Cycle Time is measured from the last valid address to
the first transitioning address.
85
P4C1981/1981L, P4C1982/1982L
Note:
11. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them.
t
CE1, CE
2
DATA OUT
AC
t
RC
t
LZ
DATA VALID
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
t
HZ
SUPPLY
CC
CURRENT
V
(9,11)
(9,11)
(11)
(11)
(11)
READ CYCLE NO. 3 (
CECE
CECE
CE
1
,
CECE
CECE
CE
2
Controlled)
(5,7,8)
t
ADDRESS
DATA OU
T
AA
t
t
OH
DATA VALIDPREVIOUS DATA VALID
(10)
RC
1520 05
READ CYCLE NO. 2 (ADDRESS Controlled)
(5,6)
86
P4C1981/1981L, P4C1982/1982L
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)
(2)
ParameterSymbol
–10 –12 –15 –20
–25
–35
–45
Min
Max Max
Max Max
Max Max MaxMin Min
Min
Min Min Min
t
WC
t
CW
t
AW
t
AS
Write Cycle Time
Chip Enable Time
to End of Write
Address Valid to
End of Write
Address Set-up
Time
t
WZ
t
DH
t
DW
t
AH
t
WP
Write Pulse Width
Address Hold Time
from End of Write
Data Valid to End
of Write
Data Hold Time
Write Enable to
Output in High Z
t
OW
Output Active from
End of Write
10
7
7
0
8
0
5
0
2
5
12
8
8
0
9
0
6
0
2
6
13
10
10
0
10
0
7
0
2
7
15
15
15
0
15
0
10
0
2
8
20
20
20
0
20
0
13
0
2
10
30
30
25
0
25
0
15
0
2
10
40
35
35
0
35
0
20
0
2
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AWE
t
ADV
Write Enable to
Data-out Valid
(P4C1981)
Data-in Valid to
Data-out Valid
(P4C1981)
ns
ns
10
10
12
12
13
13
18
18
20 30 35
35
30
20
WRITE CYCLE NO. 1 (WITH
OEOE
OEOE
OE HIGH)
ADDRESS
OE
DATA IN
tWC
(15)
t
AH
t
CW
CE1, CE
2
t
AW
t
AS
t
WP
t
OHZ
t
DW
t
DH
WE
DATA OUT
87
P4C1981/1981L, P4C1982/1982L
t
t
WE
ADDRESS
CE1, CE
2
DATA OUT
P4C1982
DATA IN
t
WC
DATA VALID
HIGH IMPEDANCE
(15)
t
AS
t
CW
t
AW
t
WP
DW
AH
WR
t
DH
t
t
ADV
DATA VALID
HIGH
IMPEDANCE
DATA OUT
P4C1981
WRITE CYCLE NO. 2 (
WEWE
WEWE
WE CONTROLLED)
(13,14)
1520 08
t
ADDRESS
t
WC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT
P4C1982
DATA UNDEFINED
(15)
(9)
t
CW
t
AW
t
WP
t
DW
t
AH
t
DH
t
OW
t
AS
WZ
(9,14)
t
AWE
DATA VALID
DATA OUT
P4C1981
t
ADV
CE1, CE
2
WRITE CYCLE NO. 3 (
CECE
CECE
CE
1
,
CECE
CECE
CE
2
CONTROLLED)
(11,12)
Notes:
12. CE (CE1, CE2and WE must be LOW for WRITE cycle.
13. OE is LOW for WRITE cycle.
14. If CE1 or CE2 goes HIGH simultaneously with WE HIGH,
theoutput remains in a high impedance state.
15. Write Cycle Time is measured from the last valid address to the
first transitioning address.
88
P4C1981/1981L, P4C1982/1982L
TRUTH TABLE
P4C1981/L (P4C1982/L)
CECE
CECE
CE
1
H
X
L
L
L
L
CECE
CECE
CE
2
X
H
L
L
L
L
WEWE
WEWE
WE
X
X
H
H
L
L
OEOE
OEOE
OE
X
X
H
L
H
L
Mode
Standby
Standby
Output Inhibit
READ
WRITE
WRITE
Output
High Z
High Z
High Z
D
OUT
High Z
DIN (High Z)
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns
Input Timing Reference Level 1.5V
Output Timing Reference Level 1.5V
Output Load See Figures 1 and 2
AC TEST CONDITIONS
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1981/L and P4C1982/L, care
must be taken when testing this device; an inadequate setup can cause
a normal functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
Figure 1. Output Load
Figure 2. Thevenin Equivalent
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must be
used in series with D
OUT
to match 166Ω (Thevenin Resistance).
D
OUT
255Ω
480Ω
+5V
30pF* (5pF* for tHZ, t
LZ
t
WZ OW
and t
,
)
30pF* (5pF* for tHZ, tLZ, t
OHZ
, t
OLZ
,
tWZ and tOW)
VTH = 1.73V
RTH = 166.5Ω
D
OUT
30pF* (5pF* for tHZ, tLZ, t
OHZ
, t
OLZ
,
tWZ and tOW)
89
P4C1981/1981L, P4C1982/1982L
SELECTION GUIDE
The P4C1981 and P4C1982 are available in the following temperature, speed and package options.
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not available
Temperature
Range
Speed (ns)
Package 10 12 15 20 25 35 45
Commercial
Industrial
Military Temp.
Military
Processed*
Plastic DIP
Plastic SOJ
Plastic DIP
Plastic SOJ
CERDIP
LCC
CERDIP
LCC
-10PC
-10JC
N/A
N/A
N/A
N/A
N/A
N/A
-12PC
-12JC
-12PI
-12JI
N/A
N/A
N/A
N/A
-15PC
-15JC
-15PI
-15JI
-15DM
-15LM
-15DMB
-15LMB
-20PC
-20JC
-20PI
-20JI
-20DM
-20LM
-20DMB
-20LMB
-25PC
-25JC
-25PI
-25JI
-25DM
-25LM
-25DMB
-25LMB
N/A
N/A
-35PI
-35JI
-35DM
-35LM
-35DMB
-35LMB
N/A
N/A
N/A
N/A
-45DM
-45LM
-45DMB
-45LMB
ORDERING INFORMATION
P4C
Static RAM Prefix
1982
l —ssp t
Temperature Range
Package Code
Speed (Access/Cycle Time)
Low Power Designator: Blank = None, L = Low Power
Device Number
= Ultra-low standby power designator L, if needed.
= Speed (access/cycle time in ns), e.g., 25, 35
= Package code, i.e., P, J, L, D.
= Temperature range, i.e., C, M, MB.
l
ss
p
t
P4C 1981
PACKAGE SUFFIX
Package
Suffix
P Plastic DIP, 300 mil wide standard
J Plastic SOJ, 300 mil wide standard
L Leadless Chip Carrier (ceramic)
D CERDIP, 300 mil wide standard
Description
TEMPERATURE RANGE SUFFIX
Temperature
Range Suffix
Description
Commercial Temperature Range,
0°C to +70°C.
Industrial Temperature Range,
–40°C to +85°C.
Military Temperature Range,
–55°C to +125°C.
Mil. Temp. with MIL-STD-883
Class B compliance.
C
I
M
MB
90
P4C1981/1981L, P4C1982/1982L
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