National Semiconductor TP3054-X, TP3057-X Technical data

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TP3054-X, TP3057-X
Extended Temperature Serial Interface CODEC/Filter
COMBO

®

Family

TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO Family

March 2005

General Description

The TP3054, TP3057 family consists of µ-law and A-law
monolithic PCM CODEC/filters utilizing the A/D and D/A
conversion architecture shown in Figure 1, and a serial PCM
interface. The devices are fabricated using National’s ad­vanced double-poly CMOS process (microCMOS).

The encode portion of each device consists of an input gain
adjust amplifier, an active RC pre-filter which eliminates very
high frequency noise prior to entering a switched-capacitor
band-pass filter that rejects signals below 200 Hz and above
3400 Hz. Also included are auto-zero circuitry and a com­panding coder which samples the filtered signal and en­codes it in the companded µ-law or A-law PCM format. The
decode portion of each device consists of an expanding
decoder, which reconstructs the analog signal from the com­panded µ-law or A-law code, a low-pass filter which corrects
for the sin x/x response of the decoder output and rejects
signals above 3400 Hz followed by a single-ended power
amplifier capable of driving low impedance loads. The de­vices require two 1.536 MHz, 1.544 MHz or 2.048 MHz
transmit and receive master clocks, which may be asynchro­nous; transmit and receive bit clocks, which may vary from
64 kHz to 2.048 MHz; and transmit and receive frame sync
pulses. The timing of the frame sync pulses and PCM data is
compatible with both industry standard formats.

Connection Diagrams

Features

n −40˚C to +85˚C operation
n Complete CODEC and filtering system (COMBO)

including:
— Transmit high-pass and low-pass filtering
— Receive low-pass filter with sin x/x correction
— Active RC noise filters
— µ-law or A-law compatible COder and DECoder
— Internal precision voltage reference
— Serial I/O interface
— Internal auto-zero circuitry

n µ-law, 16-pin —TP3054
n A-law, 16-pin —TP3057
n Designed for D3/D4 and CCITT applications

±

n

5V operation

n Low operating power —typically 50 mW
n Power-down standby mode —typically 3 mW
n Automatic power-down
n TTL or CMOS compatible digital interfaces
n Maximizes line interface card circuit density
n Dual-In-Line or PCC surface mount packages
n See also AN-370, “Techniques for Designing with

CODEC/Filter COMBO Circuits”

Plastic Chip Carriers

00867408

Top View

Order Number TP3057V-X

NS Package Number V20A

COMBO®and TRI-STATE®are registered trademarks of National Semiconductor Corporation.

© 2005 National Semiconductor Corporation DS008674 www.national.com

Dual-In-Line Package

00867401

Top View

Order Number TP3054N-X

NS Package Number N16E

Order Number TP3054WM-X

NS Package Number M16B

Block Diagram

TP3054-X, TP3057-X

Pin Descriptions

Symbol Function

V

BB

GNDA Analog ground. All signals are

VF

O Analog output of the receive power

R

V

CC

FS

R

D

R

Negative power supply pin.

V

= −5V±5%.

BB

referenced to this pin.

amplifier.

Positive power supply pin.

V

= +5V±5%.

CC

Receive frame sync pulse which
enables BCLK

.FSRis an 8 kHz pulse train. See

D

R

to shift PCM data into

R

Figure 2 and Figure 3 for timing details.

Receive data input. PCM data is shifted

following the FSRleading edge.

into D

R

FIGURE 1.

Symbol Function

BCLK

/CLKSEL The bit clock which shifts data into D

R

after the FSRleading edge. May vary
from 64 kHz to 2.048 MHz.
Alternatively, may be a logic input
which selects either 1.536 MHz/1.544
MHz or 2.048 MHz for master clock in
synchronous mode and BCLK
for both transmit and receive directions
(see Table 1).

/PDN Receive master clock. Must be 1.536

MCLK

R

MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
be synchronous with MCLK
performance. When MCLK
connected continuously low, MCLK
selected for all internal timing. When
MCLK

is connected continuously high,

R

the device is powered down.

00867402

is used

X

, but should

X

for best

X

is

R

R

is

X

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Pin Descriptions (Continued)

Symbol Function

MCLK

X

Transmit master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK

. Best

R

performance is realized from
synchronous operation.

FS

X

Transmit frame sync pulse input which
enables BCLK
data on D

to shift out the PCM

X

.FSXis an 8 kHz pulse

X

train, see Figure 2 and Figure 3 for
timing details.

BCLK

X

The bit clock which shifts out the PCM
data on D

. May vary from 64 kHz to

X

2.048 MHz, but must be synchronous
.

X

.

X

D

TS

with MCLK

X

The TRI-STATE®PCM data output
which is enabled by FS

X

Open drain output which pulses low
during the encoder time slot.

GS

X

Analog output of the transmit input
amplifier. Used to externally set gain.

−

VFXI

Inverting input of the transmit input
amplifier.

+

VF

I

X

Non-inverting input of the transmit input
amplifier.

Functional Description

POWER-UP

When power is first applied, power-on reset circuitry initial­izes the COMBO and places it into a power-down state. All
non-essential circuits are deactivated and the D
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the

/PDN pin and FSXand/or FSRpulses must be

MCLK

R

present. Thus, 2 power-down control modes are available.
The first is to pull the MCLK
to hold both FS

and FSRinputs continuously low —the

X

/PDN pin high; the alternative is

R

device will power-down approximately 1 ms after the last

or FSRpulse. Power-up will occur on the first FSXor

FS

X

pulse. The TRI-STATE PCM data output, DX, will remain

FS

R

in the high impedance state until the second FS

SYNCHRONOUS OPERATION

For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLK
and the MCLKR/PDN pin can be used as a power-down
control. A low level on MCLK

/PDN powers up the device

R

and a high level powers down the device. In either case,
MCLK

will be selected as the master clock for both the

X

transmit and receive circuits.A bit clock must also be applied
to BCLK

and the BCLKR/CLKSEL can be used to select the

X

proper internal divider for a master clock of 1.536 MHz,

1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the
device automatically compensates for the 193rd clock pulse
each frame.

and VFRO

X

pulse.

X

TP3054-X, TP3057-X

With a fixed level on the BCLK
selected as the bit clock for both the transmit and receive
directions. Table 1 indicates the frequencies of operation
which can be selected, depending on the state of BCLK
CLKSEL. In this synchronous mode, the bit clock, BCLK
may be from 64 kHz to 2.048 MHz, but must be synchronous
with MCLK

Each FS

.

X

pulse begins the encoding cycle and the PCM

X

data from the previous encode cycle is shifted out of the
enabled D

output on the positive edge of BCLKX. After 8 bit

X

clock periods, the TRI-STATE D
impedance state. With an FS
via the D

input on the negative edge of BCLKX(or BCLK

R

if running). FSXand FSRmust be synchronous with

X/R

.

MCLK

TABLE 1. Selection of Master Clock Frequencies

BCLKR/CLKSEL

Clocked 2.048 MHz 1.536 MHz or

0 1.536 MHz or 2.048 MHz

1 2.048 MHz 1.536 MHz or

ASYNCHRONOUS OPERATION

For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK

2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmis­sion performance, however, MCLK
with MCLK

, which is easily achieved by applying only static

X

logic levels to the MCLK
connect MCLK

to all internal MCLKRfunctions (see Pin

X

Description). For 1.544 MHz operation, the device automati­cally compensates for the 193rd clock pulse each frame.

starts each encoding cycle and must be synchronous

FS

X

with MCLK

and BCLKX.FSRstarts each decoding cycle

X

and must be synchronous with BCLK
clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLK
64 kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION

The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FS

X

timing relationships specified in Figure 2. With FS
during a falling edge of BCLK
BCLK

and FSR, must be one bit clock period long, with

X

enables the DXTRI-STATE output buffer, which will

X

output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge
disables the D
of BCLK
edge of BCLK

output. With FSRhigh during a falling edge

X

(BCLKXin synchronous mode), the next falling

R

latches in the sign bit. The following seven

R

falling edges latch in the seven remaining bits. All four de­vices may utilize the short frame sync pulse in synchronous
or asynchronous operating mode.

/CLKSEL pin, BCLKXwill be

R

output is returned to a high

X

pulse, PCM data is latched

R

Master Clock

Frequency Selected

TP3057 TP3054

1.544 MHz

1.544 MHz

1.544 MHz

and MCLKRmust be

X

should be synchronous

R

/PDN pin. This will automatically

R

. BCLKRmust be a

R

and BCLKRmay operate from

X

, the next rising edge of

X

X

high

/

R

,

X

R

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Functional Description (Continued)

LONG FRAME SYNC OPERATION

To use the long frame mode, both the frame sync pulses,
FS

and FSR, must be three or more bit clock periods long,

X

with timing relationships specified in Figure 3. Based on the
transmit frame sync, FS
short or long frame sync pulses are being used. For 64 kHz

TP3054-X, TP3057-X

operation, the frame sync pulse must be kept low for a
minimum of 160 ns. The D
enabled with the rising edge of FS

, whichever comes later, and the first bit clocked out

BCLK

X

is the sign bit. The following seven BCLK
out the remaining seven bits. The D
the falling BCLK

going low, whichever comes later. A rising edge on the

FS

X

edge following the eighth rising edge, or by

X

receive frame sync pulse, FS

to be latched in on the next eight falling edges of BCLK

D

R

(BCLKXin synchronous mode). All four devices may utilize
the long frame sync pulse in synchronous or asynchronous
mode.

In applications where the LSB bit is used for signalling, with

two bit clock periods long, the decoder will interpret the

FS

R

lost LSB as “

1

⁄2” to minimize noise and distortion.

TRANSMIT SECTION

The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be realized.
The op amp drives a unity-gain filter consisting of RC active

, the COMBO will sense whether

X

TRI-STATE output buffer is

X

R

or the rising edge of

X

rising edges clock

X

output is disabled by

X

, will cause the PCM data at

pre-filter, followed by an eighth order switched-capacitor
bandpass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. The A/D
is of companding type according to µ-law (TP3054) or A-law
(TP3057) coding conventions. A precision voltage reference
is trimmed in manufacturing to provide an input overload

) of nominally 2.5V peak (see table of Transmission

(t

MAX

Characteristics). The FS

frame sync pulse controls the

X

sampling of the filter output, and then the successive­approximation encoding cycle begins. The 8-bit code is then
loaded into a buffer and shifted out through D

pulse. The total encoding delay will be approximately

FS

X

at the next

X

165 µs (due to the transmit filter) plus 125 µs (due to encod­ing delay), which totals 290 µs. Any offset voltage due to the
filters or comparator is cancelled by sign bit integration.

RECEIVE SECTION

R

The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter clocked
at 256 kHz. The decoder is A-law (TP3057) or µ-law
(TP3054) and the 5th order low pass filter corrects for the sin
x/x attenuation due to the 8 kHz sample/hold. The filter is
then followed by a 2nd order RC active post-filter/power
amplifier capable of driving a 600Ω load to a level of 7.2
dBm. The receive section is unity-gain. Upon the occurrence

, the data at the DRinput is clocked in on the falling

of FS

R

edge of the next eight BCLK

(BCLKX) periods. At the end of

R

the decoder time slot, the decoding cycle begins, and 10 µs
later the decoder DAC output is updated. The total decoder
delay is ∼10 µs (decoder update) plus 110 µs (filter delay)
plus 62.5 µs (

1

⁄2frame), which gives approximately 180 µs.

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TP3054-X, TP3057-X

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

to GNDA 7V

V

CC

V

to GNDA −7V

BB

Voltage at any Digital Input or

Output V

+0.3V to GNDA−0.3V

CC

Operating Temperature Range −55˚C to + 125˚C

Storage Temperature Range −65˚C to +150˚C

Lead Temperature

(Soldering, 10 sec.) 300˚C

Voltage at any Analog Input

or Output V

+0.3V to VBB−0.3V

CC

Electrical Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC= +5.0V±5%, VBB= −5.0V±5%; TA=

−40˚C to +85˚C by correlation with 100% electrical testing at T
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V
+5.0V, V

= −5.0V, TA= 25˚C.

BB

Symbol Parameter Conditions Min Typ Max Units

DIGITAL INTERFACE

V

IL

V

IH

V

OL

V

OH

I

IL

I

IH

I

OZ

Input Low Voltage 0.6 V

Input High Voltage 2.2 V

Output Low Voltage DX,IL=3.2 mA 0.4 V

SIG

R,IL

TS

X,IL

Output High Voltage DX,IH=−3.2 mA 2.4 V

SIG

R,IH

Input Low Current GNDA≤VIN≤VIL, All Digital Inputs −10 10 µA

Input High Current VIH≤VIN≤V

Output Current in High Impedance DX, GNDA≤VO≤V

State (TRI-STATE)

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)

I

XA Input Leakage Current −2.5V≤V≤+2.5V, VFXI+or VFXI

I

R

XA Input Resistance −2.5V≤V≤+2.5V, VFXI+or VFXI

I

R

XA Output Resistance Closed Loop, Unity Gain 1 3 Ω

O

R

XA Load Resistance GS

L

C

XA Load Capacitance GS

L

V

XA Output Dynamic Range GSX,RL≥ 10 kΩ −2.8 2.8 V

O

A

XA Voltage Gain VFXI+to GS

V

F

XA Unity Gain Bandwidth 1 2 MHz

U

V

XA Offset Voltage −20 20 mV

OS

V

XA Common-Mode Voltage CMRRXA>60 dB −2.5 2.5 V

CM

X

X

CMRRXA Common-Mode Rejection Ratio DC Test 60 dB

PSRRXA Power Supply Rejection Ratio DC Test 60 dB

ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)

R

RF Output Resistance Pin VFRO13Ω

O

R

RF Load Resistance VFRO=±2.5V 600 Ω

L

C

RF Load Capacitance 500 pF

L

VOS

O Output DC Offset Voltage −200 200 mV

R

POWER DISSIPATION (ALL DEVICES)

I

0 Power-Down Current No Load (Note 2) 0.65 2.0 mA

CC

I

0 Power-Down Current No Load (Note 2) 0.01 0.33 mA

BB

I

1 Power-Up (Active) Current No Load( –40˚C to 85˚C) 5.0 11.0 mA

CC

I

1 Power-Up (Active) Current No Load ( –40˚C to 85˚C) 5.0 11.0 mA

BB

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.

Note 2: I

CC0

and I

are measured after first achieving a power-up state.

BB0

= 25˚C. All other limits are assured by correlation with other

A

=

CC

=1.0 mA 0.4 V

=3.2 mA, Open Drain 0.4 V

=−1.0 mA 2.4 V

CC

CC

−

−

−10 10 µA

−10 10 µA

−200 200 nA

10 MΩ

10 kΩ

50 pF

X

5000 V/V

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