National Semiconductor TP3054-X, TP3057-X Technical data

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TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO

Family

TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO Family

March 2005

General Description

The TP3054, TP3057 family consists of µ-law and A-law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in Figure 1, and a serial PCM interface. The devices are fabricated using National’s advanced double-poly CMOS process (microCMOS).

The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded µ-law or A-law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from the companded µ-law or A-law code, a low-pass filter which corrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads. The devices require two 1.536 MHz, 1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous; transmit and receive bit clocks, which may vary from 64 kHz to 2.048 MHz; and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats.

Connection Diagrams

Features

n −40˚C to +85˚C operation n Complete CODEC and filtering system (COMBO)

including: — Transmit high-pass and low-pass filtering — Receive low-pass filter with sin x/x correction — Active RC noise filters — µ-law or A-law compatible COder and DECoder — Internal precision voltage reference — Serial I/O interface — Internal auto-zero circuitry

n µ-law, 16-pin —TP3054 n A-law, 16-pin —TP3057 n Designed for D3/D4 and CCITT applications

5V operation

n Low operating power —typically 50 mW n Power-down standby mode —typically 3 mW n Automatic power-down n TTL or CMOS compatible digital interfaces n Maximizes line interface card circuit density n Dual-In-Line or PCC surface mount packages n See also AN-370, “Techniques for Designing with

CODEC/Filter COMBO Circuits”

Plastic Chip Carriers

00867408

Top View

Order Number TP3057V-X

NS Package Number V20A

COMBO®and TRI-STATE®are registered trademarks of National Semiconductor Corporation.

Dual-In-Line Package

00867401

Top View

Order Number TP3054N-X

NS Package Number N16E

Order Number TP3054WM-X

NS Package Number M16B

Block Diagram

TP3054-X, TP3057-X

Pin Descriptions

Symbol Function

GNDA Analog ground. All signals are

O Analog output of the receive power

Negative power supply pin.

= −5V±5%.

referenced to this pin.

amplifier.

Positive power supply pin.

= +5V±5%.

Receive frame sync pulse which enables BCLK

.FSRis an 8 kHz pulse train. See

to shift PCM data into

Figure 2 and Figure 3 for timing details.

Receive data input. PCM data is shifted

following the FSRleading edge.

into D

FIGURE 1.

Symbol Function

BCLK

/CLKSEL The bit clock which shifts data into D

after the FSRleading edge. May vary from 64 kHz to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLK for both transmit and receive directions (see Table 1).

/PDN Receive master clock. Must be 1.536

MCLK

MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLK be synchronous with MCLK performance. When MCLK connected continuously low, MCLK selected for all internal timing. When MCLK

is connected continuously high,

the device is powered down.

00867402

is used

, but should

for best

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Pin Descriptions (Continued)

Symbol Function

MCLK

Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLK

. Best

performance is realized from synchronous operation.

Transmit frame sync pulse input which enables BCLK data on D

to shift out the PCM

.FSXis an 8 kHz pulse

train, see Figure 2 and Figure 3 for timing details.

BCLK

The bit clock which shifts out the PCM data on D

. May vary from 64 kHz to

2.048 MHz, but must be synchronous .

with MCLK

The TRI-STATE®PCM data output which is enabled by FS

Open drain output which pulses low during the encoder time slot.

Analog output of the transmit input amplifier. Used to externally set gain.

−

VFXI

Inverting input of the transmit input amplifier.

Non-inverting input of the transmit input amplifier.

Functional Description

POWER-UP

When power is first applied, power-on reset circuitry initializes the COMBO and places it into a power-down state. All non-essential circuits are deactivated and the D outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the

/PDN pin and FSXand/or FSRpulses must be

MCLK

present. Thus, 2 power-down control modes are available. The first is to pull the MCLK to hold both FS

and FSRinputs continuously low —the

/PDN pin high; the alternative is

device will power-down approximately 1 ms after the last

or FSRpulse. Power-up will occur on the first FSXor

pulse. The TRI-STATE PCM data output, DX, will remain

in the high impedance state until the second FS

SYNCHRONOUS OPERATION

For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLK and the MCLKR/PDN pin can be used as a power-down control. A low level on MCLK

/PDN powers up the device

and a high level powers down the device. In either case, MCLK

will be selected as the master clock for both the

transmit and receive circuits.A bit clock must also be applied to BCLK

and the BCLKR/CLKSEL can be used to select the

proper internal divider for a master clock of 1.536 MHz,

1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame.

and VFRO

pulse.

TP3054-X, TP3057-X

With a fixed level on the BCLK selected as the bit clock for both the transmit and receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLK CLKSEL. In this synchronous mode, the bit clock, BCLK may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLK

Each FS

pulse begins the encoding cycle and the PCM

data from the previous encode cycle is shifted out of the enabled D

output on the positive edge of BCLKX. After 8 bit

clock periods, the TRI-STATE D impedance state. With an FS via the D

input on the negative edge of BCLKX(or BCLK

if running). FSXand FSRmust be synchronous with

X/R

MCLK

TABLE 1. Selection of Master Clock Frequencies

BCLKR/CLKSEL

Clocked 2.048 MHz 1.536 MHz or

0 1.536 MHz or 2.048 MHz

1 2.048 MHz 1.536 MHz or

ASYNCHRONOUS OPERATION

For asynchronous operation, separate transmit and receive clocks may be applied. MCLK

2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the TP3054, and need not be synchronous. For best transmission performance, however, MCLK with MCLK

, which is easily achieved by applying only static

logic levels to the MCLK connect MCLK

to all internal MCLKRfunctions (see Pin

Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame.

starts each encoding cycle and must be synchronous

with MCLK

and BCLKX.FSRstarts each decoding cycle

and must be synchronous with BCLK clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLK 64 kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION

The COMBO can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FS

timing relationships specified in Figure 2. With FS during a falling edge of BCLK BCLK

and FSR, must be one bit clock period long, with

enables the DXTRI-STATE output buffer, which will

output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the D of BCLK edge of BCLK

output. With FSRhigh during a falling edge

(BCLKXin synchronous mode), the next falling

latches in the sign bit. The following seven

falling edges latch in the seven remaining bits. All four devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode.

/CLKSEL pin, BCLKXwill be

output is returned to a high

pulse, PCM data is latched

Master Clock

Frequency Selected

TP3057 TP3054

1.544 MHz

and MCLKRmust be

should be synchronous

/PDN pin. This will automatically

. BCLKRmust be a

and BCLKRmay operate from

, the next rising edge of

high

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Functional Description (Continued)

LONG FRAME SYNC OPERATION

To use the long frame mode, both the frame sync pulses, FS

and FSR, must be three or more bit clock periods long,

with timing relationships specified in Figure 3. Based on the transmit frame sync, FS short or long frame sync pulses are being used. For 64 kHz

TP3054-X, TP3057-X

operation, the frame sync pulse must be kept low for a minimum of 160 ns. The D enabled with the rising edge of FS

, whichever comes later, and the first bit clocked out

BCLK

is the sign bit. The following seven BCLK out the remaining seven bits. The D the falling BCLK

going low, whichever comes later. A rising edge on the

edge following the eighth rising edge, or by

receive frame sync pulse, FS

to be latched in on the next eight falling edges of BCLK

(BCLKXin synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode.

In applications where the LSB bit is used for signalling, with

two bit clock periods long, the decoder will interpret the

lost LSB as “

⁄2” to minimize noise and distortion.

TRANSMIT SECTION

The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active

, the COMBO will sense whether

TRI-STATE output buffer is

or the rising edge of

rising edges clock

output is disabled by

, will cause the PCM data at

pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to µ-law (TP3054) or A-law (TP3057) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload

) of nominally 2.5V peak (see table of Transmission

MAX

Characteristics). The FS

frame sync pulse controls the

sampling of the filter output, and then the successiveapproximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through D

pulse. The total encoding delay will be approximately

at the next

165 µs (due to the transmit filter) plus 125 µs (due to encoding delay), which totals 290 µs. Any offset voltage due to the filters or comparator is cancelled by sign bit integration.

RECEIVE SECTION

The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3057) or µ-law (TP3054) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/power amplifier capable of driving a 600Ω load to a level of 7.2 dBm. The receive section is unity-gain. Upon the occurrence

, the data at the DRinput is clocked in on the falling

of FS

edge of the next eight BCLK

(BCLKX) periods. At the end of

the decoder time slot, the decoding cycle begins, and 10 µs later the decoder DAC output is updated. The total decoder delay is ∼10 µs (decoder update) plus 110 µs (filter delay) plus 62.5 µs (

⁄2frame), which gives approximately 180 µs.

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TP3054-X, TP3057-X

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

to GNDA 7V

to GNDA −7V

Voltage at any Digital Input or

Output V

+0.3V to GNDA−0.3V

Operating Temperature Range −55˚C to + 125˚C

Storage Temperature Range −65˚C to +150˚C

Lead Temperature

(Soldering, 10 sec.) 300˚C

Voltage at any Analog Input

or Output V

+0.3V to VBB−0.3V

Electrical Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC= +5.0V±5%, VBB= −5.0V±5%; TA=

−40˚C to +85˚C by correlation with 100% electrical testing at T production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V +5.0V, V

= −5.0V, TA= 25˚C.

Symbol Parameter Conditions Min Typ Max Units

DIGITAL INTERFACE

Input Low Voltage 0.6 V

Input High Voltage 2.2 V

Output Low Voltage DX,IL=3.2 mA 0.4 V

SIG

R,IL

X,IL

Output High Voltage DX,IH=−3.2 mA 2.4 V

SIG

R,IH

Input Low Current GNDA≤VIN≤VIL, All Digital Inputs −10 10 µA

Input High Current VIH≤VIN≤V

Output Current in High Impedance DX, GNDA≤VO≤V

State (TRI-STATE)

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)

XA Input Leakage Current −2.5V≤V≤+2.5V, VFXI+or VFXI

XA Input Resistance −2.5V≤V≤+2.5V, VFXI+or VFXI

XA Output Resistance Closed Loop, Unity Gain 1 3 Ω

XA Load Resistance GS

XA Load Capacitance GS

XA Output Dynamic Range GSX,RL≥ 10 kΩ −2.8 2.8 V

XA Voltage Gain VFXI+to GS

XA Unity Gain Bandwidth 1 2 MHz

XA Offset Voltage −20 20 mV

XA Common-Mode Voltage CMRRXA>60 dB −2.5 2.5 V

CMRRXA Common-Mode Rejection Ratio DC Test 60 dB

PSRRXA Power Supply Rejection Ratio DC Test 60 dB

ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)

RF Output Resistance Pin VFRO13Ω

RF Load Resistance VFRO=±2.5V 600 Ω

RF Load Capacitance 500 pF

VOS

O Output DC Offset Voltage −200 200 mV

POWER DISSIPATION (ALL DEVICES)

0 Power-Down Current No Load (Note 2) 0.65 2.0 mA

0 Power-Down Current No Load (Note 2) 0.01 0.33 mA

1 Power-Up (Active) Current No Load( –40˚C to 85˚C) 5.0 11.0 mA

1 Power-Up (Active) Current No Load ( –40˚C to 85˚C) 5.0 11.0 mA

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.

Note 2: I

CC0

and I

are measured after first achieving a power-up state.

BB0

= 25˚C. All other limits are assured by correlation with other

=1.0 mA 0.4 V

=3.2 mA, Open Drain 0.4 V

=−1.0 mA 2.4 V

−

−10 10 µA

−200 200 nA

10 MΩ

10 kΩ

50 pF

5000 V/V

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Timing Specifications

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC= +5.0V±5%, VBB= −5.0V±5%; TA=

−40˚C to +85˚C by correlation with 100% electrical testing at T production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V +5.0V, V

= – 5.0V, TA= 25˚C. All timing parameters are assured at VOH= 2.0V and VOL= 0.7V. See Definitions and Timing

Conventions section for test methods information.

Symbol Parameter Conditions Min Typ Max Units

TP3054-X, TP3057-X

1/t

WMH

WML

SBFM

SFFM

WBH

WBL

HBFL

Frequency of Master Clocks Depends on the Device Used and the 1.536 MHz

BCLK

/CLKSEL Pin. 1.544 MHz

MCLK

Rise Time of Master Clock MCLKXand MCLK

Fall Time of Master Clock MCLKXand MCLK

Period of Bit Clock 485 488 15725 ns

Rise Time of Bit Clock BCLKXand BCLK

Fall Time of Bit Clock BCLKXand BCLK

Width of Master Clock High MCLKXand MCLK

Width of Master Clock Low MCLKXand MCLK

Set-Up Time from BCLKXHigh First Bit Clock after Short Frame 100 ns

to MCLK

Setup Time from FSXHigh to MCLK

Falling Edge the Leading Edge

of FS

Long Frame Only 100 ns

Falling Edge

Width of Bit Clock High VIH=2.2V 160 ns

Width of Bit Clock Low VIL=0.6V 160 ns

Holding Time from Bit Clock Long Frame Only 0 ns

Low to Frame Sync

HBFS

Holding Time from Bit Clock Short Frame Only 0 ns

High to Frame Sync

SFB

Set-Up Time from Frame Sync Long Frame Only 115 ns

to Bit Clock Low

DBD

Delay Time from BCLKXHigh Load=150 pF plus 2 LSTTL Loads 0 140 ns

to Data Valid

DBTS

DZC

Delay Time to TSXLow Load=150 pF plus 2 LSTTL Loads 140 ns

Delay Time from BCLKXLow to CL=0 pF to 150 pF 50 165 ns

Data Output Disabled

DZF

Delay Time to Valid Data from CL=0 pF to 150 pF 20 165 ns

or BCLKX, Whichever

Comes Later

SDB

HBD

HBFl

Set-Up Time from DRValid to 50 ns

BCLK

Hold Time from BCLK

Set-Up Time from FS

BCLK

Hold Time from BCLK

to FS

Low

R/X

Low to 50 ns

R/X

Invalid

to Short Frame Sync Pulse (1 Bit Clock 50 ns

X/R

Low Period Long)

X/R

Low Short Frame Sync Pulse (1 Bit Clock 100 ns

X/R

Low Period Long)

X/R

Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns

Bit Clock Low to Frame Sync Clock Periods Long)

(FS

or FSR)

WFL

Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns

Sync Pulse (Low Level)

= 25˚C. All other limits are assured by correlation with other

and MCLK

160 ns

2.048 MHz

Long Frame 125

50 ns

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00867403

TP3054-X, TP3057-X

Timing Diagrams

FIGURE 2. Short Frame Sync Timing

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TP3054-X, TP3057-X

00867409

Timing Diagrams (Continued)

FIGURE 3. Long Frame Sync Timing

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Transmission Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC= +5.0V±5%, VBB= −5.0V±5%; TA=

−40˚C to +85˚C by correlation with 100% electrical testing at T production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, V connected for unity gain non inverting. Typicals are specified at V

Symbol Parameter Conditions Min Typ Max Units

AMPLITUDE RESPONSE

Absolute Levels Nominal 0 dBm0 Level is 4 dBm

(Definition of nominal gain) (600Ω)

0 dBm0 1.2276 Vrms

MAX

Max Overload Level

TP3054 (3.17 dBm0) 2.501 V

TP3057 (3.14 dBm0) 2.492 V

Transmit Gain, Absolute TA=25˚C, VCC=5V, VBB=−5V

Input at GS

Transmit Gain, Relative to G

f=16 Hz −40 dB

f=50 Hz −30 dB

f=60 Hz −26 dB

f=200 Hz −1.8 −0.1 dB

f=300 Hz– 3000 Hz −0.15 0.15 dB

f=3152 Hz −0.15 0.20 dB

f=3300 Hz −0.35 0.1 dB

f=3400 Hz −0.7 0 dB

f=4000 Hz −14 dB

f=4600 Hz and Up, Measure −32 dB

Response from 0 Hz to 4000 Hz

XAT

Absolute Transmit Gain Variation Relative to G

with Temperature

XAV

Absolute Transmit Gain Variation Relative to G

with Supply Voltage

XRL

Transmit Gain Variations with Sinusoidal Test Method

Level Reference Level=−10 dBm0

I+=−40 dBm0 to +3 dBm0 −0.2 0.2 dB

I+=−50 dBm0 to −40 dBm0 −0.4 0.4 dB

I+=−55 dBm0 to −50 dBm0 −1.2 1.2 dB

Receive Gain, Absolute TA=25˚C, VCC=5V, VBB=−5V

Input=Digital Code Sequence

for 0 dBm0 Signal at 1020 Hz −0.20 0.20 dB

Receive Gain, Relative to G

f=0 Hz to 3000 Hz −0.15 0.15 dB

f=3300 Hz −0.35 0.1 dB

f=3400 Hz −0.7 0 dB

f=4000 Hz −14 dB

RAT

Absolute Receive Gain Variation Relative to G

with Temperature

RAV

Absolute Receive Gain Variation Relative to G

with Supply Voltage

RRL

Receive Gain Variations with Sinusoidal Test Method; Reference

Level Input PCM Code Corresponds to an

Ideally Encoded

PCM Level =−40 dBm0 to +3 dBm0 −0.2 0.2 dB

PCM Level =−50 dBm0 to −40 dBm0 −0.4 0.4 dB

PCM Level =−55 dBm0 to −50 dBm0 −1.2 1.2 dB

= 25˚C. All other limits are assured by correlation with other

= +5.0V, VBB= −5.0V, TA= 25˚C.

=0 dBm0 at 1020 Hz −0.15 0.15 dB

= 0 dBm0, transmit input amplifier

−0.15 0.15 dB

−0.05 0.05 dB

−0.15 0.15 dB

−0.05 0.05 dB

TP3054-X, TP3057-X

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Transmission Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC= +5.0V±5%, VBB= −5.0V±5%; TA=

Symbol Parameter Conditions Min Typ Max Units

AMPLITUDE RESPONSE

TP3054-X, TP3057-X

Receive Output Drive Level RL=600Ω −2.5 2.5 V

ENVELOPE DELAY DISTORTION WITH FREQUENCY

Transmit Delay, Absolute f=1600 Hz 290 315 µs

Transmit Delay, Relative to D

f=500 Hz−600 Hz 195 220 µs

f=600 Hz−800 Hz 120 145 µs

f=800 Hz−1000 Hz 50 75 µs

f=1000 Hz−1600 Hz 20 40 µs

f=1600 Hz−2600 Hz 55 75 µs

f=2600 Hz−2800 Hz 80 105 µs

f=2800 Hz−3000 Hz 130 155 µs

Receive Delay, Absolute f=1600 Hz 180 200 µs

Receive Delay, Relative to D

f=500 Hz−1000 Hz −40 −25 µs

f=1000 Hz−1600 Hz −30 −20 µs

f=1600 Hz−2600 Hz 70 90 µs

f=2600 Hz−2800 Hz 100 125 µs

f=2800 Hz−3000 Hz 145 175 µs

NOISE

Transmit Noise, C Message TP3054 12 16 dBrnC0

Weighted (Note 3)

Transmit Noise, P Message TP3057 −74 −67 dBm0p

Weighted (Note 3)

Receive Noise, C Message PCM Code is Alternating

Weighted Positive and Negative Zero — TP3054 8 11 dBrnC0

Receive Noise, P Message TP3057 PCM Code Equals Positive

Weighted Zero — −82 −79 dBm0p

Noise, Single Frequency f=0 kHz to 100 kHz, Loop Around −53 dBm0

Measurement, VF

PPSR

Positive Power Supply Rejection, VCC=5.0 VDC+100 mVrms

Transmit f=0 kHz−50 kHz (Note 4) 40 dBC

NPSR

Negative Power Supply Rejection, VBB=−5.0 VDC+ 100 mVrms

Transmit f=0 kHz−50 kHz (Note 4) 40 dBC

PPSR

Positive Power Supply Rejection, PCM Code Equals Positive Zero

Receive V

=5.0 VDC+100 mVrms

Measure VF

f=0 Hz−4000 Hz 38 dBC

f=4 kHz−25 kHz 38 dB

f=25 kHz−50 kHz 35 dB

NPSR

Negative Power Supply Rejection, PCM Code Equals Positive Zero

Receive V

=−5.0 VDC+100 mVrms

Measure VF

f=0 Hz−4000 Hz 38 dBC

f=4 kHz−25 kHz 38 dB

f=25 kHz−50 kHz 35 dB

= 25˚C. All other limits are assured by correlation with other

= +5.0V, VBB= −5.0V, TA= 25˚C.

I+=0 Vrms

= 0 dBm0, transmit input amplifier

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Transmission Characteristics (Continued)

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC= +5.0V±5%, VBB= −5.0V±5%; TA=

Symbol Parameter Conditions Min Typ Max Units

NOISE

SOS Spurious Out-of-Band Signals Loop Around Measurement, 0 dBm0, −30 dB

at the Channel Output 300 Hz to 3400 Hz Input PCM Code

Applied at D

4600 Hz– 7600 Hz −30 dB

7600 Hz– 8400 Hz −40 dB

8400 Hz– 100,000 Hz −30 dB

DISTORTION

STD

Signal to Total Distortion Sinusoidal Test Method (Note 6)

Transmit or Receive Level=3.0 dBm0 33 dBC

Half-Channel =0 dBm0 to −30 dBm0 36 dBC

=−40 dBm0 XMT 28 dBC

=−55 dBm0 XMT 13 dBC

SFD

Single Frequency Distortion, −43 dB

Transmit

SFD

Single Frequency Distortion, −43 dB

Receive

IMD Intermodulation Distortion Loop Around Measurement, −41 dB

I+=−4 dBm0 to −21 dBm0, Two

Frequencies in the Range

300 Hz−3400 Hz

CROSSTALK

X-R

R-X

Transmit to Receive Crosstalk, f=300 Hz−3400 Hz −90 −70 dB

0 dBm0 Transmit Level D

=Quiet PCM Code (Note 6)

Receive to Transmit Crosstalk, f=300 Hz−3400 Hz, VFXI=Multitone −90 −70 dB

0 dBm0 Receive Level (Note 4)

= 25˚C. All other limits are assured by correlation with other

= +5.0V, VBB= −5.0V, TA= 25˚C.

= 0 dBm0, transmit input amplifier

RCV 29 dBC

RCV 14 dBC

TP3054-X, TP3057-X

ENCODING FORMAT AT DXOUTPUT

TP3054 TP3057

µ-Law A-Law

(Includes Even Bit Inversion)

(at GSX)=+Full-Scale 10000000 10101010

(at GSX)=0V 11111111 11010101

01111111 01010101

(at GSX)=−Full-Scale 00000000 00101010

Note 3: Measured by extrapolation from the distortion test result at −50 dBm0.

Note 4: PPSR

Note 5: TP3054/57 are measured using C message weighted filter for µ-law and psophometric weighted filter for A-law.

Note 6: CT

, NPSRX, and CT

1.544 MHz MCLKXfreq. is −70 dB max. 50%±5% BCLKXduty cycle.

X–R

are measured with a −50 dBm0 activation signal applied to VFXI+.

R–X

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Applications Information

POWER SUPPLIES

While the pins of the TP3050 family are well protected against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be

TP3054-X, TP3057-X

plugged into a “hot” socket with power and clocks already present, an extra long ground pin in the connector should be used.

All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 µF supply decoupling capacitors should be connected from this common ground point to V possible.

For best performance, the ground point of each CODEC/ FILTER on a card should be connected to a common card ground in star formation, rather than via a ground bus.

T-Pad Attenuator

and VBB, as close to device pins as

This common ground point should be decoupled to V

with 10 µF capacitors.

and

RECEIVE GAIN ADJUSTMENT

For applications where a TP3050 family CODEC/filter receive output must drive a 600Ω load, but a peak swing lower

than

2.5V is required, the receive gain can be easily adjusted by inserting a matched T-pad or π-pad at the output. Table 2 lists the required resistor values for 600Ω termina- tions. As these are generally non-standard values, the equations can be used to compute the attenuation of the closest practical set of resistors. It may be necessary to use unequal values for the R1 or R4 arms of the attenuators to achieve a precise attenuation. Generally it is tolerable to allow a small deviation of the input impedance from nominal while still maintaining a good return loss. For example a 30 dB return loss against 600Ω is obtained if the output impedance of the attenuator is in the range 282Ω to 319Ω (assuming a perfect transformer).

00867411

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Applications Information (Continued)

π-Pad Attenuator

TP3054-X, TP3057-X

Note: See Application Note 370 for further details.

00867412

TABLE 2. Attentuator Tables for Z1=Z2=300Ω

(All Values in Ω)

dB R1 R2 R3 R4

0.1 1.7 26k 3.5 52k

0.2 3.5 13k 6.9 26k

0.3 5.2 8.7k 10.4 17.4k

0.4 6.9 6.5k 13.8 13k

0.5 8.5 5.2k 17.3 10.5k

0.6 10.4 4.4k 21.3 8.7k

0.7 12.1 3.7k 24.2 7.5k

0.8 13.8 3.3k 27.7 6.5k

0.9 15.5 2.9k 31.1 5.8k

1.0 17.3 2.6l 34.6 5.2k

2 34.4 1.3k 70 2.6k

3 51.3 850 107 1.8k

4 68 650 144 1.3k

5 84 494 183 1.1k

6 100 402 224 900

7 115 380 269 785

8 379 284 317 698

9 143 244 370 630

10 156 211 427 527

11 168 184 490 535

12 180 161 550 500

13 190 142 635 473

14 200 125 720 450

15 210 110 816 430

16 218 98 924 413

18 233 77 1.17k 386

20 246 61 1.5k 366

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Typical Synchronous Application

TP3054-X, TP3057-X

00867406

FIGURE 4.

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Physical Dimensions inches (millimeters)

unless otherwise noted

TP3054-X, TP3057-X

Dual-In-Line Package (M)

Order Number TP3054WM-X

NS Package Number M16B

Molded Dual-In-Line Package (N)

Order Number TP3054N-X

NS Package Number N16E

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Cavity Dual-In-Line Package (V)

Order Number TP3057V-X

NS Package Number V20A

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TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO Family

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National Semiconductor TP3054-X, TP3057-X Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual