National Semiconductor SCAN182245A Technical data
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SCAN182245A
Non-Inverting Transceiver with
25X Series Resistor Outputs
SCAN182245A Transceiver with 25X Series Resistor Outputs
February 1996
General Description
The SCAN182245A is a high performance BiCMOS bidirectional line driver featuring separate data inputs organized
into dual 9-bit bytes with byte-oriented output enable and
direction control signals. This device is compliant with
IEEE 1149.1 Standard Test Access Port and Boundary
Scan Architecture with the incorporation of the defined
boundary-scan test logic and test access port consisting of
Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK).
Connection Diagram
Features
Y
High performance BiCMOS technology
Y
25X series resistors in outputs eliminate the need for
external terminating resistors
Y
Dual output enable control signals
Y
TRI-STATEÉoutputs for bus-oriented applications
Y
25 mil pitch SSOP (Shrink Small Outline Package)
Y
IEEE 1149.1 (JTAG) Compliant
Y
Includes CLAMP, IDCODE and HIGHZ instructions
Y
Additional instructions SAMPLE-IN, SAMPLE-OUT and
EXTEST-OUT
Y
Power Up TRI-STATE for hot insert
Y
Member of National’s SCAN Products
Pin Names Description
A1
(0–8)
B1
(0–8)
A2
(0–8)
B2
(0–8)
G1
,G2 Output Enable Pins (Active Low)
DIR1, DIR2 Direction of Data Flow Pins
Side A1 Inputs or TRI-STATE Outputs
Side B1 Inputs or TRI-STATE Outputs
Side A2 Inputs or TRI-STATE Outputs
Side B2 Inputs or TRI-STATE Outputs
Order Number Description
SCAN182245ASSC SSOP in Tubes
SCAN182245ASSCX SSOP Tape and Reel
SCAN182245AFMQB Flatpak Military
TL/F/11657– 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation RRD-B30M36/Printed in U. S. A.
TL/F/11657
http://www.national.com
Truth Tables
Inputs
²
G1 DIR1
LL H
LL L
LH H
LH L
HX Z Z
A1
(0–8)B1(0–8)
w
w
x
x
H
L
H
L
Functional Description
The SCAN182245A consists of two sets of nine non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1
and DIR2) LOW enables data from B ports to A ports, when
HIGH enables data from A ports to B ports. The Output
Enable pins (G1
ports by placing them in a high impedance condition.
and G2) when HIGH disables both A and B
Inputs
²
G2 DIR2
LL H
LL L
LH H
LH L
HX Z Z
e
H
HIGH Voltage Level
e
LOW Voltage Level
L
e
Immaterial
X
e
High Impedance
Z
e
²
Inactive-to-Active transition must occur to enable outputs upon
power-up.
Block Diagrams
A2
(0–8)B2(0–8)
w
w
x
x
H
L
H
L
A1, B1, G1 and DIR1
Note: BSR stands for Boundary Scan Register.
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TL/F/11657– 2
Block Diagrams (Continued)
Tap Controller
TL/F/11657– 18
A2, B2, G2 and DIR2
Note: BSR stands for Boundary Scan Register.
TL/F/11657– 3
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Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1
further description of scan cell TYPE1 and
a further description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
SCAN182245A Product IDCODE
(32-Bit Code per IEEE 1149.1)
Version Entity
0000 111111 0000000000 00000001111 1
MSB LSB
Logic 0
Part Manufacturer Required by
Number ID 1149.1
Figure 10-11
Figure 10-12
TL/F/11657– 17
for a
for
The INSTRUCTION register is an 8-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD)
during the CAPTURE-IR instruction command. The benefit
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required to
shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR
will update the SAMPLE/PRELOAD instruction. For more
information refer to the section on instruction definitions.
x
EXIT1-IR
Instruction Register Scan Chain Definition
MSBxLSB
Instruction Code Instruction
00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGH-Z
01000001 SAMPLE-IN
01000010 SAMPLE-OUT
00100010 EXTEST-OUT
10101010 IDCODE
11111111 BYPASS
All Others BYPASS
x
UPDATE-IR
TL/F/11657– 10
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Description of BOUNDARY-SCAN Circuitry (Continued)
Scan Cell TYPE1
Scan Cell TYPE2
TL/F/11657– 11
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TL/F/11657– 12
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register
Scan Chain Definition (80 Bits in Length)
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TL/F/11657– 32
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