National Semiconductor PC87382 Technical data

December 2003

PC87382
LPC-to-LPC Switch for Docking Stations, with Fast
Infrared Port, Serial Port and GPIOs

PC87382 LPC-to-LPC Switch for Docking Stations, with Fast Infrared Port, Serial Port and GPIOs

Revision 1.2

General Description

ThePC87382,amemberoftheNationalSemiconductorLPC
SuperI/O family, is targeted for a wide range of portable ap­plications.ThePC87382is PC2001 and ACPI compliant, and
features an LPC-to-LPC Switch with hot plugability, Fast In­frared port (FIR, IrDA 1.1compliant), Serial Port, and Gener­al-Purpose Input/Output (GPIO) support for a total of eight
ports.

The PC87382 enables glueless implementation of an LPC­to-LPC Switch between the motherboard LPC bus and the
Docking Station, and supports hot insertion and hot removal.

System Block Diagram

Outstanding Features

●

LPC-to-LPC Switch with hot plugability, enables LPC
devices in the Docking Station to be connected to the
Main LPC Bus, thus reducing the number of signals re­quired through the Docking Station connector

●

LPC bus interface, based on Intel’s LPC Interface
Specification Revision 1.1, August 2002 (supports

CLKRUN signal)

●

Fast Infrared port

●

PC2001 and ACPI Revision 2.0 compliant

●

Serial IRQ support (15 options)

●

Protection features, including GPIO lock and pin con­figuration lock

●

Eight GPIO ports, including with “assert IRQ” capability

●

XOR Tree and TRI-STATEdevice pins (or ICT) test­ability modes.

●

5V tolerant and back-drive protected pins (except LPC
bus pins)

●

48-pin LQFP package

I/O

Ports

South Bridge

LPC Bus

TPM

National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.

©2003 National Semiconductor Corporation

Embedded

Controller

PC87382

Serial

Interface

Infrared

Interface

Portable

Platform

DCLKOUT

Docking

Station

Docking LPC Bus

Docking

SIO

www.national.com

Features

• LPC System Interface

PC87382

— 8-bit I/O cycles

CLKRUN support

—
— Implements PCI mobile design guide recommenda-

tion (PCI Mobile Design Guide 1.1, Dec. 18, 1998)

• LPC-to-LPC Switch

— Hot plugability

CLKRUN support

—
— The connection is controlled by software
— Low switch resistance and propagation delay
— Programmable Clock to Reset Delay

• PC2001 and ACPI Compliant

— PnP Configuration Register structure
— Flexible resource allocation for all logical devices

❏ Relocatable base address
❏ 15 IRQ routing options
❏ Two optional 8-bit DMA channels (where applica-

ble) selected from four possible DMA channels

• Clock Sources

— 14.318 MHz or 48 MHz clock input
— LPC clock, up to 33 MHz
— 14.318 MHz or 48 MHz clock output to the docking

station

• Power Supply

— 3.3V supply operation
— All pins are 5V tolerant, except LPC bus pins
— All pins are back-drive protected, exceptLPC bus pins

• Eight General-Purpose I/O (GPIO) Ports

— Support assert IRQ
— Programmable drive type for each output pin (open-

drain, push-pull or output disable)

— Programmable option for internal pull-up resistor on

each input pin

— Output lock option
— Input debounce mechanism

• Serial Port (SP1)

— Software compatible with the 16550Aandthe 16450
— Shadow register support forwrite-only bit monitoring
— UART data rates up to 1.5 Mbaud

• Fast Infrared Port (FIR)

— Software compatible with the 16550Aandthe 16450
— Shadow register support forwrite-only bit monitoring
— FIR IrDA 1.1 compliant
— HP-SIR
— ASK-IR option of SHARP-IR
— DASK-IR option of SHARP-IR
— Consumer Remote Control supports RC-5, RC-6,

NEC, RCA and RECS 80

— DMA support: 1 or 2 channels

• Strap Configuration

— Base Address (BADDR) straptodetermine the base

address of the Index-Data register pair

— Strap Inputs to select testability mode

• Testability

— XOR Tree
— TRI-STATE device pins

Internal Block Diagram

14.31818 MHz

Clock

Generator

48 MHz

GPIO Ports

Ports

I/O

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Serial Port 1

Serial

Interface

FIR

Infrared

Interface

Bus

Interface

LPC Interface

Docking

LPC Switch

Docking LPC

Interface

Revision Record

Revision Date Status Comments

February 2003 Draft 0.1 Specification subject to change without notice.
March 2003 Draft 0.5 Specification subject to change without notice.
March 2003 Preliminary 0.9 Specification subject to change without notice.
April 2003 Preliminary 1.0 Specification subject to change without notice.
November 2003 1.1 Specification subject to change without notice.

December 2003 1.2

●

Added IDDand I
ing edits and typos.

●

Added t
Generator.

●

Technical writing edits and typos.

COR

and t

current numbersTechnical writ-

DDLP

for output from Clock

COF

PC87382

Revision 1.2 3 www.national.com

Table of Contents

PC87382

1.0 Signal/Pin Connection and Description

1.1 CONNECTION DIAGRAM ...........................................................................................................8

1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY ......................................................................9

1.3 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................10

1.3.1 LPC Bus Interface .......................................................................................................10

1.3.2 Docking LPC Bus ........................................................................................................10

1.3.3 Clocks ..........................................................................................................................10

1.3.4 Infrared (IR) ................................................................................................................11

1.3.5 Serial Port (SP1) ..........................................................................................................11

1.3.6 General-Purpose Input/Output (GPIO) Ports ...............................................................11

1.3.7 Power and Ground .....................................................................................................12

1.3.8 Strap Configuration ......................................................................................................12

1.3.9 Test and Miscellaneous ...............................................................................................12

1.4 INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................13

2.0 Power, Reset and Clocks

2.1 POWER .....................................................................................................................................14

2.1.1 Power Planes ..............................................................................................................14

2.1.2 Power States ...............................................................................................................14

2.1.3 Power Connection and Layout Guidelines ..................................................................14

2.2 RESET SOURCES AND TYPES ...............................................................................................15

2.2.1 VDD Power-Up Reset ..................................................................................................15

2.2.2 Hardware Reset ...........................................................................................................15

2.3 CLOCK DOMAINS .....................................................................................................................15

2.3.1 LPC Domain ................................................................................................................15

2.3.2 48 MHz Domain ...........................................................................................................15

2.3.3 Chip Power-Up ............................................................................................................16

2.3.4 Specifications ..............................................................................................................16

2.4 TESTABILITY SUPPORT ..........................................................................................................16

2.4.1 ICT ...............................................................................................................................16

2.4.2 XOR Tree Testing ........................................................................................................16

2.4.3 Test Mode Entry Sequence .........................................................................................17

3.0 Device Architecture and Configuration

3.1 OVERVIEW ...............................................................................................................................18

3.2 CONFIGURATION STRUCTURE AND ACCESS .....................................................................18

3.2.1 The Index-Data Register Pair ......................................................................................18

3.2.2 Banked Logical Device Registers Structure ................................................................19

3.2.3 Standard Configuration Register Definitions ...............................................................20

3.2.4 Standard Configuration Registers ...............................................................................22

3.2.5 Default Configuration Setup ........................................................................................23

3.3 MODULE CONTROL .................................................................................................................24

3.3.1 Module Enable/Disable ................................................................................................24

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Table of Contents (Continued)

3.3.2 Floating Module Output ...............................................................................................24

3.4 INTERNAL ADDRESS DECODING ..........................................................................................25

3.5 PROTECTION ...........................................................................................................................25

3.5.1 Configuration Lock .......................................................................................................25

3.5.2 GPIO Ports Configuration Lock ...................................................................................25

3.5.3 Fast Disable Configuration Lock ..................................................................................25

3.5.4 Clock Control Lock ......................................................................................................25

3.5.5 GPIO Ports Lock ..........................................................................................................25

3.6 REGISTER TYPE ABBREVIATIONS ........................................................................................26

3.7 SUPERI/O CONFIGURATION REGISTERS .............................................................................26

3.7.1 SuperI/O ID Register (SID) ..........................................................................................26

3.7.2 SuperI/O Configuration 1 Register (SIOCF1) ..............................................................27

3.7.3 SuperI/O Configuration 2 Register (SIOCF2) ..............................................................27

3.7.4 SuperI/O Configuration 6 Register (SIOCF6) ..............................................................28

3.7.5 SuperI/O Revision ID Register (SRID) ........................................................................28

3.7.6 Clock Generator Control Register (CLOCKCF) ...........................................................29

3.8 INFRARED CONFIGURATION .................................................................................................30

3.8.1 Logical Device 2 (IR) Configuration .............................................................................30

3.8.2 Infrared Configuration Register ...................................................................................30

PC87382

3.9 SERIAL PORT 1 CONFIGURATION .........................................................................................31

3.9.1 Logical Device 3 (SP1) Configuration ..........................................................................31

3.9.2 Serial Port 1 Configuration Register ............................................................................31

3.10 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION ..........................32

3.10.1 General Description .....................................................................................................32

3.10.2 Implementation ............................................................................................................32

3.10.3 Logical Device 7 (GPIO) Configuration .......................................................................33

3.10.4 GPIO Pin Select Register (GPSEL) .............................................................................34

3.10.5 GPIO Pin Configuration Register (GPCFG) ................................................................34

3.10.6 GPIO Event Routing Register (GPEVR) ......................................................................35

3.11 DOCKING LPC SWITCH CONFIGURATION ............................................................................36

3.11.1 Logical Device 19 (DLPC) Configuration .....................................................................36

4.0 LPC Bus Interface

4.1 OVERVIEW ...............................................................................................................................37

4.2 LPC TRANSACTIONS ...............................................................................................................37

4.3 CLKRUN FUNCTIONALITY ......................................................................................................37

4.4 INTERRUPT SERIALIZER ........................................................................................................37

5.0 General-Purpose Input/Output (GPIO) Port

5.1 OVERVIEW ...............................................................................................................................38

5.2 BASIC FUNCTIONALITY ..........................................................................................................39

5.2.1 Configuration Options ..................................................................................................39

5.2.2 Operation .....................................................................................................................39

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Table of Contents (Continued)

PC87382

5.3 EVENT HANDLING AND SYSTEM NOTIFICATION ................................................................40

5.3.1 Event Configuration .....................................................................................................40

5.3.2 System Notification ......................................................................................................40

5.4 GPIO PORT REGISTERS .........................................................................................................41

5.4.1 GPIO Pin Configuration Registers Structure ...............................................................42

5.4.2 GPIO Port Runtime Register Map ...............................................................................42

5.4.3 GPIO Data Out Register (GPDO) ................................................................................42

5.4.4 GPIO Data In Register (GPDI) ....................................................................................43

5.4.5 GPIO Event Enable Register (GPEVEN) ....................................................................43

5.4.6 GPIO Event Status Register (GPEVST) ......................................................................43

6.0 Docking LPC Switch

6.1 OVERVIEW ...............................................................................................................................44

6.2 FUNCTIONAL DESCRIPTION ..................................................................................................44

6.2.1 Basic Functionality .......................................................................................................44

6.2.2 LDRQ Sharing Mechanism ..........................................................................................44

6.3 DOCKING LPC SWITCH REGISTERS .....................................................................................45

6.3.1 Docking LPC Switch Register Map ..............................................................................45

6.3.2 Docking LPC Control (DLCTL) ....................................................................................45

7.0 Legacy Functional Blocks

7.1 SERIAL PORT 1 (SP1) ..............................................................................................................47

7.1.1 General Description .....................................................................................................47

7.1.2 Register Bank Overview ..............................................................................................47

7.1.3 SP1 Register Maps ......................................................................................................48

7.1.4 SP1 Bitmap Summary .................................................................................................49

7.2 IR FUNCTIONALITY (IR) ...........................................................................................................51

7.2.1 General Description .....................................................................................................51

7.2.2 Register Bank Overview ..............................................................................................51

7.2.3 IR Register Map for IR Functionality ............................................................................52

7.2.4 IR Bitmap Summary for IR Functionality .................................................................55

8.0 Device Characteristics

8.1 GENERAL DC ELECTRICAL CHARACTERISTICS .................................................................58

8.1.1 Recommended Operating Conditions .........................................................................58

8.1.2 Absolute Maximum Ratings .........................................................................................58

8.1.3 Capacitance ................................................................................................................59

8.1.4 Power Consumption under Recommended Operating Conditions ..............................59

8.1.5 Voltage Thresholds ......................................................................................................59

8.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES ..................................................59

8.2.1 Input, PCI 3.3V ............................................................................................................59

8.2.2 Input, TTL Compatible .................................................................................................60

8.2.3 Input, TTL Compatible with Schmitt Trigger ................................................................60

8.2.4 Output, PCI 3.3V .........................................................................................................60

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Table of Contents (Continued)

8.2.5 Output, Push-Pull Buffer ..............................................................................................60

8.2.6 Output, Open-Drain Buffer ...........................................................................................61

8.2.7 Quick Switch ................................................................................................................61

8.2.8 Exceptions ...................................................................................................................61

8.2.9 Terminology .................................................................................................................61

8.3 INTERNAL RESISTORS ...........................................................................................................62

8.3.1 Pull-Up Resistor ...........................................................................................................62

8.3.2 Pull-Down Resistor ......................................................................................................63

8.4 AC ELECTRICAL CHARACTERISTICS ....................................................................................63

8.4.1 AC Test Conditions ......................................................................................................63

8.4.2 Clock Input Timing .......................................................................................................64

8.4.3 Clock Output Timing ....................................................................................................64

8.4.4 LCLK and LRESET ......................................................................................................65

8.4.5 VDD Power-Up Reset ..................................................................................................66

8.4.6 LPC and SERIRQ Signals ...........................................................................................67

8.4.7 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing .............................68

8.4.8 MIR and FIR Timing ....................................................................................................69

8.4.9 Modem Control Timing ................................................................................................70

8.4.10 Docking LPC Switch Timing ........................................................................................71

PC87382

Revision 1.2 7 www.national.com

1.0 Signal/Pin Connection and Description

1.1 CONNECTION DIAGRAM

PC87382

/TEST

/TRIS

SOUT1

RTS1

SIN1

DSR1

DCD1

CLKIN

DCLKOUT

LAD3

DLAD3

LAD2

DLAD2

DLAD1

37384044 3941424345464748

CTS1

DTR1_BOUT1/BADDR

RI1

DLDRQ

IRRX1

IRTX

IRRX2_IRSL0

VDD

VSS

VCORF
GPIO00
GPIO01

1
2
3
4
5
6
7
8

9
10
11
12

GPIO02

GPIO03

PC87382

48-Pin LQFP

(Top View)

GPIO04

GPIO20

DLRESET

LDRQ/XOR_OUT

CLKRUN

DCLKRUN

212019181716151413

GPIO21

GPIO23

36

LAD1

35

VDD

34

VSS

33

DLAD0

32

LAD0

31

DLFRAME

30

LFRAME

29

DSERIRQ

28

SERIRQ
LRESET

27

DLCLK

26

LCLK

25

24

2322

VSS

VDD

48-Pin Low Profile Plastic Quad Flatpack (LQFP)

NS Package Number VBH48A

Order Number PC87382-VBH

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1.0 Signal/Pin Connection and Description (Continued)

1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY

This section describes all signals. Signals are organized in functional groups.

Buffer Types

The signal DC characteristics are denoted by a buffer type symbol, described briefly in Table 1 and in further detail in
Chapter 8 on page 58.

Table 1. Buffer Types

Symbol Description

PC87382

IN
IN
IN
O
O
OD

PCI

T

TS

PCI

p/n

n

Input, PCI 3.3V
Input, TTL compatible
Input, TTL compatible, with Schmidt Trigger
Output, PCI 3.3V
Output, push-pull buffer that is capable of sourcing p mA and sinking n mA
Output, open-drain output buffer that is capable of sinking n mA

QS Quick Switch pin
PWR Power pin
GND Ground pin

Revision 1.2 9 www.national.com

1.0 Signal/Pin Connection and Description (Continued)

1.3 DETAILED SIGNAL/PIN DESCRIPTIONS

PC87382

This section describes all signals of the PC87382.

1.3.1 LPC Bus Interface

Signal Pin(s) I/O Buffer Type Description

LAD3-0 40, 38,

36, 32

LCLK 25 I IN
LDRQ 16 O O
LFRAME 30 I IN

LRESET 27 I IN
SERIRQ 28 I/O IN

CLKRUN 19 I/OD IN

I/O IN

PCI/OPCI

PCI

PCI

PCI

PCI

PCI/OPCI

/OD6Clock Run. Same as PCI CLKRUN.

PCI

LPC Address-Data. Multiplexed command, address bidirectional data
and cycle status.

LPC Clock. Same as PCI clock (up to 33 MHz).
LPC DMA Request. Encoded DMA request for LPC interface.
LPC Frame. Low pulse indicates the beginning of a new LPC cycle or

termination of a broken cycle.

LPC Reset. Same as PCI system reset.
Serial IRQ. The interrupt requests are serialized over a single pin, where

each IRQ level is delivered during a designated time slot.

1.3.2 Docking LPC Bus

Signal Pin(s) I/O Buffer Type Description

DLAD3-0 41, 39,

37, 33
DLCLK 26 I/O QS Dock LPC Clock. Same as PCI clock (up to 33 MHz).
DLFRAME 31 I/O QS Dock LPC Frame. Low pulse indicates the beginning of a new LPC cycle

DSERIRQ 29 I/O QS Dock Serial IRQ. The interrupt requests are serialized over a single pin,

I/O QS Dock LPC Address-Data. Multiplexed command, address bidirectional

data and cycle status.

or termination of a broken cycle.

where each IRQ level is delivered during a designated time slot.
DCLKRUN 20 I/O QS Dock Clock Run. Same as PCI CLKRUN.
DLRESET 18 O O

DLDRQ 4 I IN

4/4

Dock LPC Reset. Main LPC Reset combined with Dock LPC enable.

Dock LPC DMA Request. Encoded DMA request for LPC interface.

T

1.3.3 Clocks

Signal Pin(s) I/O Buffer Type Description

CLKIN 43 I IN
DCLKOUT 42 O O

14/14

Clock In. 14.318 MHz or 48 MHz clock input.

T

Dock Clock Output. Buffered clock for the Docking device. Enabled
together with DLCLK; otherwise in TRI-STATE.

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1.0 Signal/Pin Connection and Description (Continued)

1.3.4 Infrared (IR)

Signal Pin(s) I/O Buffer Type Description

PC87382

IRRX1 5 I IN

IRRX2_IRSL0

7 I/O INTS/O

TS

IR Receive 1. Primary input to receive serial data from the IR transceiver.
IRRX2 - IR Receive 2. Auxiliary IR receiver input to support a second

3/6

transceiver.
IRSL0 - IR Select. Output used to control the IR transceiver.

IRTX 6 O O

6/12

IR Transmit. IR serial output data.

1.3.5 Serial Port (SP1)

Signal Pin(s) I/O Buffer Type Description

CTS1 1 I IN

DCD1 44 I IN

DSR1 45 I IN

DTR1_BOUT1 2 O O

RI1 3 I IN

TS

TS

TS

3/6

TS

Clear to Send. When low, indicates that the modem or other data transfer
device is ready to exchange data.

Data Carrier Detected. When low, indicates that the modem or other data
transfer device has detected the data carrier.

Data Set Ready. When low, indicates that the data transfer device, e.g.,
modem, is ready to establish a communications link.

Data Terminal Ready. When low, indicates to the modem or other data
transfer device that the UART is ready to establish a communications link.

Baud Output. Provides the associated serial channel baud rate generator
output signal if Test Mode is selected, i.e., if bit 7 of the EXCR1 register is
set.

Ring Indicator. When low, indicates that a telephone ring signal was
received by the modem. It is monitored during power-off for wake-up event
detection.

RTS1 47 O O

3/6

Request to Send. When low, indicates to the modem or other data
transfer device that the corresponding UART is ready to exchange data. A
system reset sets this signal to inactive high; a loopback operation holds it
inactive.

SIN1 46 I IN

SOUT1 48 O O

TS

3/6

Serial Input. Receives composite serial data from the communications link
(peripheral device, modem or other data transfer device).

Serial Output. Sends composite serial data to the communications link
(peripheral device, modem or other data transfer device). These signals
are set active high after a system reset.

1.3.6 General-Purpose Input/Output (GPIO) Ports

Signal Pin(s) I/O Buffer Type Description

GPIO00-04 11, 12,

13, 14,
15

GPIO20-21,
GPIO23

17, 21
22

I/O IN

OD

I/O IN

OD

/

TS

6,O3/6

/

TS

6,O3/6

General-Purpose I/O Port 0,bits 0-4. Each pin isconfigured independent­ly as inputor I/O, with orwithout static pull-up, andwith either open-drainor
push-pull output type. The port supports interrupt assertion, and each pin
can be enabled or masked as an interrupt source.

General-Purpose I/O Port 2, bits 0,1,3. Same as Port 0, without
interrupt support.

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1.0 Signal/Pin Connection and Description (Continued)

1.3.7 Power and Ground

PC87382

Signal Pin(s) I/O Buffer Type Description

V

DD

V

SS

35, 24, 8 I PWR Main 3.3V Power Supply.
34, 23, 9 I GND Ground.

1.3.8 Strap Configuration

Signal Pin(s) I/O Buffer Type Description

BADDR 2 I IN

TRIS 47 I IN

TEST 48 I IN

TS

TS

TS

Base Address. Sampled at VDDPower-Up reset to determine the base

address of the configuration Index-Data register pair.

– No pull-down resistor (default) - the Index-Data pair at

1

–10KΩ

external pull-down resistor - the Index-Data pair at 2Eh-2Fh1.

The external pull-down resistor must be connected to V

TRI-STATE Device. Sampled at VDDPower-Up to force the device to

float all its output and I/O pins.

– No pull-down resistor (default) - normal pin operation

–10KΩ

1

external pull-down resistor - floating device pins

The external pull-down resistor must be connected to V

TRIS is set to 0 (by an external pull-down resistor), TEST must be

When

1 (i.e., left unconnected).

XOR Tree Test Mode. Sampled at VDDPower-Up to force the device

pins into a XOR tree configuration.

– No pull-down resistor (default) - normal device operation

–10KΩ

1

external pull-down resistor - pins configured as XOR tree.

The external pull-down resistor must be connected to V

TEST is set to 0 (by an external pull-down resistor), TRIS must be

When

1 (i.e., left unconnected).

164Eh-164Fh.

SS

SS

SS

.

.

.

1. Because the strap function is multiplexed with the Serial Port pins, a CMOS transceiver device is recommended
for Serial Port functionality; in this case, the valueof the external pull-down resistor is 10 KΩ. If, however, a TTL
transceiver device is used, the value of the external pull-down resistor must be 470Ω, and since the Serial Port
pins are not able to drive this load, the external pull-down resistor must disconnect t

after VDDpower-up

EPLV

(see Section 8.4.5 on page 66).

1.3.9 Test and Miscellaneous

Signal Pin(s) I/O Buffer Type Description

XOR_OUT 16 O O

3/6

VCORF 10 I/O - On-Chip Core Power Converter Filter. Powers the core logic of all the

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XOR Tree Output. All the device pins (except ground and power pins)
are internally connected in a XOR tree structure.

device modules. An external 0.1 µF ceramic filter capacitor must be
connected between this pin and V

SS

.

1.0 Signal/Pin Connection and Description (Continued)

1.4 INTERNAL PULL-UP AND PULL-DOWN RESISTORS

The signals listedin Table 2can optionally support internalpull-up (PU) and/orpull-down (PD) resistors. SeeSection 8.3 on
page 62 for the values of each resistor type.

Table 2. Internal Pull-Up and Pull-Down Resistors

Signal Pin(s) Type Comments

General-Purpose Input/Output (GPIO) Ports

PC87382

GPIO00-04 11, 12,13,

14, 15

GPIO21 21 PU
GPIO20,

17, 22 PU

GPIO23

PU

30

80

30

Programmable

Programmable
Programmable

Strap Configuration and Testability

BADDR 2 PU
TEST 48 PU
TRIS 47 PU

30

30

30

Strap
Strap
Strap

1

1

1

Docking LPC

DLAD3-0 33, 37, 39,

41

DLCLK 26 PU
DCLKOUT 42 PU
DLFRAME 31 PU
DLRESET 18 PD
DSERIRQ 29 PU
DCLKRUN 20 PU
DLDRQ 4 PU

PU

30

30

80

30

120

30

30

30

Active when the switch is off

Active when the switch is off
Active when the switch is off
Active when the switch is off
Active when the switch is off
Active when the switch is off
Active when the switch is off

1. Active only during VDD Power-Up reset.

2. The DockingLPC signal resistors are active when the corresponding
switch is off.

2

2

2

2

2

2

2

Revision 1.2 13 www.national.com

2.0 Power, Reset and Clocks

2.1 POWER

PC87382

2.1.1 Power Planes

The PC87382 has asingle 3.3V power source,VDD. Internally, an additionalpower plane (V
chip voltage converter. This power plane feeds all the core logic.

2.1.2 Power States

The following terminology is used in this document to describe the power states:

) is generated usingan on-

CORF

• Power On - V

• Power Off - V

is active.

DD

is inactive.

DD

2.1.3 Power Connection and Layout Guidelines

The PC87382 requires a power supply voltage of 3.3V ± 10% for the VDDsupply. The on-chip Core voltage converter gen­erates a voltage below 3V for the internal logic.

V

and V

DD

To obtain the best performance, bear in mind the following recommendations.
Ground Connection. The following items must be connected to the ground layer (V

• The ground return (V

• The decoupling capacitors of the Main power supply (V

• The decoupling capacitor of the on-chip Core power converter (V

Note that a low-impedance ground layer also improves noise isolation.
Decoupling Capacitors. The following decoupling capacitors must be used in order to reduce EMI and ground bounce:

• Main power supply (V

dition, place one 10−47 µF tantalum capacitor on the common net as close to the device as possible.

• On-Chip Core power converter (V

pin as possible.

use a common ground return marked VSS.

CORF

) pins

SS

): Place one 0.1 µF capacitor on each VDD-VSSpin pair, as close to the pin as possible. In ad-

DD

): Place one 0.1 µF ceramic capacitor on the V

CORF

DD

) pins

CORF

) pin

) as close to the device as possible:

SS

CORF-VSS

pin pair as close to the

Main 3.3V

8

V

10

DD

V
V

SS

CORF

PC87382

9

µF

+

0.1 µF

0.1 µF

Figure 1. Decoupling Capacitors Connection

10-47

www.national.com 14 Revision1.2

V

V

V

V

DD

SS

DD
SS

24
23

35
34

0.1 µF

0.1 µF

2.0 Power, Reset and Clocks (Continued)

2.2 RESET SOURCES AND TYPES

The PC87382 has the following reset sources:

• V

Power-Up Reset - activated when VDDis powered up

DD

• Hardware Reset - activated when the LRESET input is asserted (low)

2.2.1 VDD Power-Up Reset

VDDPower-Up reset is generated byan internal circuit when VDDpower is turned on. VDDPower-Up reset time (t
until the
that the PC87382 operates correctly.

External devices must waitat least t
this time, the PC87382 LPC interface ignores the transaction (that is, it does not return a SYNC handshake).

V

LRESET signal is de-asserted. The Hardware reset (LRESET)must be asserted for aminimum of 10 ms to ensure

before accessing the PC87382.If the host processoraccesses the PC87382 during

IRST

Power-Up reset performs the following actions:

DD

IRST

) lasts

• Puts pins with strap options into TRI-STATE and enables their internal pull-up resistors

• Samples the logic levels of the strap pins

• Executes all the actions performed by the Hardware reset; see Section 2.2.2

2.2.2 Hardware Reset

Hardware reset is activatedbyassertion of LRESET inputwhileVDDis “good”. When VDDpower is off, thePC87382ignores
the level of the

LRESET input. Hardware reset performs the following actions:

PC87382

• Resets all lock bits in configuration registers

• Loads default values to all the bits in the Configuration Control

• Resets all the logical devices

• Loads default values to all the module registers

2.3 CLOCK DOMAINS

The PC87382 has two clock domains, as shown in Table 3.

Table 3. Clock Domains of the PC87382

Clock

Domain

LPC Up to 33 MHz LPC clock input (LCLK)

48 MHz 48 MHz

2.3.1 LPC Domain

The LPC clock signal at theLCLKpinmustbecome valid before the end of theHardwarereset(LRESET); see Section 2.2.2.
This clock can be slowed down or stopped using the

2.3.2 48 MHz Domain

The 48 MHz clock domain is sourced either by the on-chip Clock Generator or directly by the CLKIN input pin. The Clock
Generator is fed by applying a clock source at a frequency of 14.31818 MHz. The Clock Generator generates two internal
clocks, 24 MHz and 48 MHz. After power-up or Hardware reset, the clock (Clock Generator or external clock) is disabled.

Frequency Source Usage

LPC bus interface and Configuration registers,

On-chip Clock Generator or

directly from Clock Input (CLKIN)

CLKRUN protocol.

Docking LPC Switch logic

Legacy functions (Serial Port, Infrared)

and DCLKOUT output pin

Clock Generator Functional Description

The on-chip Clock Generator starts working when it is enabled by bit 7 of the CLOCKCF register, Index 29h, i.e., when the
bit value changes from 0 to 1 (only for 14.31818 MHz clock source). Once enabled, the output clock is frozen to a steady
logic level until theclockgenerator provides a stableoutputclock that meets all requirements.Then the clock starts toggling.

On Hardware reset, the chip wakes up with the on-chip Clock Generator disabled. The input clock of the Clock Generator
may toggle regardless of the state of the

Revision 1.2 15 www.national.com

LRESET pin. The Clock Generator waits for a toggling input clock.

2.0 Power, Reset and Clocks (Continued)

Bit 4 (read only) of the CLOCKCF register is the Valid Clock Generator status bit. While stabilizing, the output clock is frozen

PC87382

to a steady logic level,andthe status bit is clearedto0to indicate a frozen clock.Whenthe clock generator is stable,theoutput
clock starts togglingand the status bit is set to 1. The status bit tells the software when the ClockGenerator is ready.The soft­ware should poll this status bit until itis set (1), and only then activate theUART, the Infraredinterface and the DCLKOUT pin.

The clock generator and its output clock do not consume power when they are disabled.

2.3.3 Chip Power-Up

To ensure proper operation, proceed as follows after power-up:

1. Set bits 5 and 6 of the Clock Generator Control register (CLOCKCF) at Index 29h according to the clock source used
and the desired output frequency on DCLKOUT; see Table 4.

2. Enable the clock. If the clock source is 14.31818 MHz:

— Poll bit 4 of the CLOCKCF register while the clock generator is stabilizing.
— When bit 4 of CLOCKCF is set to 1, go to step 3.

3. Enable any module in the chip, as needed.

Table 4. Clock Generator Encoding Options

CLKIN Pin Frequency Desired DCLKOUT Frequency CLOCKCF Bits 6, 5

48 MHz 48 MHz 00

14.31818 MHz 14.31818 MHz 01
48 MHz 11

2.3.4 Specifications

Wake-uptime is 33 msec (maximum). This is measured from thetime theClockGeneratorisenableduntiltheclockis stable.
Note: The reference clock must be stable at the time the Clock Generator is enabled. Tolerance (long term deviation) of

the generator output clock, relative to the input clock, is ±110 ppm. Total tolerance is therefore
± (input clock tolerance + 110 ppm).

2.4 TESTABILITY SUPPORT

The PC87382 supports two testability modes:

• In-Circuit Testing (ICT)

• XOR Tree Testing

2.4.1 ICT

The In-Circuit Testing (ICT) technique, also known as “bed-of-nails”, injects logic patterns to the input pins of the devices
mounted on the tested board. It then checks their outputs for the correct logic levels.

The PC87382 supports this testing technique by floating (putting in TRI-STATE) all the device pins. This prevents “back­driving” the PC87382pins by the ICT tester when adevice normally controlledby PC87382 is tested(device inputs aredriv­en by the ICT tester).

2.4.2 XOR Tree Testing

When the PC87382 ismounted on aboard, it can betested using the XORTree technique. This testalso checks the correct
connection of the device pins to the board.

In XOR Tree mode,all PC87382 pins areconfigured as inputs, exceptthe last pin inthe tree, which istheXOR_OUT output. The
buffer type of theinput pins participating intheXOR tree is IN
in normal device operation mode (see Section 1.3 on page 10). The input pins are chained through XOR gates, as shown in
Figure 2. The power and ground pins (VDD, VSS, VCORF) are excluded from the XOR tree.

(Input, TTL compatible), regardlessof the buffer typeof these pins

T

www.national.com 16 Revision1.2

2.0 Power, Reset and Clocks (Continued)

V

DD

XOR_OUT

Pin 17 Pin 18 Pin 48 Pin 1 Pin 15 Pin 16

Figure 2. XOR Tree (Simplified Diagram)

The maximum propagation delay through the XOR tree, from the first pin in the chain to XOR_OUT is 200 ns.

2.4.3 Test Mode Entry Sequence

Table 5 shows thedecoding values required toentereach test mode. Thetest modes are decodedfrom the TEST andTRIS
strap pins and are latched into PC87382 on power up.

Table 5. Test Mode Selection

PC87382

Test Mode

No Test Mode Selected 1 1

ICT 1 0

XOR Tree 0 1

Reserved exclusively for NSC use 0 0

TEST TRIS

Revision 1.2 17 www.national.com

3.0 Device Architecture and Configuration

The PC87382 comprises a collectionoflegacy and proprietary functional blocks. Eachfunctionalblock is described in asep­arate chapter. This chapter describes the PC87382 structure and provides all logical device specific information, including

PC87382

special implementation of generic blocks, system interface and device configuration.

3.1 OVERVIEW

The PC87382 consists of fourlogical devices, the host interface, and a central set of configuration registers, allbuilt around
a central internal bus. Figure 3 illustrates the blocks and related logic.

The system interface serves as a bridge between the external LPC interfaceand the internal bus. It supports 8-bitread and
write transactions for I/O and DMA, as defined in Intel’s LPC Interface Specification, Revision 1.1.

The central configuration register set is ACPI compliant and supports a PnP configuration. The configuration registers are
structured as a subset ofthePlugand Play Standard registers, definedinAppendix A of the Plug andPlayISA Specification,
Revision 1.0a by Inteland Microsoft. Allsystem resources assigned to the functional blocks(I/O address space,DMA chan­nels and IRQ lines) are configured in, and managed by, the central configuration register set. In addition, some function­specific parameters are configurable throughthe configuration registers and distributedtothe functional blocks throughspe­cial control signals.

SIN1
SOUT1
RTS1

GPIO20,21,23

GPIO00-04

IRRX1,IRRX2

IRTX

IRSL0

GPIO

Ports

IR

Serial
Port 1

Bus

Interface

DTR1_BOUT1
CTS1
DSR1

DCD1
RI1

CLKIN
LRESET
LCLK

SERIRQ

LDRQ
LFRAME
LAD3-0
CLKRUN

Internal Bus

Control Signals

DLRESET
DLCLK

DSERIRQ

DLDRQ
DLFRAME
DLAD3-0
DCLKRUN

BADDR

TEST

TRIS

LPC

Bus

Switch

Strap

Config

Config &

Control Registers

Figure 3. PC87382 Detailed Block Diagram

3.2 CONFIGURATION STRUCTURE AND ACCESS

The configuration structure is comprised of a set of banked registerswhich are accessed via a pair of specialized registers.

3.2.1 The Index-Data Register Pair

Access to the PC87382 configuration registers is via an Index-Data register pair, using only two system I/O byte locations.
Thebase address of this register pair is determined during V
ping option on the BADDR pin. Table 6 shows the selected base addresses as a function of BADDR.

Power-Upreset, according to the state of the hardware strap-

DD

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3.0 Device Architecture and Configuration (Continued)

Table 6. BADDR Strapping Options

I/O Address

BADDR

Index Register Data Register

0 2Eh 2Fh

1 (default) 164Eh 164Fh

The Index registeris an 8-bit read/write register located at the selected baseaddress (Base+0). Itis used asa pointer to the
configuration register file, and holds the index of the configuration register that is currently accessible via the Data register.
Reading the Index register returns the last value written to it (or the default of 00h after reset).

The Data register isan 8-bit register(Base+1) used as adata path to anyconfiguration register. Accessing theData register
actually accesses the configuration register that is currently pointed to by the Index register.

3.2.2 Banked Logical Device Registers Structure

Eachfunctional block is associated with a Logical Device Number (LDN).Theconfigurationregistersaregroupedintobanks,
where each bank holdsthe standard configuration registersofthe corresponding logical device.Table 7 showsthe LDN val­ues of the PC87382 functional blocks. Any value not listed is reserved.

Figure 4 shows the structure of the standard configuration register file. The LDN and PC87382 configuration registers are
notbanked and are accessed by the Index-Data register pair only, as described in Section 3.2.1. However, the device control
and device configuration registers are duplicated over four banks for four logical devices. Therefore, accessing a specific
register in a specific bank is performed by two-dimensional indexing, where the LDN register selects the bank (or logical
device) and the Indexregister selects the registerwithin the bank. Accessingthe Data register whilethe Index register holds
a value of 30h or higher physically accesses the logical device configuration registers currently pointed to by the Index reg­ister, within the logical device currently selected by the LDN register.

PC87382

07h

Logical Device Number Register

20h

SuperI/O Configuration Registers

2Fh

Logical Device Control Register

30h
60h

63h
70h
71h
74h

75h
F0h
FFh

Banks

(One per Logical Device)

Figure 4. Structure of Standard Configuration Register File

Table 7. Logical Device Number (LDN) Assignments

LDN Functional Block

02h Infrared (IR)

Standard Logical Device

Configuration Registers

Special (Vendor-defined)

Logical Device

Configuration Registers

Bank Select

03h Serial Port 1 (SP1)
07h General-Purpose I/O (GPIO) Ports
19h Docking LPC Switch

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3.0 Device Architecture and Configuration (Continued)

Write accesses to unimplemented registers(i.e., accessing the Data registerwhilethe Index register points toanon-existing

PC87382

register) are ignored; reads return 00h on all addresses, except 74h and 75h (DMA configuration registers), which return
04h (indicating no DMA channel is active). The configuration registers are accessible immediately after reset.

3.2.3 Standard Configuration Register Definitions

In the registers below, any undefined bit is reserved. Unless otherwise noted, the following definitions also hold true:

●

All registers are read/write.

●

All reserved bits return 0 on reads, except where noted otherwise. To prevent unpredictable results, do not modify
these bits. Use read-modify-write to prevent the values of reserved bits from being changed during write.

●

Write-only registers must not use read-modify-write during updates.

Table 8. Standard General Configuration Registers

Index Register Name Description

07h Logical Device

Number

20h-2Fh PC87382

This register selects the current logical device. See Table 7 for valid numbers. All
other values are reserved.

PC87382 configuration registers and ID registers.

Configuration

Table 9. Logical Device Activate Register

Index Register Name Description

30h Activate Bits 7-1: Reserved.

Bit 0: Logical device activation control; see Section 3.3 on page 24.

0: Disabled
1: Enabled

Table 10. I/O Space Configuration Registers

Index Register Name Description

60h I/O Port Base

Indicates selected I/O lower limit address bits 15−8 for I/O Descriptor 0.

Address Bits 15−8

Descriptor 0

61h I/O Port Base

Indicates selected I/O lower limit address bits 7−0 for I/O Descriptor 0.

Address Bits 7−0

Descriptor 0

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3.0 Device Architecture and Configuration (Continued)

Table 11. Interrupt Configuration Registers

Index Register Name Description

70h Interrupt Number Indicates selected interrupt number.

Bits 7-4: Reserved.
Bits 3-0: These bits select the interrupt number. A value of 1 selects IRQ1. A value

of 15 selects IRQ15. IRQ0 is not a valid interrupt selection and
represents no interrupt selection.

Note: Avoid selecting the same interrupt number (except 0) for different logical

devices, as it causes the PC87382 to behave unpredictably.

PC87382

71h Interrupt Request

Type Select

Index Register Name Description

74h DMA Channel

Select 0

Indicates the type and polarity of the interrupt request number selected in the
previous register. If a logical device supports only one type of interrupt, the
corresponding bit is read only.

Bits 7-2: Reserved.
Bit 1: Polarity of interrupt request selected in previous register.

0: Low polarity.
1: High polarity.

Bit 0: Type of interrupt request selected in previous register.

0: Edge.
1: Level.

Table 12. DMA Configuration Registers

Indicates selected DMA channel for DMA 0 of the logical device (0 is the first DMA
channel if more than one DMA channel is used).

Bits 7-3: Reserved.
Bits 2-0: These select the DMA channel for DMA 0, where:

- A value of 0, 1, 2, or 3 selects DMA channel 0, 1, 2, or 3, respectively.

- A value of 4 indicates that no DMA channel is active.

- The values 5-7 are reserved.

Note: Avoid selecting the same DMA channel (except 4) for different logical

devices, as it causes the PC87382 to behave unpredictably.

75h DMA Channel

Select 1

Index Register Name Description

F0h-FFh Logical Device

Configuration

Revision 1.2 21 www.national.com

Indicates selected DMA channel for DMA 1 of the logical device (1 is the second
DMA channel if more than one DMA channel is used).

Bits 7-3: Reserved.
Bits 2-0: These select the DMA channel for DMA 1, where:

- A value of 0, 1, 2, or 3 selects DMA channel 0, 1, 2, or 3, respectively.

- A value of 4 indicates that no DMA channel is active.

- The values 5−7 are reserved.

Note: Avoid selecting the same DMA channel (except 4) for different logical

devices, as it causes the PC87382 to behave unpredictably.

Table 13. Special Logical Device Configuration Registers

Special (vendor-defined) configuration options.

3.0 Device Architecture and Configuration (Continued)

3.2.4 Standard Configuration Registers

PC87382

Index Register Name

07h Logical Device Number
20h SuperI/O ID
21h SuperI/O Configuration 1
22h SuperI/O Configuration 2

SuperI/O Control and
Configuration Registers

Logical Device Control and

Configuration Registers -

one per Logical Device

(some are optional)

23h-25h Reserved

26h SuperI/O Configuration 6
27h SuperI/O Revision ID
28h Reserved
29h Clock Generator Control

2Ah - 2Fh Reserved exclusively for National use

30h Logical Device Control (Activate)
60h I/O Base Address Descriptor 0 Bits 15-8
61h I/O Base Address Descriptor 0 Bits 7-0
70h Interrupt Number and Wake-Up on IRQ Enable
71h IRQ Type Select
74h DMA Channel Select 0
75h DMA Channel Select 1

F0h - FFh Device Specific Logical Device Configuration 1 to 15

Figure 5. Configuration Register Map

SuperI/O Configuration Registers

The PC87382 configuration registers at Indexes 20h and 27h are used for part identification. The other configuration
registers are used for global power management and the selection of pin multiplexing options. For details, see Section 3.7
on page 26.

Logical Device Control and Configuration Registers

A subset of theseregisters is implemented for eachlogical device. See thefunctionalblock descriptions in thefollowing sec­tions.

Control

The only implemented control register for each logical device is the Activate register at Index 30h. Bit 0 of the Activate reg­ister controls the activation of the associated functional block. Activation enables access to the functional block’s registers,
and attaches its system resources, which are unassigned aslongasitisnotactivated. Other effects may apply on a function­specific basis (such as clock enable and activepinout signaling). Access to the configuration register ofthe logical deviceis
enabled even when the logical device is not activated.

Standard Configuration

The standard configuration registers manage the PnPresourceallocationtothe functional blocks. The I/O portbaseaddress
descriptor 0 is a pair of registers at Index 60-61h, holding the first 16-bit base address for the register set of the functional
block. An optional 16-bit second base-address (descriptor 1) at Index 62-63h isused for logical devices withmore than one
continuous register set. Interrupt Number (Index 70h)and IRQ Type Select(Index 71h) allocatean IRQ line tothe block and
control its type. DMA Channel Select 0 (Index 74h) allocates a DMA channel to the block, where applicable. DMA Channel
Select 1 (Index 75h) allocates a second DMA channel, where applicable.

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