National Semiconductor PC16552D Technical data

PC16552D Dual Universal Asynchronous Receiver/Transmitter with FIFOs

June 1995

²

General Description

The PC16552D is a dual version of the PC16550D Universal Asynchronous Receiver/Transmitter (UART). The two serial channels are completely independent except for a common CPU interface and crystal input. On power-up both channels are functionally identical to the 16450*. Each channel can operate with on-chip transmitter and receiver FIFOs (FIFO mode) to relieve the CPU of excessive software overhead. In FIFO mode each channel is capable of buffering 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) of data in both the transmitter and receiver. All the FIFO control logic is on-chip to minimize system overhead and maximize system efficiency.

Signalling for DMA transfers is done through two pins per channel (TXRDY tiplexed on one pin with the OUT 2 tions. The CPU can select these functions through a new register (Alternate Function Register).

Each channel performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of each channel at any time. Status information reported includes the type and condition of the transfer operations being performed by the DUART, as well as any error conditions (parity, overrun, framing, or break interrupt).

The DUART includes one programmable baud rate generator for each channel. Each is capable of dividing the clock input by divisors of 1 to (2 clock for driving the internal transmitter logic. Provisions are also included to use this 16 logic. The DUART has complete MODEM-control capability, and a processor-interrupt system. Interrupts can be programmed to the user’s requirements, minimizing the computing required to handle the communications link.

The DUART is fabricated using National Semiconductor’s advanced M

and RXRDY). The RXRDY function is mul-

and BAUDOUT func-

16

b

1), and producing a 16

c

clock to drive the receiver

2

CMOSTM.

Features

Y

Dual independent UARTs

Y

Capable of running all existing 16450 and PC16550D software

Y

After reset, all registers are identical to the 16450 register set

Y

Read and write cycle times of 84 ns

Y

In the FIFO mode transmitter and receiver are each buffered with 16-byte FIFOs to reduce the number of interrupts presented to the CPU

Y

Holding and shift registers in the 16450 Mode eliminate the need for precise synchronization between the CPU and serial data

Y

Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data

Y

Independently controlled transmit, receive, line status, and data set interrupts

Y

Programmable baud generators divide any input clock by1to(2

Y

MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)

Y

Fully programmable serial-interface characteristics: Ð 5-, 6-, 7-, or 8-bit characters Ð Even, odd, or no-parity bit generation and detection Ð 1-, 1(/2-, or 2-stop bit generation Ð Baud generation (DC to 1.5M baud) with 16

Y

False start bit detection

Y

Complete status reporting capabilities

c

Y

TRI-STATEÉTTL drive for the data and control buses

Y

Line break generation and detection

Y

Internal diagnostic capabilities: Ð Loopback controls for communications link fault

Ð Break, parity, overrun, framing error simulation

Y

Full prioritized interrupt system controls

*Can also be reset to 16450 Mode under software control.

²

Note: This part is patented.

isolation

16

b

1) and generate the 16cclock

c

clock

TRI-STATEÉis a registered trademark of National Semiconductor Corporation

2

M

CMOSTMis a trademark of National Semiconductor Corporation

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TL/C/9426

Table of Contents

1.0 ABSOLUTE MAXIMUM RATINGS

2.0 DC ELECTRICAL CHARACTERISTICS

3.0 AC ELECTRICAL CHARACTERISTICS

4.0 TIMING WAVEFORMS

5.0 BLOCK DIAGRAM OF A SINGLE SERIAL CHANNEL

6.0 PIN DESCRIPTIONS

6.1 Input Signals

6.2 Output Signals

6.3 Input/Output Signals

6.4 Clock Signals

6.5 Power

7.0 CONNECTION DIAGRAM

8.0 REGISTERS

8.1 Line Control Register

8.2 Typical Clock Circuits

Basic Configuration

8.0 REGISTERS (Continued)

8.3 Programmable Baud Generator

8.4 Line Status Register

8.5 FIFO Control Register

8.6 Interrupt Identification Register

8.7 Interrupt Enable Register

8.8 Modem Control Register

8.9 Modem Status Register

8.10 Alternate Function Register

8.11 Scratchpad Register

9.0 FIFO Mode Operation

9.1 FIFO Interrupt Operation

9.2 FIFO Polled Operation

10.0 ORDERING INFORMATION

TL/C/9426– 1

2

1.0 Absolute Maximum Ratings

Temperature under Bias 0§Ctoa70§C

Storage Temperature

All Input or Output Voltages

with Respect to V

SS

b

65§Ctoa150§C

b

0.5V toa7.0V

Power Dissipation 1W

2.0 DC Electrical Characteristics

e

T

0§Ctoa70§C, V

A

DD

ea

5Vg10%, V

e

0V, unless otherwise specified

SS

Symbol Parameter Conditions Min Max Units

V

ILX

V

IHX

V

IL

V

IH

V

OL

V

OH

ICC(AV) Average Power Supply V

Clock Input Low Voltage

Clock Input High Voltage 2 V

Input Low Voltage

Input High Voltage 2 V

Output Low Voltage I

Output High Voltage I

Current No Loads on Output;

e

1.6 mA on all (Note 1) 0.4 V

OL

eb

1 mA (Note 1) 2.4 V

OH

e

5.5V

DD

CS, RD, WR, SIN, DSR, DCD,

e

CTS, RI

2V

All Other Inputse0.8V

e

XIN

24 MHz

e

Divisor

I

IL

I

CL

I

OZ

Input Leakage V

Clock Leakage

TRI-STATE Leakage V

V

EFFF

e

5.5V, V

DD

e

0V, 5.5V

IN

e

5.5V, V

DD

e

0V, 5.5V

OUT

1) Chip Deselected

2) WRITE Mode, Chip Selected

V

ILMR

V

IHMR

Note 1: Does not apply to XOUT

Note 2: T

e

A

MR Schmitt V

25§C

IL

IH

Maximum ratings indicate limits beyond which perma-

Note:

nent damage may occur. Continuous operation at these limits is not intended and should be limited to those conditions specified under DC electrical characteristics.

b

0.5 0.8 V

CC

b

0.5 0.8 V

CC

30 mA

e

0V

SS

e

0V

SS

g

10 mA

g

10 mA

g

20 mA

0.8 V

2V

V

Capacitance T

A

e

25§C, V

DD

e

V

0V

SS

Symbol Parameter Conditions Min Typ Max Units

C

XIN

XOUT

IN

OUT

I/O

Clock Input Capacitance 7 9 pF

e

f

1 MHz

Clock Output Capacitance 7 9 pF

Input Capacitance 5 7 pF

c

Unmeasured Pins Returned to V

SS

Output Capacitance 6 8 pF

Input/Output Capacitance 10 12 pF

3

3.0 AC Electrical Characteristics T

e

0§Ctoa70§C, V

A

DD

ea

5Vg10%

Symbol Parameter Conditions Min Max Units

t

AR

t

AW

t

DH

t

DS

t

HZ

t

MR

t

RA

t

RC

t

RD

t

RVD

t

WA

t

WC

t

WR

t

XH

t

XL

RC Read Cycleet

WC Write Cycleet

RD Delay from Address 15 ns

WR Delay from Address 15 ns

Data Hold Time 5 ns

Data Setup Time 15 ns

RD to Floating Data Delay (Note 2) 10 20 ns

Master Reset Pulse Width 500 ns

Address Hold Time from RD 0ns

Read Cycle Update 29 ns

RD Strobe Width 40 ns

Delay from RD to Data 25 ns

Address Hold Time from WR 0ns

Write Cycle Update 29 ns

WR Strobe Width 40 ns

Duration of Clock High Pulse External Clock (24 MHz Max) 17 ns

Duration of Clock Low Pulse External Clock (24 MHz Max) 17 ns

a

t

AR

AW

t

RD

a

RC

a

t

WR

WC

84 ns

BAUD GENERATOR

16

N Baud Divisor 1 2

t

BHD

t

BLD

Baud Output Positive Edge Delay f

Baud Output Negative Edge Delay f

e

24 MHz,d245ns

X

e

24 MHz,d245ns

X

b

1

RECEIVER

t

RAI

t

RINT

Delay from Active Edge of RD to Reset Interrupt

78 ns

Delay from Inactive Edge of RD (RD LSR) 40 ns to Reset Interrupt

t

RXI

t

SCD

t

SINT

Note 1: In the FIFO mode (FCR0e1) the trigger level interrupts, the receiver data available indication, the active RXRDY indication and the overrun error indication will be delayed 3 RCLKs. Status indicators (PE, FE, BI) will be delayed 3 RCLKs after the first byte has been received. For subsequently received bytes these indicators will be updated immediately after RDRBR goes inactive. Timeout interrupt is delayed 8 RCLKs.

Note 2: Charge and discharge time is determined by V

Note 3: All AC timings can be met with current loads that don’t exceed 3.2 mA or

Note 4: For capacitive loads that exceed 100 pF the following typical derating factors should be used:

Delay from READ to RXRDY Inactive 55 ns

Delay from RCLK to Sample Time 33 ns

Delay from Stop to Set Interrupt (Note 1)

and the external loading.

OL,VOH

s

100 pF

150 pF

k

C

150 pF te(0.1 ns/pF)(C

L

k

s

C

200 pF te(0.08 ns/pF)(C

L

I

SINK

I

SOURCE

Limits: I

SOURCE

te(0.5 ns/mA)(I

is negative, I

SINK

b

100 pF)

L

b

L

SINK

SOURCE

s

4.8 mA, I

100 pF)

mA)

SOURCE

s

b

80 mA at 100 pF capacitive loading.

b

120 mA, C

s

250 pF

L

AC Testing Load Circuit

2

BAUDOUT

TL/C/9426– 22

Cycles

4

3.0 AC Electrical Characteristics T

e

0§Ctoa70§C, V

A

ea

5Vg10% (Continued)

DD

Symbol Parameter Conditions Min Max Units

TRANSMITTER

t

HR

t

IR

t

IRS

t

SI

t

STI

t

SXA

t

WXI

Delay from WR (WR THR) to Reset Interrupt

Delay from RD (RD IIR) to Reset Interrupt (THRE)

Delay from Initial INTR Reset to Transmit Start Cycles

Delay from Initial Write to Interrupt (Note 1)

824

16 24

Delay from Start to Interrupt (THRE) (Note 1)

Delay from Start to TXRDY Active

40 ns

BAUDOUT

Cycles

8

BAUDOUT

Cycles

BAUDOUT

Cycles

Delay from Write to TXRDY Inactive 25 ns

MODEM CONTROL

t

MDO

t

RIM

t

SIM

Note 1: This delay will be lengthened by 1 character time, minus the last stop bit time if the transmitter interrupt delay circuit is active. (See FIFO Interrupt Mode Operation).

Delay from WR (WR MCR) to Output

Delay to Reset Interrupt from

(RD MSR)

RD

40 ns

78 ns

Delay to Set Interrupt from MODEM Input 40 ns

4.0 Timing Waveforms All timings are referenced to valid 0 and valid 1

External Clock Input (24 MHz Max)

AC Test Points

Note 2: The 2.4V and 0.4V levels are the voltages that the inputs are driven to during AC testing.

Note 3: The 2.0V and 0.8V levels are the voltages at which the timing tests are made.

TL/C/9426– 2

BAUDOUT Timing

5

TL/C/9426– 3

TL/C/9426– 4

4.0 Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued)

Read Cycle

Write Cycle

TL/C/9426– 6

Note 1: See Write Cycle Timing.

Note 2: See Read Cycle Timing.

TL/C/9426– 5

Transmitter Timing

TL/C/9426– 8

6

4.0 Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued)

Receiver Timing

MODEM Control Timing

TL/C/9426– 7

Note 1: See Write Cycle Timing.

Note 2: See Read Cycle Timing.

TL/C/9426– 9

7