National Semiconductor PC16552C User Manual

PC16552C Dual UART/DMA
Micro Channel Adapter

Table Of Contents

INTRODUCTION AND FEATURES

PC16552C ADAPTER BLOCK DIAGRAM

PC16552C ADAPTER USER’S GUIDE

POSÐPROGRAMMABLE OPTION SELECT

An overview of the Micro Channel Programmable Option
Select (POS), a unique feature which replaces all adapter
jumpers and switches with programmable configuration reg­isters.

A. POS Mechanism

B. Adapter Description File (ADF)

C. Configuration Utilities

D. POS Registers

E. PC16552C Adapter POS Register Design

MICRO CHANNEL BUS INTERFACE

General information on the adapter interface to the Micro
Channel, applicable to any adapter design, and specific in­formation on the design of the PC16552C Adapter.

A. Micro Channel Control Signals

B. Data Bus

C. Address Decode

D. UART Interface

E. Interrupts

MICRO CHANNEL BUS ARBITRATION

An overview of the bus arbitration system implemented on
all Micro Channel machines.

A. Central Arbiter

B. Local Arbiter

PC16552C ADAPTER DMA INTERFACE DESIGN

The design of the PC16552C Adapter’s Local Arbiter and
interface to the UART DMA request signals is described in
detail.

A. Design Considerations

B. DMA Request Enable

C. DMA Request Prioritization

D. Arbitration Vector Selection

E. Local Arbiter

F. Fairness

G. Terminal Count Interrupt

SOFTWARE

A. Programming the Micro Channel DMA Controller

B. Driver Programs

EISA BUS DESIGN COMPARISON

Brief description of a possible EISA bus serial port/DMA
design.

APPENDICES

A. ADF Listing (

B. PAL

Equations

É

@

6e6D.adf)

National Semiconductor
Application Note 770
Greg DeJager
July 1991

APPENDICES (Continued)

C. Schematics

D. Layout Drawing

E. Bill of Materials

INTRODUCTION

The PC16552C integrates two NS16550AF UARTs into a
single package. The product provides control for two inde­pendent PC-AT
dition, the on-board FIFOs and DMA request strobes of the
PC16552C create the basis for a high-performance serial
port design.

Advancing modem technology is causing a substantial in­crease in serial transfer baud rates, putting a severe strain
on existing serial port designs. Personal computer systems
are unable to keep up with transfer rates that are now
reaching 115k baud. The PC16552C allows the serial port
designer to design ports that can handle these faster data
rates. Transmitter and Receiver FIFOs buffer up to 16 bytes
of data each, and request strobes signal the system DMA
controller to transfer data

from

full receiver FIFOs. DMA burst transfers can move
data from the serial I/O ports to system RAM very quickly
with no latency time and no attention from the system CPU.

This document contains a user’s guide for the adapter and
discusses the considerations involved in designing any Mi­cro Channel Adapter equipped with a DMA slave. It gives an
overview of the Micro Channel POS mechanism, adapter
interface and bus arbitration system. The design of the
PC16552C Serial/DMA Adapter, intended as an example of
a DMA slave serial adapter, is described in detail. A descrip­ton of the software necessary to facilitate four simultaneous
file transfers serviced by the Micro Channel DMA controller
is also included.

PC16552C ADAPTER FEATURES

Two independent PC-AT and PS/2 compatible serial

#

ports with FIFOs capable of running all existing NS16450
and NS16550AF software.

All configuration done through POS mechanism. No

#

hardware jumpers or switches.

Serial ports relocatable to all eight standard I/O address-

#

es.

Serial interrupts available on IRQ3 and IRQ4.

#

Hardware interface between UART FIFO DMA requests

#

and the Micro Channel bus arbitration and DMA system.

POS configurable priority levels for UART DMA requests.

#

Support for software enable/disable of UART DMA re-

#

quests.

POS configurable Fairness feature for UART DMA re-

#

quests.

Automatic interrupt generation and DMA request disable

#

upon receipt of DMA Terminal Count.

Two DB-9 connectors for the two RS-232 compatible se-

#

rial ports.

and PS/2Écompatible serial ports. In ad-

É

to

empty transmitter FIFOs and

PC16552C Dual UART/DMA Micro Channel Adapter AN-770

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TL/F/11195

PC16552C Adapter Block Diagram

TL/F/11195– 1

2

PC16552C ADAPTER USER’S GUIDE

The PC16552C Adapter comes with a 3(/2
contains the ADF file for the adapter. The file is called

@

6e6d.adf and must be used to configure the adapter. Copy

diskette which

×

the file onto the Reference Diskette (actually the user’s
copy of the Diskette) for the machine to be used. To config­ure the adapter, plug it into an expansion slot and power up
the machine with the user’s reference diskette inserted in
the A drive. The configuration utility is menu driven and is
simple to follow. Use the manual configuration to see all the
different options available.

The DMA demo programs included on the Adapter’s disk­ette require that it be configured with Channel 1 on COM2
and Channel 2 on COM3. The priority of the DMA requests
must be configured with Channel 1 Receiver at level 0 (high­est priority), Channel 2 Receiver at level 1 and Channel 1
Transmitter at level 6. The Transmitter for Channel 2 de­faults to level 7. The Fairness feature should be enabled at
all times except for evaluation purposes.

When the card has been configured and the configuration
has been saved to the system’s CMOS RAM, remove the
Reference Diskette and reboot. The two serial ports may
then be evaluated and tested as any other 16550AF port
would be tested. To demonstrate the DMA transfers, run the
included sample demo programs.

POSÐPROGRAMMABLE OPTION SELECT

A unique feature of Micro Channel machines is their Pro­grammable Option Select, known as POS. POS eliminates
switches and jumpers from adapter cards by replacing their
function with programmable registers. The POS registers al­low the system microprocessor to poll each adapter card to
determine its characteristics as well as write configuration
data to it. All resources required by an adapter (memory and
I/O addresses, interrupts used, DMA arbitration vectors,
etc.) can be relocatable and reconfigurable by the POS sys­tem. Additionally, each card stores in POS registers a
unique ID number that the POS system uses to identify the
cards present in the system. A full understanding of the
POS mechanism is necessary before an adapter design is
undertaken. The IBM Technical Reference Manuals provide
details about POS that this document may not provide.

POS Mechanism

Each connector slot in the Micro Channel has a unique sig­nal called CDSETUP

that when asserted, puts the card resi­dent in that slot in setup mode. The setup mode allows
access to a block of 8 POS registers located at I/O ad­dresses 100h –107h. All cards in the system locate their
POS registers in this space but since only one card can be
placed in setup at a time, no conflicts can occur.

Micro Channel machines store in battery-backed CMOS
RAM the ID numbers of all resident adapters, the slot num­bers they’re plugged into and the configuration data to be
written to their respective POS registers. During Power On
Self Test (POST), the system microprocessor puts each slot
in turn into setup mode and reads its ID. If it finds a valid ID
it sends the card its configuration data. If there is no card in
a slot, the microprocessor will read an ffH which it recogniz­es as an empty slot.

Since the system remembers which adapter and ID resides
in each slot, removing a card, inserting a new card, or even
moving an existing card to a different slot will cause a POST
failure. IBM’s System Configuration utilities must then be run
to reconfigure the system by modifying the configuration
data stored in CMOS RAM.

ADFsÐAdapter Description Files

System board and adapter POS data is also stored on the
Reference diskette in the form of Adapter Description Files.
ADFs are given names corresponding to the ID of the card it
is to configure. The PC16552C Adapter has an ID number of
6E6Dh, giving it an ADF name of

@

6E6D.adf is included with this documentation.

@

6E6D.adf. A listing of

The ADF is divided into sections which each list one or
more choices of resources to be allocated to the adapter
card. A given choice specifies the data to be loaded into a
particular POS register and also lists the resources allocat­ed. For example, in

@

6E6D.adf, choosing ‘‘Serial 2’’
(COM2) for connector 1 will reserve the I/O address space
2f8–2ffh and will notify the system that IRQ3 is used. It also
specifies the data to be written to some of the bits in POS
registers 102 and 103. Note that pos[0]denotes POS102
and pos[1]denotes POS103 because registers POS100
and 101 contain the read-only card ID bytes which are not
referred to in ADFs. See PC16552C Adapter POS Register
Description for a description of the contents of the registers
used in this adapter.

The syntax for the ADF is straight forward and described in
detail in IBM’s Technical Reference manual. However, the
Configuration utilities are unforgiving of errors. Any errors in
a designer’s ADF will prevent any POS data for that card
from being loaded and the card from being enabled for op­eration. In addition, the system will not boot to the operating
system while the new card is inserted until the ADF is cor­rect and the system has been reconfigured with the new
data. One undocumented idiosyncrasy involves the 4-bit
fields for arbitration vectors. Since the system DMA control­ler only recognizes vectors 0–7, only 3 bits are needed to
specify the vectors to be used on the card. However, the
Configuration utilities required that all four bits be specified,
including the most significant bit which is always 0.

Configuration Utilities

There are two different utilities on the Reference diskette
provided with the system which actually convert the ADFs to
configuration data in CMOS RAM. One of these utilities
must be run whenever a new card is installed. The first is
the Automatic Configuration program. It takes the first
choice in each resource list that will not cause a conflict with
other adapters in the system and automatically stores the
corresponding POS register data in CMOS RAM.

The second program is Set Configuration which allows the
user to manually select the resources desired. It first reads
the configuration data already in CMOS RAM and displays
the resources allocated to each installed card. It then allows
the user to change these choices of resources by displaying
one-by-one all of the options for that adapter listed in the
ADFs. After all new choices have been made, exiting the
program causes the new POS data to be loaded into CMOS
RAM and the system is reconfigured and re-booted.

3

POS Registers

Address (hex) Function

0100 (POS Register 100) Adapter Identification Byte (LSB)
0101 (POS Register 101) Adapter Identification Byte (MSB)
0102 (POS Register 102) General Option Select Data
0103 (POS Register 103) General Option Select Data
0104 (POS Register 104) General Option Select Data
0105 (POS Register 105) General Option Select Data
0106 (POS Register 106) Sub Address Extension (LSB)
0107 (POS Register 107) Sub Address Extension (MSB)

Registers 100 and 101 are read-only and registers 102 –107
are read and write. The ID registers are required on all
adapters, but all bits in registers 102– 105 are optional and
user-defined except for the following:

102 Bit 0: Card Enable (CDEN): This bit must be imple-

#

mented and is used to enable the entire adapter card. It
is set last during POS initialization and only if the card will
not produce any resource conflicts. The CDEN signal
gates the decode of all addresses used on the adapter
as well as any interrupt requests.

105 Bit 7: Channel Check Active Indicator. This bit is

#

required only by adapters which generate CHCK
(see Micro Channel Interface Control Signals). Error han­dlers need this bit to identify the source of the error sig­nal.

105 Bit 6: Channel Check Status Indicator (STAT). This

#

bit is also required only by adapters supporting CHCK
is used to indicate that channel check status information
is available in POS106 and 107.

PC16552C Serial/DMA Adapter

POS Register Description

The Chips and Technologies 82C611 Micro Channel Inter­face IC, used to simplify the interface between the
PC16552C Adapter and the Micro Channel, provides good
POS register support. For all 8 POS registers, the 82C611
can be configured to generate read and write strobes for
externally implemented registers or can implement registers
internally. The 82C611 defines how several of the POS bits
used in this adapter were assigned. As can be seen in the
following register descriptions, some bits are available on
external pins while others are used for internal address de­coding or to define the operating modes of the 82C611.

POS100 and POS101ÐAdapter ID Bytes

All adapters must store a two-byte ID number in POS regis­ters 100 and 101. IBM specifies that all direct program con­trol adapters (including memory-mapped I/O) have an ID
byte between 6000 and 6FFFh. As previously mentioned,
the ID byte for this adapter is 6E6DH. When POS100 and
101 are read during setup, the 82C611 produces two sepa-

errors

.It

rate read strobesÐ100RD
well as their logical AND, are used by the INTR PAL to pull
down the data bus bits necessary for the CPU to read back
6D from POS100 and 6E from POS101 (see INTR.ABL for
equations). The data bus is pulled up to insure legal high
levels on bits not driven low.

6E6D has been registered at IBM and is guaranteed not to
conflict with any other legitimate adapters. The number to
call to register an ID is 800-426-7763. It is a good idea to
find out what numbers are available before implementing it
in a design as many numbers are already reserved. Num­bers that minimize the logic necessary to implement them
have as few logic 0 bits as possible and also have low and
high order bytes that have 0 bits in the same position.

POS102

This register is internal to the 82C611 and has all 8 bits
brought out to pins POS102B1 –7 and CDEN. It is pro­grammed as follows:

102B7: Fairness: (Used to enable IBM’s
Fairness algorithm. See DMA INTERFACE.)

102B6: A7*A6*A4
102B5: A8
102B4: A3
(Address bits providing decode information
for UART channel 1.)

102B3: A7*A6*A4
102B2: A8
102B1: A3
(Address bits providing decode information
for UART Channel 1.)

102B0: CDEN: (See POS Registers.)

POS103

This register is internal to the 82C611. The bits are not avail­able on external pins but instead are compared to 3 input
pins which are connected to address bus bits 14, 13 and 12.
A match produces an output used for the decode of the
UART channels.

102B7: unused
102B6: unused

102B5: A14
102B4: A13
102B3: A12
(Address bits providing decode information
for UART channel 1.)

102B2: A14
102B1: A13
102B0: A12
(Address bits providing decode information
for UART channel 2.)

and 101RD. These signals, as

4

POS104

This register stores the bus arbitration vectors for the UART
receiver DMA requests RXRDY1
mented externally using a 74LS374 latch and 74LS245 buff­er. The 82C611 decodes reads and writes to the register
during setup and provides the correct strobes. This informa­tion is also needed as external signals so they were imple­mented in a register with corresponding output pins.

102B7: RX2 ARB3
102B6: RX2 ARB2
102B5: RX2 ARB1
102B4: RX2 ARB0
102B3: RX1 ARB3
102B2: RX1 ARB2
102B1: RX1 ARB1
102B0: RX1 ARB0

POS105

This register is implemented internal to the 82C611. The
lower four bits contain the arbitration vector for UART chan­nel 1 transmitter. They were selected for the vector because
output pins were needed. The upper four bits contain con­trol bits for the Micro Channel interface.

105B7: Channel Check Active Indicator. See
POS registers. It is not used in this
adapter.

105B6: Channel Check Status Indicator
(STAT). See POS Registers. It is not used in
this adapter.

105B5: Synchronous Extended Mode: The 82C611
specifies the definition of this bit. It
generates synchronous extended cycles if set
and asynchronous extended cycles if cleared
(see CHRDY
Signals).

105B4: unused

105B3: TX1 ARB3
105B2: TX1 ARB2
105B1: TX1 ARB1
105B0: TX1 ARB0

POS106 and POS107 are not used in this adapter. The sub­addressing bits are used to specify the location of a block of
initial program load (IPL) or additional setup information.

MICRO CHANNEL BUS INTERFACE

Micro Channel Control Signals

All of the Micro Channel signals needed to control an 8- or
16-bit adapter are described below. They are all connected
directly to the 82C611 which meets all IBM timing and drive
specifications for those signals.

CD SFDBK

driven low by an adapter to acknowledge to the system
when it decodes a specified address. The 82C611 drives
this signal low when the adapter logic asserts the part’s
CDSEL input. The CDSEL signal is generated by a logical
OR of the unlatched address decodes of both UART chan­nels and the two registers decoded on the adapter for DMA
control and status (see DMA Interface Design).

in Micro Channel Control

: Card Selected Feedback: This signal must be

and RXRDY2. It is imple-

CD DS16

when an adapter requires a 16-bit data transfer. The
82C611 drives this signal as a function of its DS16 input
which is tied high in this design.

CD CHRDY: Card Channel Ready: An adapter which
needs more time to transfer data on the Micro Channel pulls
this signal low (not ready) to extend the current bus cycle.
There are two types of extended cycles: Asynchronous Ex­tended and Synchronous Extended. The difference be­tween them is when the CD CHRDY signal driven back high
(ready). In the synchronous case, CD CHRDY is removed
within 30 ns of the falling edge of CMD
system to extend the cycle 100 ns or 1 wait state. In the
asynchronous case, CD CHRDY is removed at any time by
the adapter providing as many wait states as necessary (the
limit for holding CD CHRDY low is 3 m s). POS105 bit 5 de­fines which type the 82C611 supports. A single wait state is
needed to support DMA transfers from the PC16552C so
the bit is programmed for synchronous mode. The 82C611
causes an extended cycle when its ADPRDY
serted by the adapter. In this design, the ADPRDY
the same as the CDSEL signal thus causing an extended
cycle to be generated on every access to the Adapter.

CHRESET: Channel Reset: This active high strobe from
the Micro Channel resets devices on adapter cards. It is
connected to the 82C611, PC16552C, and the Busarb,
Lockout and Fair state machines.

CD SETUP

nal low during POS setup. Upon receiving this signal, the
82C611 places the PC16552C Adapter into setup mode by
allowing access to the POS registers.

REFRESH

refresh cycle is occuring on the bus. The refresh cycle looks
like a normal memory read, which the 82C611 will ignore
upon receiving an active REFRESH

CHCK: Channel Check: Adapters assert this signal to indi­cate a serious error (such as parity) which threatens system
operation. The signal is common to all adapter slots so it
must be driven with an open-collector driver. The 82C611
drives this signal as a function of the ERROR
tied high (inactive) in this design.

S0

into separate I/O read (IOR) and I/O write (IOW) strobes.

Data Bus

A 74LS245 buffer isolates the Adapter’s data bus from the
Micro Channel data bus to prevent excessive loading of Mi­cro Channel bus. Direction and gating during read and write
cycles is controlled by the 82C611’s BUFDIR and BUFENL
signals. The internal bus connects to the PC16552C,
POS104, DMAÐEN and ISR registers (see DMA Interface)
and the INTR PAL (POS ID generator).

: Card Data Size 16: This signal is driven low

. This causes the

signal is as-

signal is

: Card Setup: The Micro Channel drives this sig-

: This system indicates through this signal that a

signal.

input which is

,S1,M/IO and CMD: The 82C611 decodes these signals

5

Address Decode

Micro Channel adapters should have their resources relo­catable and selectable through the POS mechanism. This
design allows for the two serial channels on board the
PC16552C to be located at any two of the 8 ‘‘standard’’ IBM
serial port addresses. The following table shows those ad­dresses:

COM Port Hex Address Binary Address (A15 –0)

1 03F8 0000 0011 1111 1000
2 02F8 0000 0010 1111 1000
3 3220 0011 0010 0010 0000
4 3228 0011 0010 0010 1000
5 4220 0100 0010 0010 0000
6 4228 0100 0010 0010 1000
7 5220 0101 0010 0010 0000
8 5228 0101 0010 0010 1000

The upper 13 bits of the address must be decoded while the
lower 3 bits, A2– A0, connect directly to the PC16552C to
select one of 8 internal registers of the selected channel. As
can be seen from the binary addresses above, 5 bits stay
the same for the 8 COM ports (A15, A11, A10, A9, A5) and
8 bits must be programmed for the port selected for decode.

Adapter card logic gates ‘‘compress’’ bit fields that are al­ways at the same logic level so that all 13 bits will not need
to be decoded separately. The 82C611 has inadequate ad­dress decoding resources so two 74LS521 Comparators,
one for each UART channel, are implemented to compare
compressed bits and some of the address bus bits with POS
programmed bits and hard-wired bits. POS registers 102
and 103 are programmed with the data necessary to de­code the two ports selected for use on the adapter (see
POS Register Description). The entire decode works as fol­lows:

Address bits A15, A11 and A10 are always 0. They are com­pressed to one bit with a NOR gate and compared to a
hard-wired 1 on both comparators.

A9 and A5 are always 1. They are compressed by a NAND
gate to a bit which is compared to a hard-wired 0 by both
comparators.

A7, A6 and A4 are all 0 if the port address is for COM3 –8. A
NAND gate compresses the bits to a signal which is com­pared to POS102 bit 6 by the channel 1 comparator and to
POS102 bit 3 by the channel 2 comparator. Thus POS102
bit 6 must be programmed toa0ifchannel 1 is to be COM1
or COM2 and toa1ifit’s to be COM3–8. POS102 bit 3 is
programmed similarly for channel 2.

A8isa1intheCOM1 address and 0 in all others. It is
connected directly to both comparators and compared to
POS102 bit 5 and POS102 bit 2 which are programmed for
channel 1 and channel 2 respectively.

A3 equals 1 in COM1, 2, 4, 6 and 8 and equals 0 in COM3, 5
and 7. It is also connected directly to each comparator and
compared to POS102 bit 4 and bit 1 which are programmed
for channel 1 and channel 2 respectively.

A14, A13 and A12 are connected to 82C611 multi-function
pins MFP6, 5 and 4 respectively. They are constantly com­pared to two bit fields in POS103ÐB5–3 and B2 –0. Bits 5 –
3 are programmed with the A14, A13 and A12 bits expected
for channel 1 and bits 2 –0 with the bits expected for chan­nel 2. The 82C611 will assert MFP3
for channel 1 and will assert MFP2
for channel 2. MFP3
ator and MFP2
Both are compared to a hard-wired 0.

As stated in the POS Register Description, POS102 bit 0 is
the card enable signal CDEN. The signal enables UART
address decode by being compared to a hard-wired 1 on
both comparators (CDEN is 0 until POS102 bit 0 is set).
Finally, the M/IO signal from the Micro Channel is used to
gate both LS521 comparators so that only I/O addresses
are decoded. The two comparators produce active low out­puts when an address match is found. These signals are
CS1

and CS2, the selects for the PC16552’s two channels.

The adapter decodes one additional I/O address, 2F7h,
which is the location of the write-only DMAÐEN register
and read-only ISR register (see DMA Interface for register
description). These registers are not relocatable. However,
the I/O resource is ‘‘claimed’’ in the adapter’s ADF so any
conflict with other cards will be caught by POST which will
not enable the card, preventing system damage.

UART Interface

The PC16552C register address bits (A2, A1, A0) and the
CS

outputs of the LS521 comparators are latched into a
74LS373 by the CMD
bus cycle. The latched CS1
produce the PC16552’s CS
the UART is selected by connecting the CS2
UART’s CHSL input which produces the following channel
decode:

CS1 CS2 (CHSL) Channel Selected

01 1
10 2
11 X

The adapter’s address decode logic and the PC16552C cy­cle time is fast enough to operate with the Micro Channel’s
default bus cycle length. No wait states are needed for ac­cess to the UART.

Interrupts

The Micro Channel’s IRQ interrupts are designed as active­low, level-sensitive signals. This simplifies adapter interrupt
sharing logic and reduces transient sensitivity on the inter­rupt controller while retaining compatibility with existing soft­ware. Because IRQ lines are shared, open-collector drivers
or active-low TRI-STATE
to drive the lines.

is connected to the channel 1 compar-

is connected to the channel 2 comparator.

signal and held for the duration of a

drivers must be used by adapters

É

when a match is made

when a match is made

and CS2 signals are ANDed to
signal. The correct channel on

signal to the

6

The INTR GALÉon the PC16552C Adapter drives the IRQ3
and IRQ4 signals. INTR inputs the interrupt signals from the
PC16552C (INTR1 and INTR2) and the TC interrupt (see
DMA Interface). INTR will assert IRQ3 if a TC interrupt is
generated or if a UART channel configured as COM2 –8
generates a serial interrupt. It will assert IRQ4 if it receives a
serial interrupt from a channel configured as COM1. INTR
decodes the serial interrupts by using POS102 bits 5 and 2
which store address bit A8 for channels 1 and 2 respective­ly. A8 is used because it isa1ifCOM1 is being used and a
0 if any other COM port is used. See the included INTR.ABL
listing for the GAL equations.

MICRO CHANNEL BUS ARBITRATION

The PC16552C Dual Serial/DMA Adapter implements the
logic necessary to interface a DMA slave device to the Mi­cro Channel’s bus arbitration system and DMA controller. A
DMA slave adapter must contain a Local Arbiter, as defined
by IBM, in order to compete for the bus and communicate
with the system’s Central Arbiter. The adapter must also
contain any logic necessary to directly support the device
requesting DMA service.

The following material on the DMA Interface discusses the
function of the Central Arbiter and the bus arbitration pro­cess, Local Arbiters and DMA interface design considera­tions. It then describes in detail the functions of the DMA
interface logic implemented on the PC16552C Adapter.

Central Arbiter

The Central Arbiter exists on all of IBM’s Micro Channel
machines and gives intelligent subsystems the ability to
share and control the system. It supports up to 16 arbitrating
devices, such as a DMA slave, a bus master and the system
microprocessor.

The Central Arbiter is located on the system board of the
Micro Channel machines and uses seven Micro Channel
signals to control arbitration between devices. The seven
signals are PREEMPT
ARB/GNT may only be driven by the Central Arbiter. The
rest of the signals may be driven by any device on the Chan­nel and therefore must be connected to open-collector driv­ers.

Any device requesting control of the bus asynchronously
drives PREEMPT
initiating an arbitration cycle after the device currently using
the Channel has completed. The Central Arbiter indicates
the arbitration cycle by driving the ARB/GNT signal high
into the arbitration state. Requesting devices then drive their
assigned 4-bit arbitration vector onto the ARB3 –0 bus.
These vectors are prioritized with 0000 being the highest
and 1111 being the lowest priority. Each competing device
compares the vector it is driving onto the ARB pins with the
level already on the bus. If it finds a level that has a higher
priority it stops driving its vector onto the bus, thus leaving
the highest priority vector on the bus. When the Central
Arbiter ends the arbitration period by changing the ARB/
GNT signal to the grant state, the device driving the winning
vector assumes control of the bus.

Devices requiring multiple data transfers must notify the
central arbiter by driving the BURST
are complete. A bursting device may also stop transfers

, ARB/GNT, BURST and ARB3–0.

active. The Central Arbiter responds by

signal until all transfers

if another device drives PREEMPT
any further transfers until it wins the system channel again.
IBM

requires a bursting device not to ignore an active

É

PREEMPT
mum time allowed for a single BURST transfer). At this time
the Central Arbiter forcibly takes control away from the
bursting device by raising the ARB/GNT signal. The system
will also generate an error indication and NMI.

The Central Arbiter recognizes the end of a transfer when
both status signals (S0
end of a bus cycle) and BURST
ever occurs last. Arbitration then begins for the next highest
priority requesting device. The system CPU, which is as­signed the lowest priority arbitration vector 1111, will re­sume control of the system bus if no other devices are re­questing the bus.

A programmable (through POS) fairness feature prevents
high priority devices from locking out lower priority devices.
If fairness is active, a device that has control of the bus
cannot compete again for the bus until all other competing
devices have been allowed to run their cycles. This ensures
that all arbitrating devices will be serviced in order of priority
before the same device can gain control of the channel
again.

The system DMA controller is an integral part of the Central
Arbiter. The controller has 8 channels (0 –7) which corre­spond to arbitration vectors 0000– 0111. A device request­ing DMA service competes for the system bus with the vec­tor corresponding to the DMA channel previously pro­grammed to perform the desired transfer. The DMA control­ler assumes control of the bus when the highest priority
requesting DMA wins the arbitration cycle. The controller
will execute single byte transfers unless the DMA slave as­serts the BURST
cute a burst cycle, executing transfers until the BURST
nal is deasserted or the controller’s Terminal Count (TC) is
reached. See the Software section of this document for de­tails on the operation and programming of the DMA control­ler.

Local Arbiter

Devices requesting control of the Micro Channel must im­plement logic known as a Local Arbiter. The Arbiter logic
must drive the arbitration bus in a manner that allows all
competing devices to recognize a winner.

When the Central Arbiter starts an aribtration, a competing
local arbiter drives its vector onto the ARB bus. At the same
time, it compares that vector to the value appearing on the
bus on a bit-by-bit basis beginning with the most significant
bit, ARB3. If it finds a mismatch on one of the bits, it will
cease driving that bit and all lower order bits. If it subse­quently finds a match on that bit, it will continue driving low­er order bits until another mismatch is detected. The arbitra­tion bus must be driven by open collector drivers so that
multiple devices may drive the bus and compete for service.
The following is an example of a bus arbitration:

1. Devices A and B, with arbitration levels 1001 and 0110

for more than 7.8 ms (thus 7.8 ms is the maxi-

and S1) are inactive (signifying the

signal. In this case, the controller will exe-

respectively, compete for the channel. Both devices drive
their vectors onto the ARB bus which then appears as

0000.

active, thus postponing

or CMD go inactive, which-

sig-

7

2. Device A detects a mismatch on ARB3 so it ceases driv­ing all lower order bits. Device B sees a mismatch on
ARB2 so it stops driving its lower order bits. The bus now
shows 0111.

3. Device B now sees a match on ARB2 so it continues to
drive its lower order bits (only ARB0 in this case).

4. The bus now stabilizes at a value of 0110 and device B
has won control of the channel.

PC16552C ADAPTER DMA INTERFACE DESIGN

Design Considerations

The PC16552C Adapter contains not one but four indepen­dent devices which may request DMA service. These ‘‘de­vices’’ are the four on-board FIFOs (two Transmit and two
Receive). Each FIFO has an independent request signal
which indicates when it is empty (transmitters) or when it is
full (receivers). These signals are named TXRDY1
TXRDY2

, RXRDY1 and RXRDY2. This creates some free­dom in the design of the interface between the UART re­quests and the Micro Channel. However, there is a severe
timing limitation concerning the termination of a burst cycle
that adds constraints to the design.

The design freedom lies in where the competition between
the four UART request takes place. One possibility is to
have them compete against each at the system level during
the central arbitration cycle. This requires the adapter to
implement four Local Arbiters, one for each UART request.
At the other end of the spectrum, the adapter may imple­ment prioritization logic that allows only one of the requests
to compete for the channel at a time. Thus only one Local
Arbiter is needed. The designer may also choose a compro­mise such as prioritizing the receiver and transmitter re­quests separately and using two Local Arbiters. Using four
separate Local Arbiters simplifies the overall design by elim-

inating the UART request prioritization. However, it creates
duplication of functionality (the same logic implemented four
times) and will generate a higher component cost. The
PC16552C Adapter is designed with the latter implementa­tion.

One particular timing specification required by the Micro
Channel when a DMA slave terminates a burst cycle is the
most critical issue in the design of a useful DMA-serviced
serial port. The goal of the DMA interface design is to be
able to transfer four files simultaneously in two directions
with attention from the CPU only at the beginning and end
of the file transfers. This can only be accomplished by con­tinually performing FIFO-sized burst transfers (16 bytes) in
response to UART FIFO requests until the DMA controller
reaches its programmed Terminal Count (end of the file).
This type of operation is called slave-terminated burst mode
and requires the UART to terminate a burst as soon as its

,

FIFO has been filled or emptied by the controller.

DMA controller-terminated transfers can also be used but
requires the DMA controller to be programmed with the
number of bytes to be transferred to or from a FIFO instead
of with the total number of bytes in a file. The controller
must be reprogrammed after every transfer which requires
much more attention from the CPU than with slave-terminat­ed transfers.

When the DMA controller writes the byte that fills a Transmit
FIFO or reads the last byte in a Receiver FIFO, the
PC16552C deasserts the appropriate DMA request. The re­quest signal passes through the logic on the adapter and
deasserts the BURST
minimum time that BURST

signal. The Micro Channel specifies a

be inactive high before the end
of a bus cycle in order to stop a burst without an additional
byte transfer. This is the critical timing issue. The timing
diagram in

Figure 1

illustrates the signals and delays in-

volved.

Timing Parameters:

tR/W: Time to decode S0, S1 and M/IO signals into IOR and IOW strobes.

tRXI/tWXI: RXRDYTXRDY

tLOG: Propagation delay of request signal through logic controlling BURST

tRC: RC restoration of BURST

t56: BURST

inactive high setup to CMD inactiveÐMicro Channel specifies 35 ns minimum.

inactive from leading edge of read and write strobes respectively (PC16552C DMA request signal spec).

on the Micro Channel.

TL/F/11195– 2

.

FIGURE 1

8