National Semiconductor OP-07 Technical data
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OP-07 Low Offset, Low Drift Operational Amplifier
OP-07 Low Offset, Low Drift Operational Amplifier
December 1994
General Description
The OP-07 has very low input offset voltage which is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The
OP-07 also features low input bias current and high openloop gain. The low offsets and high open-loop gain make
the OP-07 particularly useful for high-gain applications.
The wide input voltage range of
g
13V minimum combined
with high CMRR of 110 dB and high input impedance provide high accuracy in the non-inverting circuit configuration.
Excellent linearity and gain accuracy can be maintained
even at high closed-loop gains.
Stability of offsets and gain with time or variation in temperature is excellent.
The OP-07 is available in TO-99 metal can, ceramic or
molded DIP.
For improved specifications, see the LM607.
Connection Diagram
Dual-In-Line Package
See NS Package Number N08E
Ordering Information
e
T
25§C
A
V
Max
OS
(mV) Range
75 OP07EP COM
150 OP07CP COM
150 OP07DP COM
*Also available per SMDÝ8203602
Plastic
Features
Y
Low V
OS
Y
Low VOSDrift 0.6 mV/§C Max
Y
Ultra-Stable vs Time 1.0 mV/Month Max
Y
Low Noise 0.6 mVp-p Max
Y
Wide Input Voltage Range
Y
Wide Supply Voltage Range
Y
Fits 725/108A/308A, 741, AD510 Sockets
Y
Replaces the mA714
Applications
Y
Strain Gauge Amplifiers
Y
Thermocouple Amplifiers
Y
Precision Reference Buffer
Y
Analog Computing Functions
TL/H/10550– 1
N08E
Operating
Temperature
75 mV Max
g
3V tog18V
g
14V
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/H/10550
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Internal Power Dissipation (Note 5) 500 mW
Differential Input Voltage
Input Voltage (Note 6)
Output Short-Circuit Duration Continuous
g
22V
g
30V
g
22V
Simplified Schematic
Storage Temperature Range
Lead Temperature (Soldering, 60 sec.) 260§C
Junction Temperature
b
65§Ctoa150§C
b
65§Ctoa150§C
Operating Temperature Range
OP-07E, OP-07C, OP-07D 0§Ctoa70§C
*R2A and R2B are electronically trimmed on chip at the factory for minimum offset voltage.
2
TL/H/10550– 3
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