National Semiconductor OP-07 Technical data

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OP-07 Low Offset, Low Drift Operational Amplifier
OP-07 Low Offset, Low Drift Operational Amplifier
December 1994
General Description
The OP-07 has very low input offset voltage which is ob­tained by trimming at the wafer stage. These low offset volt­ages generally eliminate any need for external nulling. The OP-07 also features low input bias current and high open­loop gain. The low offsets and high open-loop gain make the OP-07 particularly useful for high-gain applications.
The wide input voltage range of
g
13V minimum combined with high CMRR of 110 dB and high input impedance pro­vide high accuracy in the non-inverting circuit configuration. Excellent linearity and gain accuracy can be maintained even at high closed-loop gains.
Stability of offsets and gain with time or variation in temper­ature is excellent.
The OP-07 is available in TO-99 metal can, ceramic or molded DIP.
For improved specifications, see the LM607.
Connection Diagram
Dual-In-Line Package
See NS Package Number N08E
Ordering Information
e
T
25§C
A
V
Max
OS
(mV) Range
75 OP07EP COM
150 OP07CP COM
150 OP07DP COM
*Also available per SMDÝ8203602
Plastic
Features
Y
Low V
OS
Y
Low VOSDrift 0.6 mV/§C Max
Y
Ultra-Stable vs Time 1.0 mV/Month Max
Y
Low Noise 0.6 mVp-p Max
Y
Wide Input Voltage Range
Y
Wide Supply Voltage Range
Y
Fits 725/108A/308A, 741, AD510 Sockets
Y
Replaces the mA714
Applications
Y
Strain Gauge Amplifiers
Y
Thermocouple Amplifiers
Y
Precision Reference Buffer
Y
Analog Computing Functions
TL/H/10550– 1
N08E
Operating
Temperature
75 mV Max
g
3V tog18V
g
14V
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/H/10550
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage
Internal Power Dissipation (Note 5) 500 mW
Differential Input Voltage
Input Voltage (Note 6)
Output Short-Circuit Duration Continuous
g
22V
g
30V
g
22V
Simplified Schematic
Storage Temperature Range
Lead Temperature (Soldering, 60 sec.) 260§C
Junction Temperature
b
65§Ctoa150§C
b
65§Ctoa150§C
Operating Temperature Range
OP-07E, OP-07C, OP-07D 0§Ctoa70§C
*R2A and R2B are electronically trimmed on chip at the factory for minimum offset voltage.
2
TL/H/10550– 3
Electrical Characteristics
Unless otherwise specified, V
e
g
S
15V, T
e
25§C. Boldface type refers to limits over 0§CsT
A
Symbol Parameter Conditions
OP-07E OP-07C
s
70§C
A
Min Typ Max Min Typ Max
V
V
I
OS
I
B
e
e
i
np-p
i
n
R
R
IVR Input Voltage Range
CMRR Common-Mode V
PSRR Power Supply V
AVOLarge Signal R
V
SR Slew Rate R
BW Closed-Loop Bandwidth A
R
P
Input Offset Voltage (Note 1) 30 75 60 150
OS
OS/t
Long-Term V Stability
OS
(Note 2)
45 130 85 250
0.3 1.5 0.4 2.0 mV/Mo
Input Offset Current 0.5 3.8 0.8 6.0
0.9 5.3 1.6 8.0
Input Bias Current
Input Noise Voltage 0.1 Hz to 10 Hz (Note 3) 0.35 0.6 0.38 0.65 mV
np-p
Input Noise Voltage f
n
Density f
e
10 Hz 10.3 18.0 10.5 20.0
O
e
100 Hz (Note 3) 10.0 13.0 10.2 13.5 nV/0Hz
O
e
f
1000 Hz 9.6 11.0 9.8 11.5
O
g
1.2g4.0
g
1.5g5.5
g
Input Noise Current 0.1 Hz to 10 Hz (Note 3) 14 30 15 35 pA
Input Noise Current f Density f
Input Resistance (Note 4)
IN
Differential-Mode
Input Resistance
INCM
Common-Mode
Rejection Ratio 103 123 97 120
Rejection Ratio V
Voltage Gain R
Output Voltage Swing R
O
Output Resistance V
O
Power Consumption V
d
Offset Adj. Range R
e
10 Hz 0.32 0.80 0.35 0.90
O
e
100 Hz (Note 3) 0.14 0.23 0.15 0.27 pA/0Hz
O
e
f
1000 Hz 0.12 0.17 0.13 0.18
O
15 50 8 33 MX
160 120 GX
g
13.0g14.0
e
g
13V 106 123 100 120
CM
e
g
3V tog18V 5 20 7 32
S
e
g
3V tog18V 732 1051
S
t
L
t
L
t
R
L
e
V
S
t
L
t
R
L
t
R
L
t
R
L
t
L
VCL
e
O
e
S
e
V
S
e
P
e
2kX,V 2kX 180 450 100 400 V/mV 500X,V
g
3V (Note 4)
10 kX 2kX 2kX 1kX
g
10V 200 500 120 400
O
e
g
0.5V,
O
150 400 100 400
g
12.5g13.0
g
12.0g12.8
g
12.0g12.6
g
10.5g12.0
2kX(Note 3) 0.1 0.3 0.1 0.3 V/ms
ea
1 (Note 3) 0.4 0.6 0.4 0.6 MHz
e
0, I
060 60X
O
g
15V, No Load 75 120 80 150
g
3V, No Load 4 6 4 8
20 kX
g
4
g
13
g
12.0g13.0
g
11.5g12.8
g
11.0g12.6
g
g
1.8g7.0
2.2g9.0
g
14 V
12.0
g
4mV
TCVOSAverage Input Offset (Note 4) 0.3 1.3 0.5 1.8
Voltage Drift Without External Trim
TCVOSn With External Trim R
TCI
TCI
Average Input Offset (Note 3)
OS
Current Drift
Average Input Bias (Note 3)
B
Current Drift
e
20 kX (Note 4) 0.3 1.3 0.4 1.6
P
835 1250pA/
13 35 18 50 pA/
3
Units
mV
nA
nA
dB
mV/V
V
mW
mV/
p-p
p-p
C
§
C
§
C
§
Electrical Characteristics
Unless otherwise specified, V
e
g
S
15V, T
e
25§C. Boldface type refers to limits over 0§CsT
A
Symbol Parameter Conditions
V
V
I
OS
I
B
e
e
i
np-p
i
n
R
R
OS
OS/t
np-p
n
IN
INCM
Input Offset Voltage (Note 1) 60 150
Long-Term VOSStability (Note 2) 0.5 3.0 mV/Mo
Input Offset Current 0.8 6.0
Input Bias Current
Input Noise Voltage 0.1 Hz to 10 Hz (Note 3) 0.38 0.65 mVp-p
Input Noise Voltage Density f
e
10 Hz 10.5 20.0
O
e
f
100 Hz (Note 3) 10.3 13.5 nV/0Hz
O
e
f
1000 Hz 9.8 11.5
O
Input Noise Current 0.1 Hz to 10 Hz (Note 3) 15 35 pAp-p
Input Noise Current Density f
e
10 Hz 0.35 0.90 pA/0Hz
O
e
f
100 Hz (Note 3) 0.15 0.27
O
e
f
1000 Hz 0.13 0.18
O
Input Resistance Differential-Mode (Note 4) 7 31 MX
Input Resistance Common-Mode 120 GX
IVR Input Voltage Range
e
CMRR Common-Mode V
Rejection Ratio 94 106
PSRR Power Supply V
Rejection Ratio 10 51
A
VO
V
O
Large Signal R Voltage Gain R
Output Voltage Swing R
SR Slew Rate R
BW Closed-Loop Bandwidth A
RO Output Resistance V
P
d
Power Consumption V
Offset Adj. Range R
TCV
Average Input Offset (Note 4) 0.7 2.5 mV/§C
OS
Voltage Drift Without
g
13V 94 110
CM
e
g
3V tog18V 7 32 mV/V
S
s
2kX,V
L
e
L
t
R
L
g
V
S
t
L
t
R
L
t
R
L
t
R
L
t
L
VCL
O
e
S
e
V
S
P
O
2kX,V
O
500X,V
O
3V (Note 4)
10 kX 2kX 2kX 1kX
2kX(Note 3) 0.1 0.3 V/ms
ea
1 (Note 3) 0.4 0.6 MHz
e
e
0, I
060X
O
g
15V, No Load 80 150
g
3V, No Load 4 8
e
20 kX
External Trim
TCV
n With External Trim R
OS
TCI
TCI
Note 1: VOSis measured approximately 0.5 second after application of power.
Note 2: Long-Term Offset Voltage Stability refers to the averaged trend line of V
Excluding the initial hour of operation, changes in V
Note 3: Sample Tested.
Note 4: Guaranteed by design.
Average Input Offset Current Drift (Note 3) 12 50 pA/§C
OS
Average Input Bias Current Drift (Note 3) 18 50 pA/§C
B
during the first 30 operating days are typically 2.5 mV. Parameter is sample tested.
OS
e
20 kX (Note 4) 0.7 2.5 mV/§C
P
s
a
70§C
A
OP-07D
Min Typ Max
85 250
1.6 8.0
g
g
g
e
g
10V 120 400
e
g
10V 100 400
e
g
0.5V,
g
12.0
g
11.5
g
11.0g12.6
vs Time over extended periods after the first 30 days of operation.
OS
g
13
400
g
g
g
g
g
2.0
12.0
3.0g14.0
14 V
13.0
12.8
12.0
4mV
Units
mV
nA
nA
dB
V/mV
V
mW
4
Test Circuits
Offset Voltage Test Circuit
Low Frequency Noise Test Circuit
TL/H/10550– 4
Optional Offset Nulling Circuit
TL/H/10550– 5
TL/H/10550– 6
5
Physical Dimensions inches (millimeters) (Continued)
Order Number OP-07EP, OP-07CP or OP-07DP
NS Package Number N08E
OP-07 Low Offset, Low Drift Operational Amplifier
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user.
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