The OP-07 has very low input offset voltage which is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The
OP-07 also features low input bias current and high openloop gain. The low offsets and high open-loop gain make
the OP-07 particularly useful for high-gain applications.
The wide input voltage range of
g
13V minimum combined
with high CMRR of 110 dB and high input impedance provide high accuracy in the non-inverting circuit configuration.
Excellent linearity and gain accuracy can be maintained
even at high closed-loop gains.
Stability of offsets and gain with time or variation in temperature is excellent.
The OP-07 is available in TO-99 metal can, ceramic or
molded DIP.
For improved specifications, see the LM607.
Connection Diagram
Dual-In-Line Package
See NS Package Number N08E
Ordering Information
e
T
25§C
A
V
Max
OS
(mV)Range
75OP07EPCOM
150OP07CPCOM
150OP07DPCOM
*Also available per SMDÝ8203602
Plastic
Features
Y
Low V
OS
Y
Low VOSDrift0.6 mV/§C Max
Y
Ultra-Stable vs Time1.0 mV/Month Max
Y
Low Noise0.6 mVp-p Max
Y
Wide Input Voltage Range
Y
Wide Supply Voltage Range
Y
Fits 725/108A/308A, 741, AD510 Sockets
Y
Replaces the mA714
Applications
Y
Strain Gauge Amplifiers
Y
Thermocouple Amplifiers
Y
Precision Reference Buffer
Y
Analog Computing Functions
TL/H/10550– 1
N08E
Operating
Temperature
75 mV Max
g
3V tog18V
g
14V
C
1995 National Semiconductor CorporationRRD-B30M115/Printed in U. S. A.
TL/H/10550
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Internal Power Dissipation (Note 5)500 mW
Differential Input Voltage
Input Voltage (Note 6)
Output Short-Circuit DurationContinuous
g
22V
g
30V
g
22V
Simplified Schematic
Storage Temperature Range
Lead Temperature (Soldering, 60 sec.)260§C
Junction Temperature
b
65§Ctoa150§C
b
65§Ctoa150§C
Operating Temperature Range
OP-07E, OP-07C, OP-07D0§Ctoa70§C
*R2A and R2B are electronically trimmed on chip at the factory for minimum offset voltage.
2
TL/H/10550– 3
Electrical Characteristics
Unless otherwise specified, V
e
g
S
15V, T
e
25§C. Boldface type refers to limits over 0§CsT
A
SymbolParameterConditions
OP-07EOP-07C
s
70§C
A
MinTypMaxMinTypMax
V
V
I
OS
I
B
e
e
i
np-p
i
n
R
R
IVRInput Voltage Range
CMRRCommon-ModeV
PSRRPower SupplyV
AVOLarge SignalR
V
SRSlew RateR
BWClosed-Loop Bandwidth A
R
P
Input Offset Voltage(Note 1)307560150
OS
OS/t
Long-Term V
Stability
OS
(Note 2)
4513085250
0.31.50.42.0mV/Mo
Input Offset Current0.53.80.86.0
0.95.31.68.0
Input Bias Current
Input Noise Voltage0.1 Hz to 10 Hz (Note 3)0.350.60.380.65mV
np-p
Input Noise Voltagef
n
Densityf
e
10 Hz10.318.010.520.0
O
e
100 Hz (Note 3)10.013.010.213.5 nV/0Hz
O
e
f
1000 Hz9.611.09.811.5
O
g
1.2g4.0
g
1.5g5.5
g
Input Noise Current0.1 Hz to 10 Hz (Note 3)14301535pA
Input Noise Currentf
Densityf
Input Resistance(Note 4)
IN
Differential-Mode
Input Resistance
INCM
Common-Mode
Rejection Ratio10312397120
Rejection RatioV
Voltage GainR
Output Voltage SwingR
O
Output ResistanceV
O
Power ConsumptionV
d
Offset Adj. RangeR
e
10 Hz0.320.800.350.90
O
e
100 Hz (Note 3)0.140.230.150.27 pA/0Hz
O
e
f
1000 Hz0.120.170.130.18
O
1550833MX
160120GX
g
13.0g14.0
e
g
13V106123100120
CM
e
g
3V tog18V520732
S
e
g
3V tog18V7321051
S
t
L
t
L
t
R
L
e
V
S
t
L
t
R
L
t
R
L
t
R
L
t
L
VCL
e
O
e
S
e
V
S
e
P
e
2kX,V
2kX180450100400V/mV
500X,V
g
3V (Note 4)
10 kX
2kX
2kX
1kX
g
10V200500120400
O
e
g
0.5V,
O
150400100400
g
12.5g13.0
g
12.0g12.8
g
12.0g12.6
g
10.5g12.0
2kX(Note 3)0.10.30.10.3V/ms
ea
1 (Note 3)0.40.60.40.6MHz
e
0, I
060 60X
O
g
15V, No Load7512080150
g
3V, No Load4648
20 kX
g
4
g
13
g
12.0g13.0
g
11.5g12.8
g
11.0g12.6
g
g
1.8g7.0
2.2g9.0
g
14V
12.0
g
4mV
TCVOSAverage Input Offset(Note 4)0.31.30.51.8
Voltage Drift Without
External Trim
TCVOSn With External TrimR
TCI
TCI
Average Input Offset(Note 3)
OS
Current Drift
Average Input Bias(Note 3)
B
Current Drift
e
20 kX (Note 4)0.31.30.41.6
P
8351250pA/
13351850pA/
3
Units
mV
nA
nA
dB
mV/V
V
mW
mV/
p-p
p-p
C
§
C
§
C
§
Electrical Characteristics
Unless otherwise specified, V
e
g
S
15V, T
e
25§C. Boldface type refers to limits over 0§CsT
A
SymbolParameterConditions
V
V
I
OS
I
B
e
e
i
np-p
i
n
R
R
OS
OS/t
np-p
n
IN
INCM
Input Offset Voltage(Note 1)60150
Long-Term VOSStability(Note 2)0.53.0mV/Mo
Input Offset Current0.86.0
Input Bias Current
Input Noise Voltage0.1 Hz to 10 Hz (Note 3)0.380.65mVp-p
Input Noise Voltage Densityf
e
10 Hz10.520.0
O
e
f
100 Hz (Note 3)10.313.5nV/0Hz
O
e
f
1000 Hz9.811.5
O
Input Noise Current0.1 Hz to 10 Hz (Note 3)1535pAp-p
Input Noise Current Densityf
e
10 Hz0.350.90pA/0Hz
O
e
f
100 Hz (Note 3)0.150.27
O
e
f
1000 Hz0.130.18
O
Input Resistance Differential-Mode(Note 4)731MX
Input Resistance Common-Mode120GX
IVRInput Voltage Range
e
CMRRCommon-ModeV
Rejection Ratio94106
PSRRPower SupplyV
Rejection Ratio1051
A
VO
V
O
Large SignalR
Voltage GainR
Output Voltage SwingR
SRSlew RateR
BWClosed-Loop BandwidthA
ROOutput ResistanceV
P
d
Power ConsumptionV
Offset Adj. RangeR
TCV
Average Input Offset(Note 4)0.72.5mV/§C
OS
Voltage Drift Without
g
13V94110
CM
e
g
3V tog18V732mV/V
S
s
2kX,V
L
e
L
t
R
L
g
V
S
t
L
t
R
L
t
R
L
t
R
L
t
L
VCL
O
e
S
e
V
S
P
O
2kX,V
O
500X,V
O
3V (Note 4)
10 kX
2kX
2kX
1kX
2kX(Note 3)0.10.3V/ms
ea
1 (Note 3)0.40.6MHz
e
e
0, I
060X
O
g
15V, No Load80150
g
3V, No Load48
e
20 kX
External Trim
TCV
nWith External TrimR
OS
TCI
TCI
Note 1: VOSis measured approximately 0.5 second after application of power.
Note 2: Long-Term Offset Voltage Stability refers to the averaged trend line of V
Excluding the initial hour of operation, changes in V
Note 3: Sample Tested.
Note 4: Guaranteed by design.
Average Input Offset Current Drift(Note 3)1250pA/§C
OS
Average Input Bias Current Drift(Note 3)1850pA/§C
B
during the first 30 operating days are typically 2.5 mV. Parameter is sample tested.
OS
e
20 kX (Note 4)0.72.5mV/§C
P
s
a
70§C
A
OP-07D
MinTypMax
85250
1.68.0
g
g
g
e
g
10V120400
e
g
10V100400
e
g
0.5V,
g
12.0
g
11.5
g
11.0g12.6
vs Time over extended periods after the first 30 days of operation.
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or2. A critical component is any component of a life
systems which, (a) are intended for surgical implantsupport device or system whose failure to perform can
into the body, or (b) support or sustain life, and whosebe reasonably expected to cause the failure of the life
failure to perform, when properly used in accordancesupport device or system, or to affect its safety or
with instructions for use provided in the labeling, caneffectiveness.
be reasonably expected to result in a significant injury
to the user.
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Fax: 1(800) 737-7018English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.