National Semiconductor NS32081-10, NS32081-15 User Manual

NS32081-10/NS32081-15 Floating-Point Units

NS32081-10/NS32081-15 Floating-Point Units

July 1988

General Description

The NS32081 Floating-Point Unit functions as a slave proc­essor in National Semiconductor’s Series 32000

É

micro­processor family. It provides a high-speed floating-point in­struction set for any Series 32000 family CPU, while remain­ing architecturally consistent with the full two-address archi­tecture and powerful addressing modes of the Series 32000
micro-processor family.

Block Diagram

Features

Y

Eight on-chip data registers

Y

32-bit and 64-bit operations

Y

Supports proposed IEEE standard for binary floating­point arithmetic, Task P754

Y

Directly compatible with NS32016, NS32008 and
NS32032 CPUs

Y

High-speed XMOSTMtechnology

Y

Single 5V supply

Y

24-pin dual in-line package

TRI-STATEÉand Series 32000Éare registered trademarks of National Semiconductor Corp.

TM

XMOS

is a trademark of National Semiconductor Corp.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/EE/5234

TL/EE/5234– 1

Table of Contents

1.0 PRODUCT INTRODUCTION

1.1 Operand Formats

1.1.1 Normalized Numbers

1.1.2 Zero

1.1.3 Reserved Operands

1.1.4 Integers

1.1.5 Memory Representations

2.0 ARCHITECTURAL DESCRIPTION

2.1 Programming Model

2.1.1 Floating-Point Registers

2.1.2 Floating-Point Status Register (FSR)

2.1.2.1 FSR Mode Control Fields

2.1.2.2 FSR Status Fields

2.1.2.3 FSR Software Field (SWF)

2.2 Instruction Set

2.2.1 General Instruction Format

2.2.2 Addressing Modes

2.2.3 Floating-Point Instruction Set

2.3 Traps

3.0 FUNCTIONAL DESCRIPTION

3.1 Power and Grounding

3.2 Clocking

3.3 Resetting

3.0 FUNCTIONAL DESCRIPTION (Continued)

3.4 Bus Operation

3.4.1 Bus Cycles

3.4.2 Operand Transfer Sequences

3.5 Instruction Protocols

3.5.1 General Protocol Sequence

3.5.2 Floating-Point Protocols

4.0 DEVICE SPECIFICATIONS

4.1 Pin Descriptions

4.1.1 Supplies

4.1.2 Input Signals

4.1.3 Input/Output Signals

4.2 Absolute Maximum Ratings

4.3 Electrical Characteristics

4.4 Switching Characteristics

4.4.1 Definitions

4.4.2 Timing Tables

4.4.2.1 Output Signals: Internal Propagation De­lays

4.4.2.2 Input Signals Requirements

4.4.2.3 Clocking Requirements

4.4.3 Timing Diagrams

2

List of Illustrations

Floating-Point Operand Formats ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА1-1

Register Set ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА2-1

The Floating-Point Status Register ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА2-2

General Instruction Format АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА2-3

Index Byte Format ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА2-4

Displacement EncodingsАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА2-5

Floating-Point Instruction FormatsАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА2-6

Recommended Supply Connections АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА3-1

Power-On Reset Requirements АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА3-2

General Reset Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА3-3

System Connection Diagram АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА3-4

Slave Processor Read CycleААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА3-5

Slave Processor Write CycleААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА3-6

FPU Protocol Status Word FormatАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА3-7

Dual-In-Line PackageААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА4-1

Timing Specification Standard (Signal Valid After Clock Edge)АААААААААААААААААААААААААААААААААААААААААААААААААААААААА4-2

Timing Specification Standard (Signal Valid Before Clock Edge) АААААААААААААААААААААААААААААААААААААААААААААААААААААА4-3

Clock Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА4-4

Power-On-Reset ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА4-5

Non-Power-On-ResetААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА4-6

Read Cycle From FPU АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА4-7

Write Cycle To FPU АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА4-8

Pulse from FPU ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА4-9

SPC

RST Release Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА4-10

List of Tables

Sample F Fields ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА1-1

Sample E Fields ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА1-2

Normalized Number RangesААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА1-3

Series 32000 Family Addressing ModesААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА2-1

General Instruction Protocol ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА3-1

Floating-Point Instruction ProtocolsААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА3-2

3

1.0 Product Introduction

The NS32081 Floating-Point Unit (FPU) provides high
speed floating-point operations for the Series 32000 family,
and is fabricated using National high-speed XMOS technol­ogy. It operates as a slave processor for transparent expan­sion of the Series 32000 CPU’s basic instruction set. The
FPU can also be used with other microprocessors as a pe­ripheral device by using additional TTL interface logic. The
NS32081 is compatible with the IEEE Floating-Point For­mats by means of its hardware and software features.

1.1 OPERAND FORMATS

The NS32081 FPU operates on two floating-point data
typesÐsingle precision (32 bits) and double precision (64
bits). Floating-point instruction mnemonics use the suffix F
(Floating) to select the single precision data type, and the
suffix L (Long Floating) to select the double precision data
type.

A floating-point number is divided into three fields, as shown
in

Figure 1-1

.

The F field is the fractional portion of the represented num­ber. In Normalized numbers (Section 1.1.1), the binary point
is assumed to be immediately to the left of the most signifi­cant bit of the F field, with an implied 1 bit to the left of the
binary point. Thus, the F field represents values in the range

sxs

1.0

2.0.

TABLE 1-1. Sample F Fields

F Field Binary Value Decimal Value

000...0 1.000...0 1.000...0

010...0 1.010...0 1.250...0

100...0 1.100...0 1.500...0

110...0 1.110...0 1.750...0

u

Implied Bit

The E field contains an unsigned number that gives the bi­nary exponent of the represented number. The value in the
E field is biased; that is, a constant bias value must be sub­tracted from the E field value in order to obtain the true
exponent. The bias value is 011...11
(single precision) or 1023 (double precision). Thus, the true
exponent can be either positive or negative, as shown in
Table 1-2.

, which is either 127

2

TABLE 1-2. Sample E Fields

E Field F Field Represented Value

011...110 100...0 1.5

011...111 100...0 1.5

100...000 100...0 1.5

b

1

c

e

2

0.75

0

c

e

2

1.50

1

c

e

2

3.00

Two values of the E field are not exponents. 11...11 sig­nals a reserved operand (Section 2.1.3). 00...00 repre­sents the number zero if the F field is also all zeroes, other­wise it signals a reserved operand.

The S bit indicates the sign of the operand. It is 0 for posi­tive and 1 for negative. Floating-point numbers are in sign­magnitude form, that is, only the S bit is complemented in
order to change the sign of the represented number.

1.1.1 Normalized Numbers

Normalized numbers are numbers which can be expressed
as floating-point operands, as described above, where the E
field is neither all zeroes nor all ones.

The value of a Normalized number can be derived by the
formula:

S

(E-Bias)

c

b

(

1)

c

2

(1aF)

The range of Normalized numbers is given in Table 1-3.

1.1.2 Zero

There are two representations for zeroÐpositive and nega­tive. Positive zero has all-zero F and E fields, and the S bit is
zero. Negative zero also has all-zero F and E fields, but its S
bit is one.

1.1.3 Reserved Operands

The proposed IEEE Standard for Binary Floating-Point Arith­metic (Task P754) provides for certain exceptional forms of
floating-point operands. The NS32081 FPU treats these
forms as reserved operands. The reserved operands are:

Positive and negative infinity

#

Not-a-Number (NaN) values

#

Denormalized numbers

#

Both Infinity and NaN values have all ones in their E fields.
Denormalized numbers have all zeroes in their E fields and
non-zero values in their F fields.

The NS32081 FPU causes an Invalid Operation trap (Sec­tion 2.1.2.2) if it receives a reserved operand, unless the
operation is simply a move (without conversion). The FPU
does not generate reserved operands as results.

63 62 52 51 0

SE F

111 52

FIGURE 1-1. Floating-Point Operand Formats

Single Precision

31 30 23 22 0

SE F

18 23

Double Precision

4

1.0 Product Introduction (Continued)

TABLE 1-3. Normalized Number Ranges

Single Precision Double Precision

Most Positive 2

Least Positive 2

Least Negative

Most Negative

Note: The values given are extended one full digit beyond their represented accuracy to help in generating rounding and conversion algorithms.

127

e

3.40282346c10

b

e

1.17549436c10

b

(2

eb

b

2

eb

1.1.4 Integers

In addition to performing floating-point arithmetic, the
NS32081 FPU performs conversions between integer and
floating-point data types. Integers are accepted or generat­ed by the FPU as two’s complement values of byte (8 bits),
word (16 bits) or double word (32 bits) length.

1.1.5 Memory Representations

The NS32081 FPU does not directly access memory. How­ever, it is cooperatively involved in the execution of a set of
two-address instructions with its Series 32000 Family CPU.
The CPU determines the representation of operands in
memory.

In the Series 32000 family of CPUs, operands are stored in
memory with the least significant byte at the lowest byte
address. The only exception to this rule is the Immediate
addressing mode, where the operand is held (within the in­struction format) with the most significant byte at the lowest
address.

2.0 Architectural Description

b

23

c

(2b2

126

b

126

)

1.17549436c10

c

(2b2

b

127

3.40282346c10

)2

38

b

38

b

38

23

)

38

1023

e

1.7976931348623157c10

b

1022

2

e

2.2250738585072014c10

b

(2

eb

1023

b

2

eb

2.1.1 Floating-Point Registers

There are eight registers (F0–F7) on the NS32081 FPU for
providing high-speed access to floating-point operands.
Each is 32 bits long. A floating-point register is referenced
whenever a floating-point instruction uses the Register ad­dressing mode (Section 2.2.2) for a floating-point operand.
All other Register mode usages (i.e., integer operands) refer
to the General Purpose Registers (R0 –R7) of the CPU, and
the FPU transfers the operand as if it were in memory.
When the Register addressing mode is specified for a dou­ble precision (64-bit) operand, a pair of registers holds the
operand. The programmer must specify the even register of
the pair. The even register contains the least significant half
of the operand and the next consecutive register contains
the most significant half.

2.1.2 Floating-Point Status Register (FSR)

The Floating-Point Status Register (FSR) selects operating
modes and records any exceptional conditions encountered
during execution of a floating-point operation.
shows the format of the FSR.

2.1 PROGRAMMING MODEL

The Series 32000 architecture includes nine registers that
are implemented on the NS32081 Floating-Point Unit (FPU).

FIGURE 2-2. The Floating-Point Status Register

2.1.2.1 FSR Mode Control Fields

The FSR mode control fields select FPU operation modes.
The meanings of the FSR mode control bits are given be­low.

Rounding Mode (RM): Bits 7 and 8. This field selects the
rounding method. Floating-point results are rounded when­ever they cannot be exactly represented. The rounding
modes are:

00 Round to nearest value. The value which is nearest to

the exact result is returned. If the result is exactly half­way between the two nearest values the even value

e

(LSB

0) is returned.

FIGURE 2-1. Register Set

TL/EE/5234– 4

01 Round toward zero. The nearest value which is closer to

zero or equal to the exact result is returned.

b

52

c

(2b2

b

1022

)

)

2.2250738585072014c10

b

(2b2

52

)

c

1.7976931348623157c10

308

b

308

b

308

308

Figure 2-2

TL/EE/5234– 5

5

2.0 Architectural Description (Continued)

10 Round toward positive infinity. The nearest value which

is greater than or equal to the exact result is returned.

11 Round toward negative infinity. The nearest value which

is less than or equal to the exact result is returned.

Underflow Trap Enable (UEN): Bit 3. If this bit is set, the
FPU requests a trap whenever a result is too small in abso­lute value to be represented as a normalized number. If it is
not set, any underflow condition returns a result of exactly
zero.

Inexact Result Trap Enable (IEN): Bit 5. If this bit is set,
the FPU requests a trap whenever the result of an operation
cannot be represented exactly in the operand format of the
destination. If it is not set, the result is rounded according to
the selected rounding mode.

2.1.2.2 FSR Status Fields

The FSR Status Fields record exceptional conditions en­countered during floating-point data processing. The mean­ings of the FSR status bits are given below:

Trap Type (TT): bits 0-2. This 3-bit field records any excep­tional condition detected by a floating-point instruction. The
TT field is loaded with zero whenever any floating-point in­struction except LFSR or SFSR completes without encoun­tering an exceptional condition. It is also set to zero by a
hardware reset or by writing zero into it with the Load FSR
(LFSR) instruction. Underflow and Inexact Result are always
reported in the TT field, regardless of the settings of the
UEN and IEN bits.

000 No exceptional condition occurred.

001 Underflow. A non-zero floating-point result is too small

in magnitude to be represented as a normalized float­ing-point number in the format of the destination oper­and. This condition is always reported in the TT field
and UF bit, but causes a trap only if the UEN bit is set. If
the UEN bit is not set, a result of Positive Zero is pro­duced, and no trap occurs.

010 Overflow. A result (either floating-point or integer) of a

floating-point instruction is too great in magnitude to be
held in the format of the destination operand. Note that
rounding, as well as calculations, can cause this condi­tion.

011 Divide by zero. An attempt has been made to divide a

non-zero floating-point number by zero. Dividing zero by
zero is considered an Invalid Operation instead (below).

100 Illegal Instruction. Two undefined floating-point instruc-

tion forms are detected by the FPU as being illegal. The
binary formats causing this trap are:

xxxxxxxxxx0011xx10111110

xxxxxxxxxx1001xx10111110

101 Invalid Operation. One of the floating-point operands of

a floating-point instruction is a Reserved operand, or an
attempt has been made to divide zero by zero using the
DIVf instruction.

110 Inexact Result. The result (either floating-point or inte-

ger) of a floating-point instruction cannot be represent­ed exactly in the format of the destination operand, and
a rounding step must alter it to fit. This condition is al­ways reported in the TT field and IF bit unless any other
exceptional condition has occurred in the same instruc­tion. In this case, the TT field always contains the code
for the other exception and the IF bit is not altered. A
trap is caused by this condition only if the IEN bit is set;
otherwise the result is rounded and delivered, and no
trap occurs.

111 (Reserved for future use.)

Underflow Flag (UF): Bit 4. This bit is set by the FPU when­ever a result is too small in absolute value to be represented
as a normalized number. Its function is not affected by the
state of the UEN bit. The UF bit is cleared only by writing a
zero into it with the Load FSR instruction or by a hardware
reset.

Inexact Result Flag (IF): Bit 6. This bit is set by the FPU
whenever the result of an operation must be rounded to fit
within the destination format. The IF bit is set only if no other
error has occurred. It is cleared only by writing a zero into it
with the Load FSR instruction or by a hardware reset.

2.1.2.3 FSR Software Field (SWF)

Bits 9-15 of the FSR hold and display any information writ­ten to them (using the LFSR and SFSR instructions), but are
not otherwise used by FPU hardware. They are reserved for
use with NSC floating-point extension software.

2.2 INSTRUCTION SET

2.2.1 General Instruction Format

Figure 2-3

instruction. The Basic Instruction is one to three bytes long

shows the general format of an Series 32000

FIGURE 2-3. General Instruction Format

TL/EE/5234– 6

6