National Semiconductor NM27P512 Technical data
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NM27P512
524,288-Bit (64K x 8) Processor Oriented
CMOS EPROM
NM27P512 524,288-Bit (64K x 8) Processor Oriented CMOS EPROM
December 1993
General Description
The NM27P512 is a 512K Processor Oriented EPROM configured as 64k x 8. It’s designed to simplify microprocessor
interfacing while remaining compatible with standard
EPROMs. It can reduce both wait states and glue logic
when the specification improvements are taken advantage
of in the system design. The NM27P512 is implemented in
National’s advanced CMOS EPROM process to provide excellent reliability and access times as fast as 120 ns.
The interface improvements address two areas to eliminate
the need for additional devices to adapt the EPROM to the
microprocessor and to eliminate wait states at the termination of the access cycle. Even with these improvements, the
NM27P512 remains compatible with industry standard
JEDEC pinout EPROMs. The maximum specification for output turn-off time has been reduced, eliminating the need for
wait states at the end of a read cycle. Also, the minimum
specification for output hold time has been increased, eliminating the need for external circuitry to hold the data.
Block Diagram
Features
Y
Fast output turn off to eliminate wait states
Y
Extended data hold time for microprocessor
compatibility
Y
High performance CMOS
Ð 120 ns access time
Y
JEDEC standard pin configuration
Y
Manufacturer’s identification code
TL/D/11365– 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
NSC800
is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/D/11365
Connection Diagrams
27C080 27C040 27C020 27C010 27C256
A19XX/VPPXX/VPPXX/V
A16A16A16A
A15A15A15A15V
A12A12A12A12A
A7A7A7A7A
A6A6A6A6A
A5A5A5A5A
A4A4A4A4A
A3A3A3A3A
A2A2A2A2A
A1A1A1A1A
A0A0A0A0A
O0O0O0O0O
O1O1O1O1O
O2O2O2O2O
GND GND GND GND GND
PP
16
PP
12
7
6
5
4
3
2
1
0
0
1
2
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27P512 pins.
Commercial Temp Range (0§Ctoa70§C)
Parameter/Order Number Access Time (ns)*
NM27P512 Q, N, V 120 120
NM27P512 Q, N, V 150 150
NM27P512 Q, N, V 200 200
Military Temp Range (b55§Ctoa125§C)
Parameter/Order Number Access Time (ns)*
NM27P512 QM 200 200
DIP
NM27P512
27C256 27C010 27C020 27C040 27C080
TL/D/11365– 2
V
XX/PGM XX/PGM A
V
CC
A
A
A
A
CE/PGM CE CE CE/PGM CE/PGM
A
14
A
13
A
8
A
9
A
11
OE OE OE OE OE/
A
10
O
7
O
6
O
5
O
4
O
3
CC
XX A
14
13
A
8
A
9
11
10
O
7
O
6
O
5
O
4
O
3
V
A
A
A
A
V
CC
A
17
A
14
A
13
A
8
A
9
A
11
A
10
O
7
O
6
O
5
O
4
O
3
V
CC
18
17
14
13
A
A
11
10
O
O
O
O
O
CC
A
18
A
17
A
14
A
13
A
8
9
7
6
5
4
3
8
A
9
A
11
VPP
A
10
O
7
O
6
O
5
O
4
O
3
Extended Temp Range (b40§Ctoa85§C)
Parameter/Order Number Access Time (ns)*
NM27P512 QE, NE, VE 120 120
NM27P512 QE, NE, VE 150 150
NM27P512 QE, NE, VE 200 200
Note: Surface mount PLCC package available for commercial and extended
temperature ranges only.
*All versions are guaranteed to function for slower speeds.
Package Types: NM27P512 Q, N, V XXX
e
Q
Quartz-Windowed Ceramic DIP Package
e
N
Plastic OTP DIP Package
e
V
PLCC Package
All packages conform to the JEDEC standard.
#
Pin Names
A0–A15 Addresses
CE Chip Enable
OE Output Enable
O0–O7 Outputs
PGM Program
XX Don’t Care (During Read)
PLCC
TL/D/11365– 3
2
Absolute Maximum Ratings (Note 1)
V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
All Input Voltages Except A9 with
Respect to Ground
VPPand A9 with Respect to Ground
b
65§Ctoa150§C
b
0.6V toa7V
b
0.7V toa14V
Supply Voltage with
CC
Respect to Ground
ESD Protection
(MIL Std. 883, Method 3015.2)
All Output Voltages with
Respect to Ground V
b
a
1.0V to GNDb0.6V
CC
0.6V toa7V
l
2000V
Operating Range
Range Temperature V
Comm’l 0§Ctoa70§C
Industrial
Military
b
40§Ctoa85§C
b
55§Ctoa125§C
CC
a
5V
a
5V
a
5V
Tolerance
g
10%
g
10%
g
10%
Read Operation
DC Electrical Characteristics
Symbol Parameter Test Conditions Min Max Units
V
IL
V
IH
VOLOutput Low Voltage I
V
OH
(10)
I
SB1
I
SB2
ICCVCCActive Current CEeOEeVIL,f
I
PP
V
PP
I
LI
ILOOutput Leakage Current V
Input Low Level
Input High Level 2.0 V
e
2.1 mA 0.4 V
OL
Output High Voltage I
VCCStandby Current (CMOS) CEeV
VCCStandby Current CEeV
VPPSupply Current V
eb
2.5 mA 3.5 V
OH
g
0.3V 100 mA
CC
IH
e
I/O
e
0mA
e
V
PP
CC
5 MHz
VPPRead Voltage V
Input Load Current V
IN
OUT
e
5.5V or GND
e
5.5V or GND
b
0.5 08 V
a
1V
CC
1mA
40 mA
10 m A
b
0.7 V
CC
b
11mA
b
10 10 m A
CC
V
AC Electrical Characteristics
Symbol Parameter
t
ACC
t
CE
t
OE
t
DF
t
CF
t
OH
(2)
(2)
(2)
Address to Output Delay 120 150 200
CE to Output Delay 120 150 200
OE to Output Delay 50 50 50
Output Disable to Output Float 25 25 25
Chip Disable to Output Float 30 30 30
Output Hold from Addresses, CE
, Whichever Occurred First
or OE
120 150 200
Min Max Min Max Min Max
777
3
Units
ns
Capacitance T
ea
25§C, fe1 MHz (Note 2)
A
Symbol Parameter Conditions Typ Max Units
C
IN1
C
OUT
C
IN2
Input Capacitance V
except OE
/V
PP
Output Capacitance V
OE/VPPInput V
Capacitance
AC Test Conditions
Output Load 1 TTL Gate and
Input Rise and Fall Times
Input Pulse Levels 0.45V to 2.4V
e
C
100 pF (Note 8)
L
s
5ns
AC Waveforms (Notes 6, 7)
e
0V
IN
OUT
IN
e
e
0V
612pF
0V 9 12 pF
20 25 pF
Timing Measurement Reference Level (Note 9)
Inputs 0.8V and 2V
Outputs 0.8V and 2V
Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE
Note 4: The t
Note 5: TRI-STATE may be attained using OE
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on
every device between V
Note 7: The outputs must be restricted to V
Note 8: 1 TTL Gate: I
Note 9: Inputs and outputs can undershoot to
Note 10: CMOS inputs; V
may be delayed up to t
and tCFcompare level is determined as follows:
DF
High to TRI-STATE, the measured V
Low to TRI-STATE, the measured V
OL
: 100 pF includes fixture capacitance.
C
L
CC
e
IL
and GND.
1.6 mA, I
e
ACC–tOE
GNDg0.3V, V
after the falling edge of CE without impacting t
(DC)b0.10V;
OH1
(DC)a0.10V.
OL1
or CE.
a
1.0V to avoid latch-up and device damage.
CC
eb
400 mA.
OH
b
2.0V for 20 ns Max.
e
g
V
IH
0.3V.
CC
ACC
.
TL/D/11365– 4
4
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