National Semiconductor NM27P040 Technical data

NM27P040
4,194,304-Bit (512K x 8) Processor Oriented
CMOS EPROM

General Description

The NM27P040 is a 4096K Processor Oriented EPROM

TM

(POP

) configured as 512K x 8. It’s designed to simplify
microprocessor interfacing while remaining compatible with
standard EPROMs. It can reduce both wait states and glue
logic when the specification improvements are taken advan­tage of in the system design. The NM27P040 is implement­ed in National’s advanced CMOS EPROM process to pro­vide a reliable solution and access times as fast as 120 ns.

The interface improvements address two areas to eliminate
the need for additional devices to adapt the EPROM to the
microprocessor and to eliminate wait states at the termina­tion of the access cycle. Even with these improvements, the
NM27P040 remains compatible with industry standard
JEDEC pinout EPROMs. The time from CE or OE being
negated until the outputs are guaranteed to be in the high
impedance state has been reduced to eliminate the need
for wait states at the termination of the memory cycle and

the data-out hold time has been extended to eliminate the
need to provide data hold time for the microprocessor by
delaying control signals or latching and holding the data in
external latches.

Features

Y

Fast output turn off to eliminate wait states

Y

Extended data hold time for microprocessor
compatibility

Y

High performance CMOS
Ð 120 ns access time

Y

JEDEC standard pin configuration

Y

Manufacturer’s identification code

NM27P040 4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM

December 1993

Block Diagram

TL/D/11367– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

TM

POP

is a trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/D/11367

Connection Diagrams

27C080 27C020 27C010

A19 XX/V
A16 A16 A16
A15 A15 A15
A12 A12 A12

A7 A7 A7
A6 A6 A6
A5 A5 A5
A4 A4 A4
A3 A3 A3
A2 A2 A2
A1 A1 A1
A0 A0 A0
O

0

O

1

O

2

GND GND GND

O
O
O

Commercial Temperature Range (0§Ctoa70§C)

Parameter/Order Number Access Time (ns)

NM27P040 Q 120 120

NM27P040 Q 150 150

NM27P040 Q 170 170

XX/V

PP

0
1
2

V

CC

PP

O

0

O

1

O

2

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27P040 pin.

e

5Vg10%

DIP

NM27P040

27C010 27C020 27C080

V

CC

XX/PGM XX/PGM A18

XX A17 A17
A14 A14 A14
A13 A13 A13

A8 A8 A8

A9 A9 A9
A11 A11 A11

OE
A10 A10 A10

CE

O

7

O

6

O

5

O

4

O

3

TL/D/11367– 2

Extended Temperature Range (b40§Ctoa85§C)

e

V

5Vg10%

CC

V

CC

V

CC

OE OE/V

CE CE/PGM
O

7

O

6

O

5

O

4

O

3

O
O
O
O
O

Parameter/Order Number Access Time (ns)

NM27P040 QE 150 150

NM27P040 QE 170 170

PP

7
6
5
4
3

Military Temperature Range (b55§Ctoa125§C)

e

V

5Vg10%

CC

Parameter/Order Number Access Time (ns)

NM27P040 QM 150 150

NM27P040 QM 200 200

Pin Names

A0–A18 Addresses

CE/PGM Chip Enable/Program

OE Output Enable

O0–O7 Outputs

XX Don’t Care (During Read)

Package Types: NM27P040 QXXX

e

Q

Quartz-Windowed Ceramic DIP

All packages conform to the JEDEC standard.

#

All versions are guaranteed to function for slower

#

speeds.

2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Storage Temperature

All Input Voltages except A9 with

Respect to Ground (Note 10)

VPPand A9 with Respect to Ground

Supply Voltage with

V

CC

Respect to Ground

ESD Protection

All Output Voltages with

Respect to Ground (Note 10) V

b

65§Ctoa150§C

b

b

0.6V toa14V

b

a

1.0V to GNDb0.6V

CC

0.6V toa7V

0.6V toa7V

l

2000V

Read Operation

Operating Range

Range Temperature V

Commercial 0§Ctoa70§C
Industrial
Military

b

40§Ctoa85§C

b

55§Ctoa125§Cg5V

Tolerance

CC

a

g

5V
5V

g

g

g

10%
10%
10%

DC Electrical Characteristics

Over operating range with V

e

V

PP

CC

Symbol Parameter Test Conditions Min Max Units

V

IL

V

IH

VOLOutput Low Voltage I

V

OH

I

SB1

I

SB2

Input Low Level

Input High Level 2.0 V

e

2.1 mA 0.4 V

OL

Output High Voltage I

VCCStandby Current (CMOS) CEeV
(Note 11)

VCCStandby Current CEeV

eb

2.5 mA 3.5 V

OH

g

0.3V

CC

IH

ICCVCCActive Current CEeOEeVIL, I/Oe0mA

e

f

5 MHz

I

PP

V

PP

I

LI

VPPSupply Current V

VPPRead Voltage V

Input Load Current V

ILOOutput Leakage Current V

PP

IN

OUT

e

e

V

CC

5.5V or GND

e

5.5V or GND

AC Electrical Characteristics Over operating range with V

Symbol Parameter

t

ACC

t

CE

t

OE

t

DF

(Note 2) Output Float

t

CF

(Note 2) Output Float

t

OH

(Note 2) Whichever Occurred First

Address to Output Delay 120 150 170 250

CE to Output Delay 120 150 170 250

OE to Output Delay 50 50 50 50

Output Disable to 35

Chip Disable to 35

Output Hold from Addresses, CE or OE,

120 150 170 250

Min Max Min Max Min Max Min Max

7777

e

PP

b

0.2 0.8 V

a

1V

CC

100 mA

1mA

30 mA

10 m A

b

0.4 V

CC

b

11mA

b

10 10 mA

V

CC

CC

25 25 25

30 30 30

V

Units

ns

3