OCTAL TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
General Description
The ABT646 consists of bus tranceiver circuits wit TRI-STATE, D-type flip-flops, and
control circuitry arranged for multiplexed transmission of data directly from the input
bus or from the internal registers. Data on the A or B bus will be clocked into the
registers as the appropriate clock pin goes to a high logic level. Control OE and
direction pins are provided to control the transceiver function. In the transceiver mode,
data present at the high impedance port may be stored in either the A or the B register or
in both. The select controls can mutiplex stored and real-time (transparent mode) data.
The direction control determines which bus will receive data when the enable control OE is
Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B
register and/or B data may be stored in the A register.
1Static tests at +25
2Static tests at +125
3Static tests at -55
4Dynamic tests at +25
5Dynamic tests at +125
6Dynamic tests at -55
7Functional tests at +25
8AFunctional tests at +125
8BFunctional tests at -55
9Switching tests at +25
10Switching tests at +125
11Switching tests at -55
o
1
MN54ABT646-X REV 0B0
MICROCIRCUIT DATA SHEET
Features
- Independent registers for A and B buses.
- Multiplexed real-time and stored data.
- A and B output sink capability of 48 mA, source capability of 24 mA
- Guaranteed latchup protection
- High impedance glitch free bus loading during entire power up and power down cycle.
- Non-Destructive hot insertion capability.
- SMD : 5962-9457701Q3A*, QLA**, QKA***
2
MN54ABT646-X REV 0B0
(Absolute Maximum Ratings)
(Note 1)
Vcc Pin Potential to Ground Potential
Input Voltage
(Note 2)
Input Current
(Note 2)
Voltage Applied To Any Output
Current Applied To Output
Junction Temperature (Tj)
Thermal Resistance
Storage Temperature
Lead Temperature
ESD Classification
Maximum Power Dissipation
MICROCIRCUIT DATA SHEET
-0.5V to +7.0V
-0.5V to +7.0V
-30mA to +5.0mA
-0.5V to 5.5VIn the Disabled or Power-Off State
-0.5V to VccIn The High State
96mAIn The Low State (Max)
+175CCeramic
See Mil-Std 1835Junction-To-Case (Theta JC)
-65C to +150C
+300C(Soldering, 10 seconds)
Class 3
500 mW
Note 1:Absolute maximum ratings are values beyond which the device may be damaged or have
Note 2:Either voltage limit or current limit is sufficient to protect inputs.
its useful life impaired. Functional operation under these conditions is not
implied.
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC:CL=50pF RL=500 OHMS TRISE/TFALL = 3.0nS
SYMBOLPARAMETERCONDITIONSNOTES
ts (H/L)Setup Time HIGH
or LOW
th (H/L)Hold Time HIGH or
LOW
tw (L)Pulse WidthVCC=5.0V @25C, VCC=4.5V & 5.5V
FmaxMax Clock
Frequency
Note 1:Screen tested 100% on each device at -55C, +25C & +125C Temp., Subgroups 1,2,3,7 & 8.
Note 2:Screen tested 100% on each device at -55C, +25C, and +125C temp., subgroups A9, A10,
and A11.
Note 3:Screen tested 100% on each device at +25C temp. only, subgroup A9.
Note 4:Sample tested (Method 5005, Table 1) on each mfg. lot at +25C, +125C, & -55C temp.
subgroups A1, 2, 3, 7 & 8.
Note 5:Sample tested (Method 5005, Table 1) on each mfg. Lot at +25C, +125C & -55C temp.,
subgroups A9, 10 & 11.
Note 6:Sample tested (Method 5005, Table 1) on each mfg. Lot at 25C temp only, subgroup A9.
Note 7:Not tested (Guaranteed by Design Characterization Data).
Note 8:Max number of outputs defines as (N). N-1 data inputs are driven 0V to 3V. one
output @Vol or @Voh.
Note 9:Max number of data inputs (N) switching. (N-1) inputs switching 0V to 3V.
Input-under-test switching : 3V to threshold (Vild), 0V to threshold (Vihd), Freq= 1
MHZ
Note 10: Maximum test duration not to exceed one second, not more than one output shorted at
one time.
VCC=5.0V @25C, VCC=4.5V & 5.5V
@-55C/125C
VCC=5.0V @25C, VCC=4.5V & 5.5V
@-55C/125C
@-55C/125C
VCC=5.0V @25C, VCC=4.5V & 5.5V
@-55C/125C
PINNAME
7BUS to
Clock
7BUS to
Clock
7BUS to
Clock
7BUS to
Clock
7CPAB/CPBA4.0ns9, 10,
7CPAB/CP
BA
MINMAXUNIT
3.0ns9
3.5ns10, 11
1.0ns9
1.0ns10, 11
125MHz9, 10,
SUB-
GROUPS
11
11
7
MN54ABT646-X REV 0B0
Graphics and Diagrams
GRAPHICS#DESCRIPTION
E28ARDLCC (E), TYPE C, 28 TERMINAL(P/P DWG)
J24FRGCERDIP (J), 24LD, .300 CENTERS (P/P DWG)
W24CRECERPACK (W), 24 LEAD (P/P DWG)
See attached graphics following this page.
MICROCIRCUIT DATA SHEET
8
MN54ABT646-X REV 0B0
MICROCIRCUIT DATA SHEET
Revision History
RevECN #Rel DateOriginatorChanges
0B0M0002947 10/05/98Bill PetcherChanged MDS MN54ABT646-X REV 0A0 to MN54ABT646-X REV
0B0
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