National Semiconductor MM54HC540, MM74HC540, MM54HC541, MM74HC541 Service Manual
MM54HC540/MM74HC540
Inverting Octal TRI-STATE
É
MM54HC541/MM74HC541
Octal TRI-STATE Buffer
General Description
These TRI-STATE buffers utilize advanced silicon-gate
CMOS technology. They possess high drive current outputs
which enable high speed operation even when driving large
bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the advantage of CMOS circuitry, i.e., high noise immunity, and
low power consumption. Both devices have a fanout of 15
LS-TTL equivalent inputs.
The MM54HC540/MM74HC540 is an inverting buffer and
the MM54HC541/MM74HC541 is a non-inverting buffer.
The TRI-STATE control gate operates as a two-input NOR
such that if either G1
the high-impedance state.
or G2 are high, all eight outputs are in
February 1988
Buffer
In order to enhance PC board layout, the ’HC540 and
’HC541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to V
Features
Y
Typical propagation delay: 12 ns
Y
TRI-STATE outputs for connection to system buses
Y
Wide power supply range: 2 –6V
Y
Low quiescent current: 80 mA maximum (74HC Series)
Y
Output current: 6 mA
and ground.
CC
MM54HC540/MM74HC540 Inverting Octal TRI-STATE Buffer
MM54HC541/MM74HC541 Octal TRI-STATE Buffer
Connection Diagrams
Dual-In-Line Package
TL/F/5341– 1
Top View
Order Number MM54HC540 or MM74HC540
TL/F/5341– 2
Top View
Order Number MM54HC541 or MM74HC541
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5341
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (ICD)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
35 mA
70 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (T
) (Soldering 10 seconds) 260§C
L
DC Electrical Characteristics (Note 4)
e
T
25§C
Symbol Parameter Conditions V
CC
A
Typ Guaranteed Limits
V
Minimum High Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level V
OH
Output Voltage
e
VIHor V
l
IN
I
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
IN
I
OUT
e
V
Maximum Low Level V
OL
Output Voltage
IL
s
6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
OZ
Maximum Input V
Current
Maximum TRI-STATE V
Output Leakage V
Current
I
CC
Maximum Quiescent V
Supply Current I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
g
and VILoccur at V
IH
e
IN
e
IN
OUT
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
VIHor VIL,GeVIH6.0V
e
VCCor GND
g
0.1
g
0.5
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
g
5
Min Max Units
V
§
§
Units
b
b
40
55
A
eb
CC
a
85
a
125
55 to 125§C
g
1.0 mA
g
10 mA
C
C
2
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