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MM74HC356

National Semiconductor MM54HC354, MM54HC356, MM74HC354, MM74HC356 Service Manual

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MM54HC354/MM74HC354/ MM54HC356/MM74HC356 8-Channel TRI-STATE
General Description
The MM54HC354/MM74HC354 and MM54HC356/ MM74HC356 utilize advanced silicon-gate CMOS technolo­gy. They exhibit the high noise immunity and low power dis­sipation of standard CMOS integrated circuits, along with the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the TRI-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus orga­nized system.
These data selectors/multiplexers contain full on-chip bina­ry decoding to select one of eight data sources. The data select address is stored in transparent latches that are en­abled by a low level address on pin 11, SC input lines is stored in a parallel input/output register which in the MM54HC354/MM74HC354 is composed of 8 trans­parent latches enabled by a low level on pin 9, DC the MM54HC356/MM74HC356 is composed of 8 edge-trig­gered flip-flops, clocked by a low to high transition on pin 9, CLK. Both true (Y) and complementary (W) TRI-STATE out­puts are available on both devices.
É
. Data on the 8
, and in
June 1992
The 54HC/74HC logic family is functionally as well as pin­out compatible with the standard 54LS/74LS-TTL logic fam­ily. All inputs are protected from damage due to static dis­charge by internal diode clamps to V
and ground.
CC
Features
Y
Transparent latches on data select inputs
Y
Choice of data registers:
Transparent (’354) Edge-triggered (’356)
Y
TRI-STATE complementary outputs with fanout of 15 LS-TTL loads
Y
Typical propagation delay:
Data to output (’354): 32 ns Clock to output (’346): 35 ns
Y
Wide power supply range: 2V –6V
Y
Low quiescent supply current: 80 mA maximum
Y
Low input current: 1 mA maximum
MM54HC354/MM74HC354/MM54HC356/MM74HC356
8-Channel TRI-STATE Multiplexers with Latches
Connection Diagram
Dual-In-Line Package
Top View
Order Number MM54HC354/356 or MM74HC354/356
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5208
TL/F/5208– 1
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (ICD)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5V toa7.0V
1.5V to V
CC
0.5V to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
35 mA
70 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW S.O. Package only 500 mW
Lead Temp. (T
)
L
(Soldering 10 seconds) 260§C
DC Electrical Characteristics (Note 4)
e
T
25§C
Symbol Parameter Conditions V
CC
A
Typ Guaranteed Limits
V
Minimum High Level Input 2.0V 1.5 1.5 1.5 V
IH
Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level Input 2.0V 0.5 0.5 0.5 V
IL
Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level Output V
OH
Voltage
e
VIHor V
l
I
OUT
IN
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
OUT
e
IN
V
Maximum Low Level Output V
OL
Voltage
IL
s
6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
k
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
OZ
I
CC
Maximum Input Current V
Maximum TRI-STATE Output V Leakage Current G
Maximum Quiescent Supply V Current I
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
g
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
and VILoccur at V
IH
IN
OUT
1eV
IN
OUT
CC
e
e
e
IL
s
6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
e
VCCor GND
IH
6.0V
g
0.1
g
0.5
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
g
5.0
Min Max Units
CC
b b
40 55
eb
A
a
85
a
125
55 to 125§C
g
1.0 mA
g
10 mA
V
§
§
Units
C C
2
AC Electrical Characteristics V
CC
5V, T
e
A
25§C, t
e
e
t
6ns
r
f
e
MM54HC354/MM74HC354
Symbol Parameter Conditions Typ
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PZH,tPZL
t
PHZ,tPLZ
t
S
t
H
t
W
Maximum Propagation C Delay D0–D7 to either Output
Maximum Propagation C Delay DC
to either Output
Maximum Propagation C Delay S0–S2 to either Output
Maximum Propagation C Delay SC
to either Output
Maximum Output Enable Time R
Maximum Output Disable Time R
Minimum Setup Time 3 10 ns D0–D7toDC
,S0–S2toSC
Minimum Hold Time 0 5 ns D0–D7toDC
,S0–S2toSC
Minimum Pulse Width, SC or DC 10 15 ns
e
45 pF 32 46 ns
L
e
45 pF 38 53 ns
L
e
45 pF 40 56 ns
L
e
45 pF 42 58 ns
L
e
1kX 17 24 ns
L
e
C
45 pF
L
e
1kX 23 32 ns
L
e
C
5pF
L
MM54HC356/MM74HC356
Symbol Parameter Conditions Typ
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PZH,tPZL
t
PHZ,tPLZ
t
S
t
H
t
W
Maximum Propagation C Delay CLK to either Output
Maximum Propagation C Delay S0–S2 to either Output
Maximum Propagation C Delay SC
to either Output
Maximum Output Enable Time R
Maximum Output Disable Time R
Minimum Setup Time 3 10 ns D0–D7 to CLK, S0–S2 to SC
Minimum Hold Time 0 5 ns D0–D7 to CLK, S0–S2 to SC
Minimum Pulse Width, SC or CLK 10 15 ns
e
45 pF 35 50 ns
L
e
45 pF 40 56 ns
L
e
45 pF 42 58 ns
L
e
1kX 17 24 ns
L
e
C
45 pF
L
e
1kX 23 32 ns
L
e
C
5pF
L
Guaranteed
Limit
Guaranteed
Limit
Units
Units
3
AC Electrical Characteristics MM54HC354/MM74HC354 (Continued)
e
V
2.0–6.0V, C
CC
Symbol Parameter Conditions V
e
L
50 pF, t
e
e
t
6 ns (unless otherwise specified)
r
f
CC
e
T
25§C
A
T
A
Typ Guaranteed Limits
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PZH,tPZL
t
PHZ,tPLZ
t
S
t
H
t
W
t
TLH,tTHL
C
PD
C
IN
C
OUT
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Propagation C Delay D0–D7 to either Output C
Maximum Propagation C Delay DC
Maximum Propagation C Delay S0–S2 to either Output C
Maximum Propagation C Delay SC to either Output C
to either Output C
Maximum Output Enable Time R
Maximum Output Disable Time R
Minimum Setup Time 2.0V 6 50 60 75 ns D0–D7toDC
Minimum Hold Time 2.0V 0 5 5 5 ns D0–D7toDC,S0–S2toSC 4.5V 0 5 5 5 ns
Minimum Pulse Width 2.0V 30 80 100 120 ns
or DC 4.5V 10 16 20 24 ns
SC
Maximum Output Rise C and Fall Time 4.5V 7 12 15 18 ns
Power Dissipation Capacitance (per package) (Note 5) Active 150 pF
,S0–S2toSC 4.5V 3 10 13 15 ns
Maximum Input Capacitance 5 10 10 10 pF
Maximum Output Capacitance 15 20 20 20 pF
e
50 pF 2.0V 90 235 294 352 ns
L
e
150 pF 2.0V 100 275 344 412 ns
L
e
C
50 pF 4.5V 35 47 59 70 ns
L
e
150 pF 4.5V 40 55 68 83 ns
C
L
e
C
50 pF 6.0V 26 40 50 60 ns
L
e
150 pF 6.0V 32 46 58 69 ns
C
L
e
50 pF 2.0V 115 270 337 405 ns
L
e
150 pF 2.0V 125 310 387 465 ns
L
e
C
50 pF 4.5V 40 54 68 82 ns
L
e
150 pF 4.5V 46 62 78 93 ns
C
L
e
C
50 pF 6.0V 32 46 58 69 ns
L
e
150 pF 6.0V 38 52 66 78 ns
C
L
e
50 pF 2.0V 120 285 356 427 ns
L
e
150 pF 2.0V 130 325 406 488 ns
L
e
C
50 pF 4.5V 42 57 71 86 ns
L
e
C
150 pF 4.5V 50 65 81 97 ns
L
e
C
50 pF 6.0V 34 48 60 72 ns
L
e
150 pF 6.0V 40 55 69 82 ns
C
L
e
50 pF 2.0V 120 300 375 450 ns
L
e
150 pF 2.0V 110 340 425 510 ns
L
e
C
50 pF 4.5V 45 60 75 90 ns
L
e
C
150 pF 4.5V 52 68 85 102 ns
L
e
C
50 pF 6.0V 36 51 64 77 ns
L
e
150 pF 6.0V 42 58 72 87 ns
C
L
e
1kX
L
e
50 pF 2.0V 50 125 156 188 ns
C
L
e
150 pF 2.0V 60 165 206 248 ns
C
L
e
C
50 pF 4.5V 18 25 31 38 ns
L
e
150 pF 4.5V 25 33 41 49 ns
C
L
e
C
50 pF 6.0V 15 21 26 32 ns
L
e
C
150 pF 6.0V 21 28 35 42 ns
L
e
1kX 2.0V 68 165 206 248 ns
L
e
50 pF 4.5V 24 33 41 49 ns
C
L
6.0V 20 28 35 42 ns
6.0V 3 10 13 15 ns
6.0V 0 5 5 5 ns
6.0V 10 15 18 20 ns
e
50 pF 2.0V 25 60 75 90 ns
L
6.0V 6 10 13 15 ns
TRI-STATE 50 pF
2
e
CPDV
D
faICCVCC, and the no load dynamic current consumption, I
CC
74HC 54HC
eb
40 to 85§CT
A
eb
55 to 125§C
e
CPDVCCfaICC.
S
Units
4
AC Electrical Characteristics MM54HC356/MM74HC356 (Continued)
e
V
2.0–6.0V, C
CC
Symbol Parameter Conditions V
e
L
50 pF, t
e
e
t
6 ns (unless otherwise specified)
r
f
CC
e
T
25§C
A
Typ Guaranteed Limits
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PZH,tPZL
t
PHZ,tPLZ
t
S
Maximum Propagation C Delay CLK to either Output C
Maximum Propagation C Delay S0–S2 to either Output C
Maximum Propagation C Delay SC
to either Output C
Maximum Output Enable Time R
Maximum Output Disable Time R
Minimum Setup Time 2.0V 6 50 60 75 ns D0–D7 to CLK, S0–S2 to SC
e
50 pF 2.0V 100 225 318 338 ns
L
e
150 pF 2.0V 110 295 369 442 ns
L
e
C
50 pF 4.5V 36 51 63 76 ns
L
e
C
150 pF 4.5V 42 59 73 90 ns
L
e
C
50 pF 6.0V 28 43 53 64 ns
L
e
C
150 pF 6.0V 34 50 63 75 ns
L
e
50 pF 2.0V 120 285 356 427 ns
L
e
150 pF 2.0V 130 325 406 488 ns
L
e
C
50 pF 4.5V 42 57 71 86 ns
L
e
C
150 pF 4.5V 50 65 81 97 ns
L
e
C
50 pF 6.0V 34 48 60 72 ns
L
e
C
150 pF 6.0V 40 55 69 82 ns
L
e
50 pF 2.0V 120 300 375 450 ns
L
e
150 pF 2.0V 110 340 425 510 ns
L
e
C
50 pF 4.5V 45 60 75 90 ns
L
e
C
150 pF 4.5V 52 68 85 102 ns
L
e
C
50 pF 6.0V 36 51 64 77 ns
L
e
C
150 pF 6.0V 42 58 72 87 ns
L
e
1kX
L
e
C
50 pF 2.0V 50 125 156 188 ns
L
e
C
150 pF 2.0V 60 165 206 248 ns
L
e
C
50 pF 4.5V 18 25 31 38 ns
L
e
C
150 pF 4.5V 25 33 41 49 ns
L
e
C
50 pF 6.0V 15 21 26 32 ns
L
e
C
150 pF 6.0V 21 28 35 42 ns
L
e
1kX 2.0V 68 165 206 248 ns
L
e
C
50 pF 4.5V 24 33 41 49 ns
L
6.0V 20 28 35 42 ns
4.5V 3 10 13 15 ns
6.0V 3 10 13 15 ns
t
H
Minimum Hold Time 2.0V 0 5 5 5 ns D0–D7 to CLK, S0–S2 to SC 4.5V 0 5 5 5 ns
6.0V 0 5 5 5 ns
t
W
Minimum Pulse Width 2.0V 30 80 100 120 ns SC to CLK 4.5V 10 16 20 24 ns
6.0V 10 15 18 20 ns
tr,t
Maximum Clock Input 2.0V 1000 1000 1000 ns
f
Rise and Fall Time 4.5V 500 500 500 ns
6.0V 400 400 400 ns
t
TLH,tTHL
Maximum Output Rise C and Fall Time 4.5V 7 12 15 18 ns
e
50 pF 2.0V 25 60 75 90 ns
L
6.0V 6 10 13 15 ns
C
PD
Power Dissipation Capacitance (per package) (Note 5) Active 150 pF
TRI-STATE 50 pF
C
IN
C
OUT
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Input Capacitance 5 10 10 10 pF
Maximum Output Capacitance 15 20 20 20 pF
2
e
CPDV
D
faICCVCC, and the no load dynamic current consumption, I
CC
74HC 54HC
eb
T
40 to 85§CT
A
A
eb
55 to 125§C
e
CPDVCCfaICC.
S
Units
5
Function Table
Inputs
²
Select
S1 S2 S0 DC CLK G1G2G3 W Y
XXX X X HX X Z Z XXX X X XHX Z Z XXX X X X X L Z Z LLL L L L L H HorL L L H D LLH L L L H H HorL L L H D LHL L L H L H HorL L L H D2nD2 LHH L L H H H HorL L L H D3nD3 HLL L H L L H HorL L L H D HLH L H L H H HorL L L H D HHL L H H L H HorL L L H D6nD6 HHH L H H H H HorL L L H D
Hehigh level (steady state)
e
L
low level (steady state)
e
X
irrelevant (any input, including transitions)
e
Z
high-impedance state (off state)
e
transition from low to high level
u
e
D0...D7 high clock transition in the case of ’HC356
D0 recent low-to-high transition of data control or clock.
²
the level steady-state inputs at inputs D0 through D7, respectively, at the time of the low-to-
e
...D7
n
This column shows the input address set-up with SC low.
the level of steady state inputs at inputs D0 through D7, respectively, before the most
n
Data
Control Clock Output Outputs
’HC354 ’HC356 Enables
u
LLHD0D0
0nD0
u
LLHD1D1
1nD1
u
u
u
LLHD2D2
LLHD3D3
LLHD4D4
4nD4
u
LLHD5D5
5nD5
u
u
LLHD6D6
LLHD7D7
7nD7
n
n
n
n
n
n
n
n
6
Logic Diagram
HC354
Ê
TL/F/5208– 2
7
Logic Diagram
HC356
Ê
TL/F/5208– 3
8
9
Physical Dimensions inches (millimeters)
Order Number MM54HC354J, MM54HC356J, MM74HC354J or MM74HC356J
Ceramic Dual-In-Line Package (J)
NS Package Number J20A
8-Channel TRI-STATE Multiplexers with Latches
MM54HC354/MM74HC354/MM54HC356/MM74HC356
Molded Dual-In-Line Package (N)
Order Number MM74HC354N or MM74HC356N
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user.
NS Package Number N20A
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1111 West Bardin Road Fax: ( Arlington, TX 76017 Email: cnjwge@tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fran3ais Tel: ( Italiano Tel: (
a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
a
49) 0-180-530 85 85 Tsimshatsui, Kowloon
a
49) 0-180-532 78 32 Hong Kong
a
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a
49) 0-180-534 16 80 Fax: (852) 2736-9960
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