National Semiconductor MM54C941, MM74C941 Technical data
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MM54C941/MM74C941 Octal Buffers/Line Receivers/
Line Drivers with TRI-STATE
Outputs
É
MM54C941/MM74C941 Octal Buffers/Line Receivers/Line Drivers with TRI-STATE Outputs
February 1988
General Description
These octal buffers and line drivers are monolithic complementary MOS (CMOS) integrated circuits with TRI-STATE
outputs. These outputs have been specially designed to
drive highly capacitive loads such as bus-oriented systems.
These devices have a fan-out of 6 low power Schottky
loads. When V
and low logic levels.
e
5V, inputs can accept true TTL high
CC
Connection and Logic Diagrams
Dual-In-Line Package
Features
Y
Wide supply voltage range (3V to 15V)
Y
Low power consumption
Y
TTL compatibility (Improved on the inputs)
Y
High capacitive load
Y
TRI-STATE outputs
Y
Input protection
Y
20-pin dual-in-line package
Y
High output drive
Top View
Order Number MM54C941 or MM74C941
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5923
TL/F/5923– 1
TL/F/5923– 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin 0.3V to V
Operating Temperature Range (TA)
MM54C941
MM74C941
b
b
a
0.3V
CC
55§Ctoa125§C
40§Ctoa85§C
Storage Temperature Range (T
)
S
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Operating V
V
CC
Range 3V to 15V
CC
Lead Temperature (TL)
65§Ctoa150§C
b
(Soldering, 10 seconds) 260
DC Electrical Characteristics Min/Max limits apply across temperature range, unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
I
OZ
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
Supply Current V
TRI-STATE Leakage V
CMOS/TTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage 54C, V
Logical ‘‘0’’ Input Voltage 54C, V
Logical ‘‘1’’ Output Voltage 54C, V
Logical ‘‘0’’ Output Voltage 54C, V
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Output Source Current V
(P-Channel) T
Output Source Current V
(P-Channel) T
Output Sink Current V
(N-Channel) T
Output Sink Current V
(N-Channel) T
e
5.0V 2.5 V
CC
e
V
10V 8.0 V
CC
e
5.0V 0.8 V
CC
e
V
10V 2.0 V
CC
CC
V
CC
CC
V
CC
CC
CC
CC
CC
74C, V
74C, V
74C, V
54C, V
74C, V
74C, V
CC
e
A
CC
e
A
CC
e
A
CC
e
A
e
e
e
e
e
e
e
e
e
25§C
e
25§C
e
25§C
e
25§C
eb
5.0V, I
10V, I
5.0V, I
10V, I
15V, V
15V, V
10mA 4.5 V
O
eb
10mA 9.0 V
O
e
10 mA 0.5 V
O
e
10 mA 1.0 V
O
e
15V 0.005 1.0 mA
IN
e
0V
IN
b
1.0
b
0.005 mA
15V 0.05 300 mA
15V, V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
5.0V, V
10V, V
5.0V, V
10V, V
e
0V or 15V
OUT
e
4.5V V
e
4.75V V
e
4.5V 0.8 V
e
4.75V 0.8 V
e
e
e
e
e
e
4.5V, I
4.75V, I
4.5V, I
4.75V, I
4.5V, I
4.75V, I
OUT
OUT
OUT
OUT
eb
450 mAV
O
eb
450 mAV
O
eb
2.2 mA 2.4 V
O
eb
2.2 mA 2.4 V
O
e
2.2 mA 0.4 V
O
e
2.2 mA 0.4 V
O
e
0V
e
0V
e
V
CC
e
V
CC
b
2.5 V
CC
b
2.5 V
CC
b
0.4 V
CC
b
0.4 V
CC
b
14.0
b
36.0
b
30.0 mA
b
70.0 mA
12.0 20.0 mA
48.0 70 mA
g
10 mA
18V
C
§
2
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