National Semiconductor MF10 Technical data
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MF10
Universal Monolithic Dual
Switched Capacitor Filter
General Description
The MF10 consists of 2 independent and extremely easy to
use, general purpose CMOS active filter building blocks.
Each block, together with an external clock and 3 to 4 resistors, can produce various 2nd order functions. Each building
block has 3 output pins. One of the outputs can be configured to perform either an allpass, highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and
bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both
clock frequency and external resistor ratios. The center frequency of the notch and allpass functions is directly dependent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th
order functions can be performed by cascading the two 2nd
order building blocks of the MF10; higher than 4th order
functions can be obtained by cascading MF10 packages.
December 1994
Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and Chebyshev) can be formed.
For pin-compatible device with improved performance refer
to LMF100 datasheet.
Features
Y
Easy to use
Y
Clock to center frequency ratio accuracyg0.6%
Y
Filter cutoff frequency stability directly dependent on
external clock quality
Y
Low sensitivity to external component variation
Y
Separate highpass (or notch or allpass), bandpass, lowpass outputs
Y
c
f
Q range up to 200 kHz
O
Y
Operation up to 30 kHz
Y
20-pin 0.3×wide Dual-In-Line package
Y
20-pin Surface Mount (SO) wide-body package
MF10 Universal Monolithic Dual Switched Capacitor Filter
System Block Diagram
TL/H/10399– 1
Connection Diagram
Surface Mount and Dual-In-Line
Package
TL/H/10399– 4
Top View
Order Number MF10AJ or MF10CCJ
See NS Package Number J20A
Order Number MF10ACWM or
MF10CCWM
See NS Package Number M20B
Order Number MF10ACN or
MF10CCN
See NS Package Number N20A
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/H/10399
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
a
Supply Voltage (V
Voltage at Any Pin V
b
Vb) 14V
a
b
V
a
0.3V
b
0.3V
Input Current at Any Pin (Note 2) 5 mA
Package Input Current (Note 2) 20 mA
Power Dissipation (Note 3) 500 mW
Storage Temperature 150
§
ESD Susceptability (Note 11) 2000V
a
Electrical Characteristics V
apply for T
MIN
to T
MAX
; all other limits T
ea
5.00V and V
e
e
T
A
25§C.
J
Symbol Parameter Conditions
a
b
V
VbSupply Voltage Min 99V
Max 14 14 V
I
S
f
O
f
CLK
f
CLK/fO
f
CLK/fO
H
V
V
V
V
V
Maximum Supply Clock Applied to Pins 10 & 11
Current No Input Signal
Center Frequency Min f
Range
Clock Frequency Min 5.0 10 5.0 10 Hz
Range
50:1 Clock to MF10A Qe10 V
Center Frequency
Ratio Deviation
100:1 Clock to MF10A Qe10 V
Center Frequency
Ratio Deviation
Max 30 20 30 20 kHz
Max 1.5 1.0 1.5 1.0 MHz
MF10C
MF10C
Clock Feedthrough Qe10
Q Error (MAX) Qe10 V
(Note 4) Mode 1 f
DC Lowpass Gain Mode 1 R1eR2e10k 0
OLP
DC Offset Voltage (Note 5)
OS1
DC Offset Voltage Min V
OS2
(Note 5)
Max
Min V
Max
DC Offset Voltage Min V
OS3
(Note 5)
DC Offset Voltage V
OS2
(Note 5) (f
Max
(Note 5) (f
DC Offset Voltage V
OS3
(Note 5) (f
c
Qk200 kHz 0.1 0.2 0.1 0.2 Hz
O
pin12
Mode 1 f
Mode 1 f
CLK
pin12
CLK
e
e
Mode 1
pin12
e
CLK
V
pin12
e
f
CLK
pin12
(f
CLK/fO
pin12
(f
CLK/fO
pin12
(f
CLK/fO
pin12
CLK/fO
V
pin12
CLK/fO
pin12
CLK/fO
ea
5V S
e
50)
ea
5V S
e
50)
ea
5V All Modes
e
50)
e
0V S
e
100)
e
0V S
e
100)
e
0V All Modes
e
100)
A/B
A/B
A/B
A/B
e
e
e
e
Soldering Information
N Package: 10 sec. 260
J Package: 10 sec. 300
SO Package: Vapor Phase (60 Sec.) 215
Infrared (15 Sec.) 220
See AN-450 ‘‘Surface Mounting Methods and Their Effect
on Product Reliability’’ (Appendix D) for other methods of
soldering surface mount devices.
Operating Ratings (Note 1)
C
Temperature Range T
MF10ACN, MF10CCN 0§CsT
MF10CCWM, MF10ACWM 0§CsT
e
5V
250 kHz
e
0V
500 kHz
e
5V
250 kHz
e
0V
500 kHz
a
V
b
V
a
V
b
V
2
MF10CCJ
MF10AJ
b
eb
5.00V unless otherwise specified. Boldface limits
MF10ACN, MF10CCN,
MF10ACWM, MF10CCWM
Tested Design
Typical
(Note 8)
Limit Limit
(Note 9) (Note 10) (Note 9) (Note 10)
81212 8 12 mA
g
0.2g0.6g0.6g0.2g1.0 %
g
0.2g1.5g1.5g0.2g1.5 %
g
0.2g0.6g0.6g0.2g1.0 %
g
0.2g1.5g1.5g0.2g1.5 %
10 10 mV
g
g
2
g
2
g
g
5.0g20
b
150b185b185b150b185
b
b
70
b70b
b
b
300
b
140
b
140
g
6
6
g
g
6
6
0.2g0.2 0
g
20g5.0g20 mV
b
85
85
100b100b70b100
b
20
20
b
MF10CCJ, MF10AJ
Tested Design Units
Typical
(Note 8)
g2g
g2g
b
70 mV
b
300 mV
b
140 mV
b
140 mV
s
s
T
MIN
A
s
A
s
A
b
40§CsT
55§CsT
s
A
s
125§C
A
Limit Limit
10 %
10 %
g
0.2 dB
b
85
b
20
T
MAX
70§C
70§C
85§C
C
§
C
§
C
§
C
§
mV
mV
Electrical Characteristics (Continued) V
Boldface limits apply for T
MIN
to T
MAX
; all other limits T
a
Symbol Parameter Conditions
V
Minimum Output BP, LP Pins R
OUT
Voltage Swing
N/AP/HP Pin R
e
5k
L
e
3.5k
L
ea
e
A
5.00V and V
T
J
Typical
(Note 8)
b
eb
e
25§C.
MF10ACN, MF10CCN,
MF10ACWM, MF10CCWM
g
4.25g3.8
g
4.25g3.8
5.00V unless otherwise specified.
MF10CCJ, MF10AJ
Tested Design
Limit Limit
(Note 9) (Note 10) (Note 9) (Note 10)
Typical
(Note 8)
g
3.8g4.25g3.8 V
g
3.8g4.25g3.6 V
Tested Design Units
Limit Limit
GBW Op Amp Gain BW Product 2.5 2.5 MHz
SR Op Amp Slew Rate 7 7 V/ms
Dynamic Range V
(Note 6) (f
I
Maximum Output Short Source 20 20 mA
SC
Circuit Current (Note 7)
Sink 3.0 3.0 mA
Logic Input Characteristics Boldface limits apply for T
Parameter Conditions
a
CMOS Clock Min Logical ‘‘1’’ V
Input Voltage
Max Logical ‘‘0’’
Min Logical ‘‘1’’ V
Max Logical ‘‘0’’
TTL Clock Min Logical ‘‘1’’ V
Input Voltage
Max Logical ‘‘0’’
Min Logical ‘‘1’’ V
Max Logical ‘‘0’’
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
device, T
number increases to 95
Note 4: The accuracy of the Q value is a function of the center frequency (f
Characteristics’’.
Note 5: V
Note 6: For
the MF10 with a 50:1 CLK ratio and 280 mV rms for the MF10 with a 100:1 CLK ratio.
Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8: Typicals are at 25
Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 11: Human body model, 100 pF discharged through a 1.5 kX resistor.
e
125§C, and the typical junction-to-ambient thermal resistance of the MF10ACN/CCN when board mounted is 55§C/W. For the MF10AJ/CCJ, this
JMAX
OS1,VOS2
C/W and for the MF10ACWM/CCWM this number is 66§C/W.
§
, and V
refer to the internal offsets as discussed in the Applications Information Section 3.4.
g
5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 mV rms for
OS3
C and represent most likely parametric norm.
§
ea
5V, V
e
V
0V
LSh
a
ea
10V, V
ea
V
LSh
a
ea
5V, V
e
V
0V
LSh
a
ea
10V, V
V
LSh
) at any pin exceeds the power supply rails (V
IN
ea
pin12
CLK/fO
V
pin12
(f
CLK/fO
b
5V
b
e
(T
D
5V
e
50)
e
0V
e
100)
Typical
(Note 8)
eb
5V,
b
e
0V,
eb
5V,
b
e
0V,
b
TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this
JMAX
83 83 dB
80 80 dB
to T
MIN
; all other limits T
MAX
MF10ACN, MF10CCN,
MF10ACWM, MF10CCWM
Tested Design
Limit Limit
(Note 9) (Note 10) (Note 9) (Note 10)
a
b
a
a
a
a
a
a
k
Vbor V
IN
). This is illustrated in the curves under the heading ‘‘Typical Performance
O
a
3.0
b
3.0
a
8.0
a
2.0
a
2.0
a
0.8
a
2.0
a
0.8
l
Va) the absolute value of current at that pin should be limited
IN
JMAX
Typical
(Note 8)
3.0
3.0
8.0
2.0
2.0
0.8
2.0
0.8
, iJA, and the ambient temperature, TA. The maximum
e
T
A
J
MF10CCJ, MF10AJ
Tested Design Units
Limit Limit
a
3.0 V
b
3.0 V
a
8.0 V
a
2.0 V
a
2.0 V
a
0.8 V
a
2.0 V
a
0.8 V
e
25§C
3
Typical Performance Characteristics
Power Supply Current
vs Power Supply Voltage
Negative Output
Swing vs Temperature
Q Deviation vs
Temperature
Positive Output Voltage Swing
vs Load Resistance
(N/AP/HP Output)
Positive Output Swing
vs Temperature
Q Deviation vs
Temperature
Negative Output Voltage
Swing vs Load
Resistance (N/AP/HP Output)
Crosstalk vs Clock
Frequency
Q Deviation vs
Clock Frequency
Q Deviation vs
Clock Frequency
Deviation
f
CLK/fO
vs Temperature
4
f
Deviation
CLK/fO
vs Temperature
TL/H/10399– 2
Typical Performance Characteristics (Continued)
Deviation
f
CLK/fO
vs Clock Frequency
f
Deviation
CLK/fO
vs Clock Frequency
f
Deviation of
vs Nominal Q
CLK
f
O
Deviation of
vs Nominal Q
f
CLK
f
O
TL/H/10399– 3
Pin Descriptions
LP(1,20), BP(2,19), The second order lowpass, bandpass
N/AP/HP(3,18) and notch/allpass/highpass outputs.
INV(4,17) The inverting input of the summing op-
S1(5,16) S1 is a signal input pin used in the all-
These outputs can typically sink 1.5 mA
and source 3 mA. Each output typically
swings to within 1V of each supply.
amp of each filter. These are high impedance inputs, but the non-inverting input is internally tied to AGND, making
INV
and INVBbehave like summing
A
junctions (low impedance, current inputs).
pass filter configurations (see modes 4
and 5). The pin should be driven with a
source impedance of less than 1 kX.If
S1 is not driven with a signal it should be
tied to AGND (mid-supply).
S
(6) This pin activates a switch that connects
A/B
one of the inputs of each filter’s second
summer to either AGND (S
b
V
) or to the lowpass (LP) output (S
tied to Va). This offers the flexibility
needed for configuring the filter in its
various modes of operation.
a
V
A
a
(7),V
(8) Analog positive supply and digital posi-
D
tive supply. These pins are internally
connected through the IC substrate and
therefore V
rived from the same power supply
a
and V
A
source. They have been brought out
separately so they can be bypassed by
separate capacitors, if desired. They
can be externally tied together and bypassed by a single capacitor.
b
V
A
(14), V
b
(13) Analog and digital negative supplies.
D
The same comments as for V
a
V
apply here.
D
5
a
should be de-
D
A/B
tied to
a
A
A/B
and
Pin Descriptions (Continued)
LSh(9) Level shift pin; it accommodates various
CLKA(10), Clock inputs for each switched capaciCLKB(11) tor filter building block. They should both
50/100/CL(12) By tying this pin high a 50:1 clock-to-fil-
AGND(15) This is the analog ground pin. This pin
clock levels with dual or single supply
operation. With dual
g
5V supplies, the
MF10 can be driven with CMOS clock
g
levels (
5V) and the LSh pin should be
tied to the system ground. If the same
supplies as above are used but only TTL
clock levels, derived from 0V to
a
5V
supply, are available, the LSh pin should
be tied to the system ground. For single
supply operation (0V and
b
b
V
,V
A
the system ground, the AGND pin
pins should be connected to
D
should be biased at
a
10V) the
a
5V and the LSh
pin should also be tied to the system
ground for TTL clock levels. LSh should
be biased at
a
5V for CMOS clock lev-
els in 10V single-supply applications.
be of the same level (TTL or CMOS).
The level shift (LSh) pin description discusses how to accommodate their levels. The duty cycle of the clock should
be close to 50% especially when clock
frequencies above 200 kHz are used.
This allows the maximum time for the
internal op-amps to settle, which yields
optimum filter operation.
ter-center-frequency ratio is obtained.
Tying this pin at mid-supplies (i.e, analog
ground with dual supplies) allows the filter to operate at a 100:1 clock-to-center-frequency ratio. When the pin is tied
low (i.e., negative supply with dual supplies), a simple current limiting circuit is
triggered to limit the overall supply current down to about 2.5 mA. The filtering
action is then aborted.
should be connected to the system
ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of midsupply biasing techniques see the Applications Information (Section 3.2). For
optimum filter performance a ‘‘clean’’
ground must be provided.
1.0 Definition of Terms
f
: the frequency of the external clock signal applied to
CLK
pin 10 or 11.
f
: center frequency of the second order function complex
O
pole pair. f
MF10, and is the frequency of maximum bandpass gain.
(Figure 1)
f
notch
notch outputs.
f
: the center frequency of the second order complex zero
z
pair, if any. If f
observed as the frequency of a notch at the allpass output.
(Figure 10)
Q: ‘‘quality factor’’ of the 2nd order filter. Q is measured at
the bandpass outputs of the MF10 and is equal to f
by the
(Figure 1)
order filter responses as shown in
QZ: the quality factor of the second order complex zero pair,
if any. Q
written:
H
AP
where Q
H
OBP
H
OLP
(Figure 2)
H
OHP
f
CLK
HON: the gain (in V/V) of the notch output as fx0Hz
and as f
above and below the center frequency
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3a
below are used in place of H
H
ON1
H
ON2
is measured at the bandpass outputs of the
O
: the frequency of minimum (ideally zero) gain at the
is different from fOand if QZis high, it can be
z
divided
b
3 dB bandwidth of the 2nd order bandpass filter
O
. The value of Q determines the shape of the 2nd
Figure 6
.
is related to the allpass characteristic, which is
Z
s0
O
2
H
s
OAP
#
e
(s)
2
a
s
e
Q for an all-pass response.
Z
b
s0
Q
O
Q
2
a
0
O
Z
a
J
2
0
O
: the gain (in V/V) of the bandpass output at fefO.
: the gain (in V/V) of the lowpass output as fx0Hz
.
: the gain (in V/V) of the highpass output as f
/2
(Figure 3)
.
x
f
/2, when the notch filter has equal gain
CLK
(Figures 11
and8), the two quantities
.
ON
(Figure 4)
. When the
: the gain (in V/V) of the notch output as fx0 Hz.
: the gain (in V/V) of the notch output as fxf
CLK
x
/2.
6
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