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MF10
Universal Monolithic Dual
Switched Capacitor Filter
General Description
The MF10 consists of 2 independent and extremely easy to
use, general purpose CMOS active filter building blocks.
Each block, together with an external clock and 3 to 4 resistors, can produce various 2nd order functions. Each building
block has 3 output pins. One of the outputs can be configured to perform either an allpass, highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and
bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both
clock frequency and external resistor ratios. The center frequency of the notch and allpass functions is directly dependent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th
order functions can be performed by cascading the two 2nd
order building blocks of the MF10; higher than 4th order
functions can be obtained by cascading MF10 packages.
December 1994
Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and Chebyshev) can be formed.
For pin-compatible device with improved performance refer
to LMF100 datasheet.
Features
Y
Easy to use
Y
Clock to center frequency ratio accuracyg0.6%
Y
Filter cutoff frequency stability directly dependent on
external clock quality
Y
Low sensitivity to external component variation
Y
Separate highpass (or notch or allpass), bandpass, lowpass outputs
Y
c
f
Q range up to 200 kHz
O
Y
Operation up to 30 kHz
Y
20-pin 0.3×wide Dual-In-Line package
Y
20-pin Surface Mount (SO) wide-body package
MF10 Universal Monolithic Dual Switched Capacitor Filter
System Block Diagram
TL/H/10399– 1
Connection Diagram
Surface Mount and Dual-In-Line
Package
TL/H/10399– 4
Top View
Order Number MF10AJ or MF10CCJ
See NS Package Number J20A
Order Number MF10ACWM or
MF10CCWM
See NS Package Number M20B
Order Number MF10ACN or
MF10CCN
See NS Package Number N20A
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/H/10399
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
a
Supply Voltage (V
Voltage at Any Pin V
b
Vb) 14V
a
b
V
a
0.3V
b
0.3V
Input Current at Any Pin (Note 2) 5 mA
Package Input Current (Note 2) 20 mA
Power Dissipation (Note 3) 500 mW
Storage Temperature 150
§
ESD Susceptability (Note 11) 2000V
a
Electrical Characteristics V
apply for T
MIN
to T
MAX
; all other limits T
ea
5.00V and V
e
e
T
A
25§C.
J
Symbol Parameter Conditions
a
b
V
VbSupply Voltage Min 99V
Max 14 14 V
I
S
f
O
f
CLK
f
CLK/fO
f
CLK/fO
H
V
V
V
V
V
Maximum Supply Clock Applied to Pins 10 & 11
Current No Input Signal
Center Frequency Min f
Range
Clock Frequency Min 5.0 10 5.0 10 Hz
Range
50:1 Clock to MF10A Qe10 V
Center Frequency
Ratio Deviation
100:1 Clock to MF10A Qe10 V
Center Frequency
Ratio Deviation
Max 30 20 30 20 kHz
Max 1.5 1.0 1.5 1.0 MHz
MF10C
MF10C
Clock Feedthrough Qe10
Q Error (MAX) Qe10 V
(Note 4) Mode 1 f
DC Lowpass Gain Mode 1 R1eR2e10k 0
OLP
DC Offset Voltage (Note 5)
OS1
DC Offset Voltage Min V
OS2
(Note 5)
Max
Min V
Max
DC Offset Voltage Min V
OS3
(Note 5)
DC Offset Voltage V
OS2
(Note 5) (f
Max
(Note 5) (f
DC Offset Voltage V
OS3
(Note 5) (f
c
Qk200 kHz 0.1 0.2 0.1 0.2 Hz
O
pin12
Mode 1 f
Mode 1 f
CLK
pin12
CLK
e
e
Mode 1
pin12
e
CLK
V
pin12
e
f
CLK
pin12
(f
CLK/fO
pin12
(f
CLK/fO
pin12
(f
CLK/fO
pin12
CLK/fO
V
pin12
CLK/fO
pin12
CLK/fO
ea
5V S
e
50)
ea
5V S
e
50)
ea
5V All Modes
e
50)
e
0V S
e
100)
e
0V S
e
100)
e
0V All Modes
e
100)
A/B
A/B
A/B
A/B
e
e
e
e
Soldering Information
N Package: 10 sec. 260
J Package: 10 sec. 300
SO Package: Vapor Phase (60 Sec.) 215
Infrared (15 Sec.) 220
See AN-450 ‘‘Surface Mounting Methods and Their Effect
on Product Reliability’’ (Appendix D) for other methods of
soldering surface mount devices.
Operating Ratings (Note 1)
C
Temperature Range T
MF10ACN, MF10CCN 0§CsT
MF10CCWM, MF10ACWM 0§CsT
e
5V
250 kHz
e
0V
500 kHz
e
5V
250 kHz
e
0V
500 kHz
a
V
b
V
a
V
b
V
2
MF10CCJ
MF10AJ
b
eb
5.00V unless otherwise specified. Boldface limits
MF10ACN, MF10CCN,
MF10ACWM, MF10CCWM
Tested Design
Typical
(Note 8)
Limit Limit
(Note 9) (Note 10) (Note 9) (Note 10)
81212 8 12 mA
g
0.2g0.6g0.6g0.2g1.0 %
g
0.2g1.5g1.5g0.2g1.5 %
g
0.2g0.6g0.6g0.2g1.0 %
g
0.2g1.5g1.5g0.2g1.5 %
10 10 mV
g
g
2
g
2
g
g
5.0g20
b
150b185b185b150b185
b
b
70
b70b
b
b
300
b
140
b
140
g
6
6
g
g
6
6
0.2g0.2 0
g
20g5.0g20 mV
b
85
85
100b100b70b100
b
20
20
b
MF10CCJ, MF10AJ
Tested Design Units
Typical
(Note 8)
g2g
g2g
b
70 mV
b
300 mV
b
140 mV
b
140 mV
s
s
T
MIN
A
s
A
s
A
b
40§CsT
55§CsT
s
A
s
125§C
A
Limit Limit
10 %
10 %
g
0.2 dB
b
85
b
20
T
MAX
70§C
70§C
85§C
C
§
C
§
C
§
C
§
mV
mV
Electrical Characteristics (Continued) V
Boldface limits apply for T
MIN
to T
MAX
; all other limits T
a
Symbol Parameter Conditions
V
Minimum Output BP, LP Pins R
OUT
Voltage Swing
N/AP/HP Pin R
e
5k
L
e
3.5k
L
ea
e
A
5.00V and V
T
J
Typical
(Note 8)
b
eb
e
25§C.
MF10ACN, MF10CCN,
MF10ACWM, MF10CCWM
g
4.25g3.8
g
4.25g3.8
5.00V unless otherwise specified.
MF10CCJ, MF10AJ
Tested Design
Limit Limit
(Note 9) (Note 10) (Note 9) (Note 10)
Typical
(Note 8)
g
3.8g4.25g3.8 V
g
3.8g4.25g3.6 V
Tested Design Units
Limit Limit
GBW Op Amp Gain BW Product 2.5 2.5 MHz
SR Op Amp Slew Rate 7 7 V/ms
Dynamic Range V
(Note 6) (f
I
Maximum Output Short Source 20 20 mA
SC
Circuit Current (Note 7)
Sink 3.0 3.0 mA
Logic Input Characteristics Boldface limits apply for T
Parameter Conditions
a
CMOS Clock Min Logical ‘‘1’’ V
Input Voltage
Max Logical ‘‘0’’
Min Logical ‘‘1’’ V
Max Logical ‘‘0’’
TTL Clock Min Logical ‘‘1’’ V
Input Voltage
Max Logical ‘‘0’’
Min Logical ‘‘1’’ V
Max Logical ‘‘0’’
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
device, T
number increases to 95
Note 4: The accuracy of the Q value is a function of the center frequency (f
Characteristics’’.
Note 5: V
Note 6: For
the MF10 with a 50:1 CLK ratio and 280 mV rms for the MF10 with a 100:1 CLK ratio.
Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8: Typicals are at 25
Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 11: Human body model, 100 pF discharged through a 1.5 kX resistor.
e
125§C, and the typical junction-to-ambient thermal resistance of the MF10ACN/CCN when board mounted is 55§C/W. For the MF10AJ/CCJ, this
JMAX
OS1,VOS2
C/W and for the MF10ACWM/CCWM this number is 66§C/W.
§
, and V
refer to the internal offsets as discussed in the Applications Information Section 3.4.
g
5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 mV rms for
OS3
C and represent most likely parametric norm.
§
ea
5V, V
e
V
0V
LSh
a
ea
10V, V
ea
V
LSh
a
ea
5V, V
e
V
0V
LSh
a
ea
10V, V
V
LSh
) at any pin exceeds the power supply rails (V
IN
ea
pin12
CLK/fO
V
pin12
(f
CLK/fO
b
5V
b
e
(T
D
5V
e
50)
e
0V
e
100)
Typical
(Note 8)
eb
5V,
b
e
0V,
eb
5V,
b
e
0V,
b
TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this
JMAX
83 83 dB
80 80 dB
to T
MIN
; all other limits T
MAX
MF10ACN, MF10CCN,
MF10ACWM, MF10CCWM
Tested Design
Limit Limit
(Note 9) (Note 10) (Note 9) (Note 10)
a
b
a
a
a
a
a
a
k
Vbor V
IN
). This is illustrated in the curves under the heading ‘‘Typical Performance
O
a
3.0
b
3.0
a
8.0
a
2.0
a
2.0
a
0.8
a
2.0
a
0.8
l
Va) the absolute value of current at that pin should be limited
IN
JMAX
Typical
(Note 8)
3.0
3.0
8.0
2.0
2.0
0.8
2.0
0.8
, iJA, and the ambient temperature, TA. The maximum
e
T
A
J
MF10CCJ, MF10AJ
Tested Design Units
Limit Limit
a
3.0 V
b
3.0 V
a
8.0 V
a
2.0 V
a
2.0 V
a
0.8 V
a
2.0 V
a
0.8 V
e
25§C
3
Typical Performance Characteristics
Power Supply Current
vs Power Supply Voltage
Negative Output
Swing vs Temperature
Q Deviation vs
Temperature
Positive Output Voltage Swing
vs Load Resistance
(N/AP/HP Output)
Positive Output Swing
vs Temperature
Q Deviation vs
Temperature
Negative Output Voltage
Swing vs Load
Resistance (N/AP/HP Output)
Crosstalk vs Clock
Frequency
Q Deviation vs
Clock Frequency
Q Deviation vs
Clock Frequency
Deviation
f
CLK/fO
vs Temperature
4
f
Deviation
CLK/fO
vs Temperature
TL/H/10399– 2
Typical Performance Characteristics (Continued)
Deviation
f
CLK/fO
vs Clock Frequency
f
Deviation
CLK/fO
vs Clock Frequency
f
Deviation of
vs Nominal Q
CLK
f
O
Deviation of
vs Nominal Q
f
CLK
f
O
TL/H/10399– 3
Pin Descriptions
LP(1,20), BP(2,19), The second order lowpass, bandpass
N/AP/HP(3,18) and notch/allpass/highpass outputs.
INV(4,17) The inverting input of the summing op-
S1(5,16) S1 is a signal input pin used in the all-
These outputs can typically sink 1.5 mA
and source 3 mA. Each output typically
swings to within 1V of each supply.
amp of each filter. These are high impedance inputs, but the non-inverting input is internally tied to AGND, making
INV
and INVBbehave like summing
A
junctions (low impedance, current inputs).
pass filter configurations (see modes 4
and 5). The pin should be driven with a
source impedance of less than 1 kX.If
S1 is not driven with a signal it should be
tied to AGND (mid-supply).
S
(6) This pin activates a switch that connects
A/B
one of the inputs of each filter’s second
summer to either AGND (S
b
V
) or to the lowpass (LP) output (S
tied to Va). This offers the flexibility
needed for configuring the filter in its
various modes of operation.
a
V
A
a
(7),V
(8) Analog positive supply and digital posi-
D
tive supply. These pins are internally
connected through the IC substrate and
therefore V
rived from the same power supply
a
and V
A
source. They have been brought out
separately so they can be bypassed by
separate capacitors, if desired. They
can be externally tied together and bypassed by a single capacitor.
b
V
A
(14), V
b
(13) Analog and digital negative supplies.
D
The same comments as for V
a
V
apply here.
D
5
a
should be de-
D
A/B
tied to
a
A
A/B
and
Pin Descriptions (Continued)
LSh(9) Level shift pin; it accommodates various
CLKA(10), Clock inputs for each switched capaciCLKB(11) tor filter building block. They should both
50/100/CL(12) By tying this pin high a 50:1 clock-to-fil-
AGND(15) This is the analog ground pin. This pin
clock levels with dual or single supply
operation. With dual
g
5V supplies, the
MF10 can be driven with CMOS clock
g
levels (
5V) and the LSh pin should be
tied to the system ground. If the same
supplies as above are used but only TTL
clock levels, derived from 0V to
a
5V
supply, are available, the LSh pin should
be tied to the system ground. For single
supply operation (0V and
b
b
V
,V
A
the system ground, the AGND pin
pins should be connected to
D
should be biased at
a
10V) the
a
5V and the LSh
pin should also be tied to the system
ground for TTL clock levels. LSh should
be biased at
a
5V for CMOS clock lev-
els in 10V single-supply applications.
be of the same level (TTL or CMOS).
The level shift (LSh) pin description discusses how to accommodate their levels. The duty cycle of the clock should
be close to 50% especially when clock
frequencies above 200 kHz are used.
This allows the maximum time for the
internal op-amps to settle, which yields
optimum filter operation.
ter-center-frequency ratio is obtained.
Tying this pin at mid-supplies (i.e, analog
ground with dual supplies) allows the filter to operate at a 100:1 clock-to-center-frequency ratio. When the pin is tied
low (i.e., negative supply with dual supplies), a simple current limiting circuit is
triggered to limit the overall supply current down to about 2.5 mA. The filtering
action is then aborted.
should be connected to the system
ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of midsupply biasing techniques see the Applications Information (Section 3.2). For
optimum filter performance a ‘‘clean’’
ground must be provided.
1.0 Definition of Terms
f
: the frequency of the external clock signal applied to
CLK
pin 10 or 11.
f
: center frequency of the second order function complex
O
pole pair. f
MF10, and is the frequency of maximum bandpass gain.
(Figure 1)
f
notch
notch outputs.
f
: the center frequency of the second order complex zero
z
pair, if any. If f
observed as the frequency of a notch at the allpass output.
(Figure 10)
Q: ‘‘quality factor’’ of the 2nd order filter. Q is measured at
the bandpass outputs of the MF10 and is equal to f
by the
(Figure 1)
order filter responses as shown in
QZ: the quality factor of the second order complex zero pair,
if any. Q
written:
H
AP
where Q
H
OBP
H
OLP
(Figure 2)
H
OHP
f
CLK
HON: the gain (in V/V) of the notch output as fx0Hz
and as f
above and below the center frequency
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3a
below are used in place of H
H
ON1
H
ON2
is measured at the bandpass outputs of the
O
: the frequency of minimum (ideally zero) gain at the
is different from fOand if QZis high, it can be
z
divided
b
3 dB bandwidth of the 2nd order bandpass filter
O
. The value of Q determines the shape of the 2nd
Figure 6
.
is related to the allpass characteristic, which is
Z
s0
O
2
H
s
OAP
#
e
(s)
2
a
s
e
Q for an all-pass response.
Z
b
s0
Q
O
Q
2
a
0
O
Z
a
J
2
0
O
: the gain (in V/V) of the bandpass output at fefO.
: the gain (in V/V) of the lowpass output as fx0Hz
.
: the gain (in V/V) of the highpass output as f
/2
(Figure 3)
.
x
f
/2, when the notch filter has equal gain
CLK
(Figures 11
and8), the two quantities
.
ON
(Figure 4)
. When the
: the gain (in V/V) of the notch output as fx0 Hz.
: the gain (in V/V) of the notch output as fxf
CLK
x
/2.
6
1.0 Definition of Terms (Continued)
TL/H/10399– 5
(a)
FIGURE 1. 2nd-Order Bandpass Response
TL/H/10399– 7
(a)
FIGURE 2. 2nd-Order Low-Pass Response
(b)
(b)
TL/H/10399– 6
TL/H/10399– 8
HBP(s)
e
Q
e
f
L
e
f
H
0
O
HLP(s)
e
f
C
e
f
p
H
OP
0O
H
S
OBP
e
f
O
b
f
H
f
O
#
f
O
e
2qf
e
c
f
O
f
O
0
e
H
Q
s0
O
Q
e
0#
0#
OLP0O
s0
Q
b
1
1
2Q
1
Q
2
a
0
O
fLf
0
H
2
1
a
1
2Q
J
J
2
1
a
1
2Q
J
J
2
O
2
a
0
O
1
2
2Q
Ja0#
2
1
1
b
1
2
4Q
0
2
1
b
a
1
1
2
2Q
J
2
a
s
;f
O
f
L
b
1
a
2Q
1
a
2Q
#
O
H
2
a
s
0
#
b
1
c
OLP
(a)
TL/H/10399– 9
2
H
s
OHP
e
HHP(s)
e
f
C
e
f
p
H
OP
FIGURE 3. 2nd-Order High-Pass Response
s0
O
2
a
s
c
f
O
0
Ð
c
f
1
O
Ð0
e
c
H
OHP
2
a
0
O
Q
1
b
1
2
2Q
#
Ja0#
b
1
1
b
2
2Q
(
1
1
1
b
1
2
Q
4Q
0
2
1
b
1
a
1
2
2Q
J
7
(b)
TL/H/10399– 10
b
1
(
1.0 Definitions of Terms (Continued)
TL/H/10399– 11
(a)
FIGURE 4. 2nd-Order Notch Response
(b)
TL/H/10399– 12
HN(s)
e
Q
e
f
L
e
f
H
HAP(s)
2
2
a
HON(s
0
)
e
2
s
f
O
b
f
f
H
b
f
O
2Q
#
f
O
2Q
#
e
O
s0
O
a
;f
L
1
1
a
H
OAP
2
a
0
O
Q
e
fLf
0
O
H
2
1
a
s
a
1
2Q
0#
J
J
2
1
a
1
2Q
0#
J
J
s0
O
2
b
s
#
s0
2
a
Q
2
a
0
O
Q
O
J
2
a
0
O
TL/H/10399– 13
(a)
TL/H/10399– 14
(b)
FIGURE 5. 2nd-Order All-Pass Response
(a) Bandpass (b) Low Pass (c) High-Pass
(d) Notch (e) All-Pass
FIGURE 6. Response of various 2nd-order filters as a function of Q.
Gains and center frequencies are normalized to unity.
8
TL/H/10399– 15
2.0 Modes of Operation
The MF10 is a switched capacitor (sampled data) filter. To
fully describe its transfer functions, a time domain approach
is appropriate. Since this is cumbersome, and since the
MF10 closely approximates continuous filters, the following
discussion is based on the well know frequency domain.
Each MF10 can produce a full 2nd order function. See Table I for a summary of the characteristics of the various
modes.
MODE 1: Notch 1, Bandpass, Lowpass Outputs:
e
f
O
e
e
f
notch
e
H
OLP
e
H
OBP
e
H
ON
e
f
fO(See
Figure 7
notch
)
center frequency of the complex pole pair
f
f
CLK
CLK
or
100
50
center frequency of the imaginary zero pairefO.
R2
Lowpass gain (as fx0)
Bandpass gain (at fefO)
Notch output gain as
eb
eb
fx0
fxf
CLK
R3
R1
R1
b
R
2
e
/2
R
(
1
f
R3
O
e
Q
e
BW
e
R2
quality factor of the complex pole pair
BWetheb3 dB bandwidth of the bandpass output.
Circuit dynamics:
H
OBP
e
H
OLP
H
OLP(peak)
or H
OBP
Q
c
e
H
Q.
ON
j
c
Q
H
OLP
MODE 1a: Non-Inverting BP, LP (See
f
f
CLK
e
f
O
e
Q
eb
H
OLP
eb
H
OBP
1
e
H
OBP
2
Circuit Dynamics: H
Note: VINshould be driven from a low impedance (k1kX) source.
CLK
or
100
50
R3
R2
1; H
OLP(peak)
R3
R2
1 (Non-Inverting)
OBP1
j
c
Q
e
Q
e
H
OLP
(for high Q’s)
Figure 8
H
OLP
c
Q
)
(for high Q’s)
FIGURE 7. MODE 1
FIGURE 8. MODE 1a
9
TL/H/10399– 16
TL/H/10399– 17
2.0 Modes of Operation (Continued)
a
CLK
2
2
notch
1
J
e
k
eb
H
0
ON1HON2
MODE 2: Notch 2, Bandpass, Lowpass: f
(See
Figure 9
)
e
f
center frequency
O
f
R2
CLK
e
100
R4
0
f
f
CLK
e
f
notch
Q
H
OLP
H
OBP
H
ON
1
H
ON
2
Filter dynamics: H
or
100
e
quality factor of the complex pole pair
R2/R4a1
0
e
R2/R3
e
Lowpass output gain (as fx0)
R2/R1
eb
R2/R4a1
e
Bandpass output gain (at fefO)ebR3/R1
e
Notch output gain (as fx0)
R2/R1
eb
R2/R4a1
e
Notch output gain#as f
CLK
50
OBP
f
R2
CLK
a
1or
50
R4
0
f
x
e
Q0H
OLPHON
f
O
R2/R1
MODE 3: Highpass, Bandpass, Lowpass Outputs
(See
Figure 10
e
f
O
e
Q
e
e
H
OHP
e
H
OBP
e
H
OLP
Circuit dynamics:
H
OLP(peak)
H
OHP(peak)
)
0
R3
R2
R2
R4
H
c
c
R2
R4
OBP
H
e
OLP
H
OHP
f
CLK
or
50
x
H
OHP
;
H
OLP
e
H
0
OHP
(for high Q’s)
(for high Q’s)
R2
c
R4
0
f
CLK
eb
2
J
R3
eb
O
R1
J
R4
eb
R1
J
c
c
H
OLP
f
CLK
c
100
quality factor of the complex pole pair
R2
c
R4
0
Highpass Gain#as f
Lowpass Gain#at fef
Lowpass Gain#as fx0
j
Q
j
Q
R2
R1
Q
FIGURE 9. MODE 2
*In Mode 3, the feedback loop is closed around the input summing amplifier; the finite GBW product of this op amp causes a slight Q enhancement. If this is a
problem, connect a small capacitor (10 pF
b
100 pF) across R4 to provide some phase lead.
FIGURE 10. MODE 3
10
TL/H/10399– 18
TL/H/10399– 19
2.0 Modes of Operation (Continued)
MODE 3a: HP, BP, LP and Notch with External Op Amp
(See
f
O
Q
H
OHP
H
OBP
H
OLP
f
n
H
ON
H
n1
H
n2
Figure 11
)
f
e
e
0
eb
eb
eb
e
notch frequency
e
f
e
gain of notch (as fx0)
e
gain of notch#as f
eb
R2
CLK
c
100
R4
0
R2
R3
c
R4
R2
R2
R1
R3
R1
R4
R1
gain of notch at
e
e
f
O
ÀÀQ#
R
g
c
H
OHP
R
h
or
e
R
g
R
f
I
CLK
50
H
f
CLK
100
OLP
x
R2
c
R4
0
f
R
h
or
R
0
I
R
g
b
H
R
h
R
g
e
R
I
f
CLK
2
J
OHP
c
CLK
50
H
JÀÀ
OLP
R
h
R
0
I
MODE 4: Allpass, Bandpass, Lowpass Outputs
(See
Figure 12
f
O
Q
*eAllpass gain#at 0kf
H
OAP
H
OLP
H
OBP
Circuit Dynamics: H
*Due to the sampled data nature of the filter, a slight mismatch of fzand f
occurs causing a 0.4 dB peaking around fOof the allpass filter amplitude
response (which theoretically should be a straight line). If this is unacceptable, Mode 5 is recommended.
)
e
center frequency
f
f
CLK
e
e
e
eb
e
eb
CLK
or
100
fz*ecenter frequency of the complex zero&f
f
O
BW
Q
Z
For AP output make R1eR2
Lowpass gain (as fx0)
Bandpass gain (at fefO)
;
50
R3
e
;
R2
e
quality factor of complex zero pair
f
CLK
k
2
J
R2
a
eb
1
a
OBP
2
J
R2
R1
J
e
eb
(H
OLP
R3
2
R2
#
J
)cQe(H
R3
R2
#
R1
1
#
eb
e
R2
R1
OAP
R3
R1
eb
a
1
1)Q
O
O
FIGURE 11. MODE 3a
FIGURE 12. MODE 4
11
TL/H/10399– 20
TL/H/10399– 21
2.0 Modes of Operation (Continued)
MODE 5: Numerator Complex Zeros, BP, LP
(See
f
O
f
z
Q
Q
Z
H
0
H
0
H
OBP
H
OLP
Figure 13
z1
z2
)
R2
f
e
a
1
0
e
b
1
0
e
1aR2/R4
0
e
1bR1/R4
0
e
gain at C.Z. output (as fx0 Hz)
b
R2(R4bR1)
R1(R2aR4)
e
gain at C.Z. output#as f
R2
e
b
R1
#
R2aR1
e
b
R2aR4
#
R4
R2
R4
CLK
c
100
f
CLK
c
100
R3
c
R2
R3
c
R1
a
or
1
0
b
or
1
0
x
R3
a
c
1
R2
J
R4
c
R1
J
R2
R4
R1
R4
f
CLK
2
f
CLK
c
50
f
CLK
c
50
b
e
J
R1
R2
MODE 6a: Single Pole, HP, LP Filter (See
e
f
H
H
MODE 6b: Single Pole LP Filter (Inverting and Non-Inverting) (See
f
H
H
cutoff frequency of LP or HP output
c
e
f
CLK
or
100
Figure 15
f
CLK
or
100
R2R3f
)
R2R3f
OLP
OHP
c
OLP1
OLP2
R2
R3
R3
e
b
R1
R2
e
b
R1
e
cutoff frequency of LP outputs
R2
j
R3
e
1 (non-inverting)
R3
e
b
R2
CLK
50
CLK
50
Figure 14
)
FIGURE 13. MODE 5
FIGURE 14. MODE 6a
FIGURE 15. MODE 6b
12
TL/H/10399– 22
TL/H/10399– 23
TL/H/10399– 24
2.0 Modes of Operation (Continued)
TABLE I. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks.
Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios.
Mode BP LP HP N AP
Number of Adjustable
Resistors f
CLK/fO
1 ***3No
(2) May need input buffer.
eb
1a H
H
OBP1
OBP2
QH
ea
1 high Q.
2 ***3
3 *** 4 Yes
3a ****7 Yes
4 ** *3No
5 ** *4
a
1 2 No Poor dynamics for
OLP
CLK
CLK
/100)
/50
Universal State-Variable
Filter. Best general-purpose mode.
As above, but also includes
resistor-tuneable notch.
Gives Allpass response with
H
Gives flatter allpass response
than above if R
Yes (above f
or f
OAP
6a ** 3 Single pole.
(2)
ea
6b H
H
OLP1
OLP2
1 2 Single Pole.
b
R3
e
R2
3.0 Applications Information
The MF10 is a general-purpose dual second-order state
variable filter whose center frequency is proportional to the
frequency of the square wave applied to the clock input
(f
). By connecting pin 12 to the appropriate DC voltage,
CLK
the filter center frequency f
f
/100 or f
CLK
g
6%) by using a crystal clock oscillator, or can be easily
/50. fOcan be very accurately set (within
CLK
can be made equal to either
O
varied over a wide frequency range by adjusting the clock
frequency. If desired, the f
external resistors as in
Figures 9, 10, 11, 13, 14
ratio can be altered by
CLK/fO
and15. The
filter Q and gain are determined by external resistors.
All of the five second-order filter types can be built using
either section of the MF10. These are illustrated in
Figures 1
through5along with their transfer functions and some related equations.
Figure 6
shows the effect of Q on the shapes
of these curves. When filter orders greater than two are
desired, two or more MF10 sections can be cascaded.
3.1 DESIGN EXAMPLE
In order to design a second-order filter section using the
MF10, we must define the necessary values of three parameters: f
, the filter section’s center frequency; H0, the pass-
0
band gain; and the filter’s Q. These are determined by the
characteristics required of the filter being designed.
As an example, let’s assume that a system requires a
fourth-order Chebyshev low-pass filter with 1 dB ripple, unity
gain at DC, and 1000 Hz cutoff frequency. As the system
order is four, it is realizable using both second-order sections of an MF10. Many filter design texts include tables that
list the characteristics (f
der filter sections needed to synthesize a given higher-order
and Q) of each of the second-or-
O
filter. For the Chebyshev filter defined above, such a table
yields the following characteristics:
e
f
0A
e
f
0B
529 Hz Q
993 Hz Q
e
0.785
A
e
3.559
B
For unity gain at DC, we also specify:
e
H
1
0A
e
H
1
0B
The desired clock-to-cutoff-frequency ratio for the overall
filter of this example is 100 and a 100 kHz clock signal is
available. Note that the required center frequencies for the
two second-order sections will not be obtainable with clockto-center-frequency ratios of 50 or 100. It will be necessary
f
to adjust
can be used to produce a low-pass filter with resistor-adjust-
CLK
externally. From Table I, we see that Mode 3
f
0
able center frequency.
In most filter designs involving multiple second-order
stages, it is best to place the stages with lower Q values
ahead of stages with higher Q, especially when the higher Q
is greater than 0.707. This is due to the higher relative gain
at the center frequency of a higher-Q stage. Placing a stage
with lower Q ahead of a higher-Q stage will provide some
attenuation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage
A has the lower Q (0.785) so it will be placed ahead of the
other stage.
For the first section, we begin the design by choosing a
convenient value for the input resistance: R
absolute value of the passband gain H
eb
Notes
1 and H
1
OLPA
eb
OLP
e
e
R
0.02R4.
2
e
20k. The
1A
is made equal
2.
13
3.0 Applications Information (Continued)
eb
H
4A
4
c
(529)
(1000)
3
c
OLPAR1A
2
e
2
2c10
f
0A
/100)
4A
4A
2
e
such that: R
e
2c10
2
0.78505.6c10
to 1 by choosing R
e
R
20k. If the 50/100/CL pin is connected to mid-sup-
1A
ply for nominal 100:1 clock-to-center-frequency ratio, we
find R
by:
2A
e
R
R
2A
4A
(f
CLK
e
Q
A
R2AR
0
R
3A
5.6k and
4
e
8.3k
e
The resistors for the second section are found in a similar
fashion:
e
R
20k
1B
e
e
R
R
4B
e
R
2B
e
R
3B
The complete circuit is shown in
20k
1B
2
f
0B
/100)
4B
2
e
e
20k
3.55901.97c10
R
4B
(f
CLK
Q
R2BR
0
B
(993)
(1000)
Figure 16
2
e
2
4
19.7k
c
2c10
for splitg5V
4
e
70.6k
power supplies. Supply bypass capacitors are highly recommended.
FIGURE 16. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1.
TL/H/10399– 25
g
5V Power Supply. 0V–5V TTL orb5Vg5V CMOS Logic Levels.
FIGURE 17. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1.
Single
a
10V Power Supply. 0V–5V TTL Logic Levels. Input Signals
TL/H/10399– 26
Should be Referred to Half-Supply or Applied through a Coupling Capacitor.
14
3.0 Applications Information (Continued)
(a) Resistive Divider with
TL/H/10399– 27
(b) Voltage Regulator
Decoupling Capacitor
FIGURE 18. Three Ways of Generating
3.2 SINGLE SUPPLY OPERATION
The MF10 can also operate with a single-ended power supply.
Figure 17
power supply. V
positive power supply (8V to 14V), and V
connected to ground. The A
for single supply operation. This half-supply point should be
shows the example filter with a single-ended
a
A
and V
a
are again connected to the
D
GND
b
and V
A
pin must be tied to Va/2
b
are
D
very ‘‘clean’’, as any noise appearing on it will be treated as
an input to the filter. It can be derived from the supply voltage with a pair of resistors and a bypass capacitor
18a)
, or a low-impedance half-supply voltage can be made
(Figure
using a three-terminal voltage regulator or an operational
amplifier
(Figures 18b
and
18c)
. The passive resistor divider
with a bypass capacitor is sufficient for many applications,
provided that the time constant is long enough to reject any
power supply noise. It is also important that the half-supply
reference present a low impedance to the clock frequency,
so at very low clock frequencies the regulator or op-amp
approaches may be preferable because they will require
smaller capacitors to filter the clock frequency. The main
power supply voltage should be clean (preferably regulated)
and bypassed with 0.1 mF.
3.3 DYNAMIC CONSIDERATIONS
The maximum signal handling capability of the MF10, like
that of any active filter, is limited by the power supply voltages used. The amplifiers in the MF10 are able to swing to
within about 1V of the supplies, so the input signals must be
kept small enough that none of the outputs will exceed
these limits. If the MF10 is operating on
the outputs will clip at about 8 V
voltage multiplied by the filter gain should therefore be less
than 8 V
p–p
.
g
5V, for example,
. The maximum input
p–p
Note that if the filter Q is high, the gain at the lowpass or
highpass outputs will be much greater than the nominal filter
gain
(Figure 6)
. As an example, a lowpass filter withaQof
TL/H/10399– 28
TL/H/10399– 29
(c) Operational Amplifier
with Divider
a
V
for Single-Supply Operation
2
10 will have a 20 dB peak in its amplitude response at f
the nominal gain of the filter H
f
will be 10. The maximum input signal at fOmust therefore
O
be less than 800 mV
g
5V supplies.
p–p
is equal to 1, the gain at
OLP
when the circuit is operated on
O
Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1
output will be very small at f
apply a large signal to the input. However, the bandpass will
have its maximum gain at f
one output clips, the performance at the other outputs will
(Figure 7)
, so it might appear safe to
O
and can clip if overdriven. If
O
. The notch
be degraded, so avoid overdriving any filter section, even
ones whose outputs are not being directly used. Accompanying
Figures 7
through15are equations labeled ‘‘circuit
dynamics’’, which relate the Q and the gains at the various
outputs. These should be consulted to determine peak circuit gains and maximum allowable signals for a given application.
3.4 OFFSET VOLTAGE
The MF10’s switched capacitor integrators have a higher
equivalent input offset voltage than would be found in a
typical continuous-time active filter integrator.
Figure 19
shows an equivalent circuit of the MF10 from which the output DC offsets can be calculated. Typical values for these
offsets with S
e
V
opamp offset
os1
eb
V
os2
eb
V
os3
When S
A/B
DC offset at the BP output is equal to the input offset of the
lowpass integrator (V
depend on the mode of operation and the resistor ratios, as
tied to Vaare:
A/B
e
150 mV@50:1
70 mV@50:1
is tied to Vb,V
os3
g
5mV
will approximately halve. The
os2
b
300 mV@100:1
b
140 mV@100:1
). The offsets at the other outputs
described in the following expressions.
.If
15
3.0 Applications Information (Continued)
Mode 1 and Mode 4
V
OS(N)
V
OS(BP)
V
OS(LP)
Mode 1a
(N.INV.BP)
V
OS
V
(INV.BP)eV
OS
V
OS(LP)
e
e
e
e
e
1
OS1
OS3
OS(N)
#
OS3
a
1ÀÀH
Q
#
b
V
OS2
1
a
1
b
V
OS1
Q
J
V
V
V
VOS(N.INV.BP)bV
V
OLP
OS3
Q
OS2
ÀÀJ
V
OS3
b
Q
Mode 2 and Mode 5
R2
e
V
OS(N)
V
OS(BP)
V
OS(LP)
Mode 3
V
OS(HP)
V
OS(BP)
V
OS(LP)
a
R
#
p
a
V
OS2
e
R
p
e
V
OS3
e
V
OS(N)
e
V
OS2
e
V
OS3
e
V
OS1
b
V
OS3
RpeR1//R2//R3
1JV
OS1
1
1aR4/R2
R1//R3//R4
b
V
OS2
R4
a
1
R
Ð
(
p
R4
R3
#
J
c
1aR2/R4
b
Q01aR2/R4
b
V
OS2
1
V
OS3
:
R4
R2
#
J
FIGURE 19. MF10 Offset Voltage Sources
FIGURE 20. Method for Trimming V
16
OS
TL/H/10399– 30
TL/H/10399– 31
3.0 Applications Information (Continued)
For most applications, the outputs are AC coupled and DC
offsets are not bothersome unless large signals are applied
to the filter input. However, larger offset voltages will cause
clipping to occur at lower AC signal levels, and clipping at
any of the outputs will cause gain nonlinearities and will
change f
become excessively large if R2 and R4 are used to make
f
CLK/fO
cially if Q is also high. An extreme example is a bandpass
filter having unity gain,aQof20,andf
pin 12 tied to ground (100:1 nominal). R4/R2 will therefore
be equal to 6.25 and the offset voltage at the lowpass output will be about
can be adjusted by using the circuit of
adjustment of V
different outputs as described in the above equations. Some
outputs cannot be adjusted this way in some modes, however (V
3.5 SAMPLED DATA SYSTEM CONSIDERATIONS
The MF10 is a sampled data filter, and as such, differs in
many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the
sampling frequency. (The MF10’s sampling frequency is the
same as its clock frequency.) If a signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled data system, it will be ‘‘reflected’’ to
a frequency less than one-half the sampling frequency.
Thus, an input signal whose frequency is f
cause the system to respond as though the input frequency
and Q. When operating in Mode 3, offsets can
O
significantly higher than the nominal value, espe-
e
250 with
. This allows
/2a100 Hz will
s
a
1V. Where necessary , the offset voltage
, which will have varying effects on the
OS1
in modes 1a and 3, for example).
OS(BP)
CLK/fO
Figure 20
was f
/2b100 Hz. This phenomenon is known as ‘‘alias-
s
ing’’, and can be reduced or eliminated by limiting the input
signal spectrum to less than f
require the use of a bandwidth-limiting filter ahead of the
/2. This may in some cases
s
MF10 to limit the input spectrum. However, since the clock
frequency is much higher than the center frequency, this will
often not be necessary.
Another characteristic of sampled-data circuits is that the
output signal changes amplitude once every sampling period, resulting in ‘‘steps’’ in the output voltage which occur at
the clock rate
(Figure 21)
. If necessary, these can be
‘‘smoothed’’ with a simple R –C low-pass filter at the MF10
output.
The ratio of f
also affect performance. A ratio of 100:1 will reduce any
to fC(normally either 50:1 or 100:1) will
CLK
aliasing problems and is usually recommended for wideband input signals. In noise sensitive applications, however,
a ratio of 50:1 may be better as it will result in 3 dB lower
output noise. The 50:1 ratio also results in lower DC offset
voltages, as discussed in Section 3.4.
The accuracy of the f
of Q. This is illustrated in the curves under the heading
ratio is dependent on the value
CLK/fO
‘‘Typical Performance Characteristics’’. As Q is changed,
the true value of the ratio changes as well. Unless the Q is
low, the error in f
for a specific application, use a mode that allows adjustment
will be small. If the error is too large
CLK/fO
of the ratio with external resistors.
It should also be noted that the product of Q and f
be limited to 300 kHz when f
l
f
5 kHz.
O
k
5 kHz, and to 200 kHz for
O
O
should
FIGURE 21. The Sampled-Data Output Waveform
17
TL/H/10399– 32
18
Physical Dimensions inches (millimeters)
20-Lead Ceramic Dual-In-Line Package (J)
Order Number MF10AJ or MF10CCJ
NS Package Number J20A
Molded Package (Small Outline) (M)
Order Number MF10ACWM or MF10CCWM
NS Package Number M20B
19
Physical Dimensions inches (millimeters) (Continued)
20-Lead Molded Dual-In-Line Package (N)
Order Number MF10ACN or MF10CCN
NS Package Number N20A
MF10 Universal Monolithic Dual Switched Capacitor Filter
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
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Tel: 1(800) 272-9959 Deutsch Tel: (
Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
a
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