May 2007
LP5951
Micropower, 150mA Low-Dropout CMOS Voltage
Regulator
General Description
The LP5951 regulator is designed to meet the requirements
of portable, battery-powered systems providing a regulated
output voltage and low quiescent current. When switched to
shutdown mode via a logic signal at the Enable pin, the power
consumption is reduced to virtually zero.
The LP5951 is designed to be stable with small 1µF ceramic
capacitors.
The LP5951 also features internal protection against shortcircuit currents and over-temperature conditions.
Performance is specified for a -40°C to 125°C temperature
range.
The device is available in SOT23-5 and SC70-5 package.
The device is available in fixed output voltages in the range
of 1.3V to 3.3V. For availability, please contact your local NSC
sales office.
Features
■
Excellent line transient response: ±2mV typ.
■
Excellent PSRR: -60dB at 1kHz typ.
■
Low quiescent current of 29µA typ.
■
1.8 to 5.5V input voltage range
■
Small SC70-5 and SOT23-5 packages
■
Fast turn-on time of 30µs typ.
■
Typ. < 1nA quiescent current in shutdown
■
Guaranteed 150mA output current
■
Output voltage range: 1.3V to 3.3V
■
Logic controlled enable 0.4V/0.9V
■
Good load transient response of 50mVpp typ.
■
Thermal-overload and short-circuit protection
■
-40°C to +125°C junction temperature range
Applications
■
General purpose
Typical Application Circuit
20136201
© 2007 National Semiconductor Corporation 201362 www.national.com
LP5951 Micropower, 150mA Low-Dropout CMOS Voltage Regulator
Connection Diagrams
5-Lead Small Outline Package
SOT23-5 (MF)
20136202
Top View
See NS Package Number MF05A
5-Lead Small Outline Package
SC70-5 (MG)
20136203
Top View
See NS Package Number MAA05A
Pin Descriptions
Pin Number Pin Name Description
1 V
IN
Input Voltage. Input range: 1.8V to 5.5V
2 GND Ground
3 EN Enable pin logic input: Low = shutdown, High = normal operation. This pin should not be left floating.
4 NC No internal connection
5 V
OUT
Regulated output voltage
Order Information
For 5-Lead Small Outline Package SOT23-5 (MF)
Output Voltage
(V)
LP5951 Supplied as 1000 Units,
Tape and Reel
LP5951 Supplied as 3000 Units,
Tape and Reel
Flow Package
Marking
1.3
LP5951MF-1.3 LP5951MFX-1.3 LKRB
LP5951MF-1.3 LP5951MFX-1.3 NOPB LKRB
1.5
LP5951MF-1.5 LP5951MFX-1.5 LKAB
LP5951MF-1.5 LP5951MFX-1.5 NOPB LKAB
1.8
LP5951MF-1.8 LP5951MFX-1.8 LKBB
LP5951MF-1.8 LP5951MFX-1.8 NOPB LKBB
2.0
LP5951MF-2.0 LP5951MFX-2.0 LKCB
LP5951MF-2.0 LP5951MFX-2.0 NOPB LKCB
2.5
LP5951MF-2.5 LP5951MFX-2.5 LKEB
LP5951MF-2.5 LP5951MFX-2.5 NOPB LKEB
2.8
LP5951MF-2.8 LP5951MFX-2.8 LKFB
LP5951MF-2.8 LP5951MFX-2.8 NOPB LKFB
3.0
LP5951MF-3.0 LP5951MFX-3.0 LKGB
LP5951MF-3.0 LP5951MFX-3.0 NOPB LKGB
3.3
LP5951MF-3.3 LP5951MFX-3.3 LKHB
LP5951MF-3.3 LP5951MFX-3.3 NOPB LKHB
www.national.com 2
LP5951
For 5-Lead Small Outline Package SC70-5 (MG)
Output Voltage
(V)
LP5951 Supplied as 1000 Units,
Tape and Reel
LP5951 Supplied as 3000 Units,
Tape and Reel
Flow Package
Marking
1.3
LP5951MG-1.3 LP5951MGX-1.3 L23
LP5951MG-1.3 LP5951MGX-1.3 NOPB L23
1.5
LP5951MG-1.5 LP5951MGX-1.5 L2B
LP5951MG-1.5 LP5951MGX-1.5 NOPB L2B
1.8
LP5951MG-1.8 LP5951MGX-1.8 L3B
LP5951MG-1.8 LP5951MGX-1.8 NOPB L3B
2.0
LP5951MG-2.0 LP5951MGX-2.0 L4B
LP5951MG-2.0 LP5951MGX-2.0 NOPB L4B
2.5
LP5951MG-2.5 LP5951MGX-2.5 L5B
LP5951MG-2.5 LP5951MGX-2.5 NOPB L5B
2.8
LP5951MG-2.8 LP5951MGX-2.8 L6B
LP5951MG-2.8 LP5951MGX-2.8 NOPB L6B
3.0
LP5951MG-3.0 LP5951MGX-3.0 L7B
LP5951MG-3.0 LP5951MGX-3.0 NOPB L7B
3.3
LP5951MG-3.3 LP5951MGX-3.3 LAB
LP5951MG-3.3 LP5951MGX-3.3 NOPB LAB
Note:
The package marking on the backside of the component designates the date code and a NSC internal code for die traceability. It will vary considerably.
SOT23-5: ZWTT
SC70-5: WTT
with: Z: 1 Digit Assembly Plant Code, W: 1 Digit Date Code, TT: 2 Digit Dierun Code
3 www.national.com
LP5951
Absolute Maximum Ratings (Notes 2, 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN pin: Voltage to GND -0.3V to 6.5V
EN pin: Voltage to GND -0.3V to (VIN+0.3V)
with 6.5V max
Continuous Power Dissipation
(Note 3) Internally Limited
Junction Temperature (T
J-MAX
) 150°C
Storage Temperature Range -65°C to + 150°C
Package Peak Reflow Temperature
(10-20 sec.) 240°C
Package Peak Reflow Temperature
(Pb-free, 10-20 sec.) 260°C
ESD Rating(Note 4)
Human Body Model: 2.0kV
Machine Model 200V
Operating Ratings
(Notes 1, 2)
Input Voltage Range (VIN) 1.8V to 5.5V
VEN Input Voltage 0 to (VIN + 0.3V)
Junction Temperature (TJ) Range -40°C to + 125°C
Ambient Temperature (TA) Range (Note 5)
Thermal Properties
Junction-to-Ambient Thermal
Resistance (θJA), (Note 6)
SOT23-5 Package: 220°C/W
SC70-5 Package: 415°C/W
ESD Caution Notice
National Semiconductor recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper
ESD handling techniques can result in damage.
Electrical Characteristics (Notes 2, 7)
Typical values and limits appearing in standard typeface are for TA = 25°C. Limits appearing in boldface type apply over the full
operating temperature range: -40°C ≤ TJ ≤ +125°C. Unless otherwise noted, VIN = V
OUT(NOM)
+ 1V, CIN = 1µF, C
OUT
= 1µF, VEN =
0.9V.
Symbol Parameter Condition Typ Limit Units
Min Max
V
IN
Input Voltage
VIN ≥ V
OUT(NOM)
+ V
DO
1.8 5.5 V
ΔV
OUT
Output Voltage
Tolerance
I
OUT
= 1mA
-30°C ≤ TJ ≤ +125°C
-2.0
-3.5
2.0
3.5
%
%
Line Regulation Error VIN = V
OUT(NOM)
+ 1V to 5.5V
I
OUT
= 1mA
0.1 %/V
Load Regulation Error I
OUT
= 1mA to 150mA -0.01 %/mA
V
DO
Output Voltage Dropout
(Note 10)
I
OUT
= 150mA
V
OUT
≥ 2.5V
V
OUT
< 2.5V
200
250
350
mV
mV
I
Q
Quiescent Current VEN = 0.9V, I
LOAD
= 0
VEN = 0.9V, I
LOAD
= 150mA
VEN = 0V
29
33
0.005
55
70
1
µA
µA
µA
I
SC
Output Current
(short circuit)
VIN = V
OUT(NOM)
+ 1V 400 150 mA
PSRR Power Supply
Rejection Ratio
Sine modulated V
IN
f = 100Hz
f = 1kHz
f = 10kHz
60
60
50
dB
dB
dB
E
N
Output Noise BW = 10Hz - 100kHz 125 µV
RMS
TSD Thermal Shutdown 160 °C
Temperature Hysteresis 20 °C
www.national.com 4
LP5951
Enable Control Characteristics
Symbol Parameter Conditions Typical Limit Units
Min Max
I
EN
Maximum Input Current
at VEN Input
0V ≤ VEN ≤ VIN, VIN = 5.5V
-1 1 µA
V
IL
Low Input Threshold
(shutdown)
VIN = 1.8..5.5V 0.4 V
V
IH
High Input Threshold
(enable)
VIN = 1.8..5.5V 0.9 V
Transient Characteristics
Symbol Parameter Conditions Typical Limit Units
Min Max
ΔV
OUT
Dynamic Line
Transient
VIN = V
OUT(NOM)
+ 1V to
V
OUT(NOM)
+ 1V + 0.6V in 30µs, no load
±2 mV
ΔV
OUT
Dynamic Load
Transient
I
OUT
= 0mA to 150mA in 10µs
I
OUT
= 150mA to 0mA in 10µs
I
OUT
= 1mA to 150mA in 1µs
I
OUT
= 150mA to 1mA in 1µs
-30
20
-50
40
mV
mV
mV
mV
ΔV
OUT
Overshoot on Startup Nominal conditions 10 mV
T
ON
Turn on time I
OUT
= 1mA 30 µs
Output Capacitor, Recommended Specification
Symbol Parameter Conditions Value
Limit (Note 8)
Units
Min Max
C
OUT
Output Capacitance
Capacitance (Note 9)
I
OUT
= 150mA, VIN = 5.0V
1.0 0.7 47 µF
ESR 0.003 0.300
Ω
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and disengages at T
J
= 140°C (typ.).
Note 4: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin. (MIL-STD-883 3015.7)
Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
A-MAX
) is dependent on the maximum operating junction temperature (T
J-MAX-OP
= 125°C), the maximum power
dissipation of the device in the application (P
D-MAX
), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: T
A-MAX
= T
J-MAX-OP
– (θJA × P
D-MAX
).
Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special attention must be paid to thermal dissipation issues in board design.
Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8: Min and Max limits are guaranteed by design
Note 9: The capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered when selecting
a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application,
X5R, Y5V, and Z5U can also be used. The shown minimum limit represents real minimum capacitance, including all tolerances and must be maintained over
temperature and dc bias voltage (See capacitor section in Applications Hints)
Note 10: Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100mV below the nominal output voltage. This
specification does not apply for output voltages below 1.8V.
5 www.national.com
LP5951
Output Current Derating
Maximum Load Current vs VIN - V
OUT
, TA = 85°C, V
OUT
= 1.5V
20136204
Block Diagram
20136205
www.national.com 6
LP5951
Typical Performance Characteristics Unless otherwise specified, C
IN
= 1µF ceramic, C
OUT
= 1µF
ceramic, VIN = V
OUT(NOM)
+ 1V, TA = 25°C, Enable pin is tied to VIN.
Load Transient Response
20136209
Load Transient Response
20136210
Line Transient Response
20136211
Line Transient Response
20136212
Enable Start-up Time
20136213
Enable Start-up Time
20136214
7 www.national.com
LP5951
Output Voltage Change vs Temperature
20136217
Ground Current vs V
IN
20136216
Power Supply Rejection Ratio
20136215
www.national.com 8
LP5951
Application Hints
POWER DISSIPATION AND DEVICE OPERATION
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power
source, the junctions of the IC, to the ultimate heat sink, the
ambient environment. Thus the power dissipation is dependent on the ambient temperature and the thermal resistance
across the various interfaces between the die and ambient
air.
As stated in (Note 5) in the electrical specification section, the
allowable power dissipation for the device in a given package
can be calculated using the equation:
PD = (T
J(MAX)
- TA) / θ
JA
With a θJA = 220°C/W, the device in the SOT23-5 package
returns a value of 454 mW with a maximum junction temperature of 125°C at TA of 25°C.
The actual power dissipation across the device can be estimated by the following equation:
PD ≈ (VIN - V
OUT
) * I
OUT
This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage drop
across the device, and the continuous current capability of the
device. These two equations should be used to determine the
optimum operating conditions for the device in the application.
EXTERNAL CAPACITORS
As is common with most regulators, the LP5951 requires external capacitors to ensure stable operation. The LP5951 is
specifically designed for portable applications requiring minimum board space and the smallest size components. These
capacitors must be correctly selected for good performance.
INPUT CAPACITOR
An input capacitor is required for stability. It is recommended
that a 1.0µF capacitor be connected between the LP5951 input pin and ground (this capacitance value may be increased
without limit).
This capacitor must be located a distance of not more than 1
cm from the input pin and returned to a clean analogue
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series
Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the
capacitor to ensure the capacitance will remain ≥0.7µF over
the entire operating temperature range.
OUTPUT CAPACITOR
The LP5951 is designed specifically to work with very small
ceramic output capacitors. A ceramic capacitor (dielectric
types X7R, Z5U, or Y5V) in the 1.0µF range (up to 47µF) and
with ESR between 3 mΩ to 500 mΩ is suitable in the LP5951
application circuit.
This capacitor must be located a distance of not more than
1cm from the V
OUT
pin and returned to a clean analogue
ground.
It is also possible to use tantalum or film capacitors at the
device output, V
OUT
, but these are not as attractive for reasons of size and cost (see the section Capacitor Characteristics).
CAPACITOR CHARACTERISTICS
The LP5951 is designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer. For
capacitance values in the range of 1µF to 4.7µF, ceramic capacitors are the smallest, least expensive and have the lowest
ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1µF ceramic capacitor is
in the range of 3mΩ to 40mΩ, which easily meets the ESR
requirement for stability for the LP5951.
For both input and output capacitors, careful interpretation of
the capacitor specification is required to ensure correct device
operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type.
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance
can vary with DC bias conditions as well as temperature and
frequency of operation. Capacitor values will also show some
decrease over time due to aging. The capacitor parameters
are also dependant on the particular case size, with smaller
sizes giving poorer performance figures in general. As an example, Figure 1 shows a typical graph comparing different
capacitor case sizes in a Capacitance vs. DC Bias plot. As
shown in the graph, increasing the DC Bias condition can result in the capacitance value falling below the minimum value
given in the recommended capacitor specifications table
(0.7µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher
bias voltages. It is therefore recommended that the capacitor
manufacturers’ specifications for the nominal value capacitor
are consulted for all conditions, as some capacitor sizes (e.g.
0402) may not be suitable in the actual application.
20136206
FIGURE 1. Graph Showing A Typical Variation In
Capacitance vs DC Bias
9 www.national.com
LP5951
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of -55°C to +125°C, will only vary the capacitance
to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of -55°C to +85°C.
Many large value ceramic capacitors, larger than 1µF are
manufactured with Z5U or Y5V temperature characteristics.
Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient
temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
1µF to 4.7µF range.
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have
to be larger in capacitance (which means bigger and more
costly) than a ceramic capacitor with the same ESR value. It
should also be noted that the ESR of a typical tantalum will
increase about 2:1 as the temperature goes from 25°C down
to -40°C, so some guard band must be allowed.
NO-LOAD STABILITY
The LP5951 will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications.
ENABLE OPERATION
The LP5951 may be switched ON or OFF by a logic input at
the Enable pin, VEN. A logic high at this pin will turn the device
on. When the enable pin is low, the regulator output is off and
the device typically consumes 5nA.
If the application does not require the Enable switching feature, the VEN pin should be tied to VIN to keep the regulator
output permanently on.
To ensure proper operation, the signal source used to drive
the VEN input must be able to swing above and below the
specified turn-on/off voltage thresholds listed in the Electrical
Characteristics section under Enable Control Characteristics,
VIL and VIH.
FAST TURN OFF AND ON
The controlled switch-off feature of the device provides a fast
turn off by discharging the output capacitor via an internal FET
device. This discharge is current limited by the RDSon of this
switch.
Fast turn-on is guaranteed by an optimized architecture allowing a very fast ramp of the output voltage to reach the
target voltage.
SHORT-CIRCUIT PROTECTION
The LP5951 is short circuit protected and in the event of a
peak over-current condition, the output current through the
PMOS will be limited.
If the over-current condition exists for a longer time, the average power dissipation will increase depending on the input
to output voltage difference until the thermal shutdown circuitry will turn off the PMOS.
Please refer to the section on thermal information for power
dissipation calculations.
THERMAL-OVERLOAD PROTECTION
Thermal-Overload Protection limits the total power dissipation
in the LP5951. When the junction temperature exceeds TJ =
160°C typ., the shutdown logic is triggered and the PMOS is
turned off, allowing the device to cool down. After the junction
temperature dropped by 20°C (temperature hysteresis), the
PMOS is activated again. This results in a pulsed output voltage during continuous thermal-overload conditions.
The Thermal-Overload Protection is designed to protect the
LP5951 in the event of a fault condition. For normal, continuous operation, do not exceed the absolute maximum junction
temperature rating of TJ = +150°C (see Absolute Maximum
Ratings).
REVERSE CURRENT PATH
The internal PFET pass device in LP5951 has an inherent
parasitic body diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode
is reverse biased. However, if the output is pulled above the
input in an application, then current flows from the output to
the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the
parasitic diode is limited to 50mA.
For currents above this limit an external Schottky diode must
be connected from V
OUT
to VIN (cathode on VIN, anode on
V
OUT
).
EVALUATION BOARDS
For availability of evaluation boards please refer to the Product Folder of LP5951 at www.national.com. For information
regarding evaluation boards, please refer to Application Note:
AN-1486.
SUGGESTED CAPACITORS AND THEIR SUPPLIERS
Capacitance / µF Model Vendor Type Case Size / Inch (mm)
1.0 C1608X5R1A105K TDK Ceramic, X5R 0603 (1608)
1.0 C1005X5R1A105K TDK Ceramic, X5R 0402 (1005)
www.national.com 10
LP5951
Physical Dimensions inches (millimeters) unless otherwise noted
NS Package Number MF05A
5-Lead Small Outline Package SOT23-5 (MF),
NS Package Number MAA05A
5-Lead Small Outline Package SC70-5 (MG),
For most accurate revision please refer to www.national.com/packaging/parts/
11 www.national.com
LP5951
Notes
LP5951 Micropower, 150mA Low-Dropout CMOS Voltage Regulator
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2007 National Semiconductor Corporation
For the most current product information visit us at www.national.com
National Semiconductor
Americas Customer
Support Center
Email:
new.feedback@nsc.com
Tel: 1-800-272-9959
National Semiconductor Europe
Customer Support Center
Fax: +49 (0) 180-530-85-86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +49 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
National Semiconductor Asia
Pacific Customer Support Center
Email: ap.support@nsc.com
National Semiconductor Japan
Customer Support Center
Fax: 81-3-5639-7507
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com
Loading...