National Semiconductor LP5550 Technical data

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LP5550

LP5550 PowerWise

October 2005

PowerWise

™

Technology Compliant Energy

Management Unit

General Description

The LP5550 is a PWI 1.0 compliant Energy Management System for reducing power consumption of stand-alone mobile phone processors such as base-band or applications processors.

The LP5550 contains an advanced, digitally controlled switching regulator for supplying variable voltage to processor core and memory. The device also incorporates 3 programmable LDO-regulators for powering I/O, PLLs and maintaining memory retention in shutdown-mode.

The device is controlled via the PWI open-standard interface. The LP5550 operates cooperatively with PowerWise technology compatible processors to optimize supply voltages adaptively over process and temperature variations or dynamically using frequency/voltage pre-characterized look-up tables.

System Diagram

Features

n Supports high-efficiency PowerWise Technology

Adaptive Voltage Scaling

n PWI open standard interface for system power

management

n Digitally controlled intelligent voltage scaling n 1 MHz PWM switching frequency n Auto or PWI controlled PFM mode transition n Internal soft start/startup sequencing. n 3 programmable LDOs for I/O, PLL, and memory

retention supply generation.

n Power OK output.

Applications

n GSM/GPRS/EDGE & UMTS cellular handsets n Hand-held radios n PDAs n Battery powered devices n Portable instruments

™

Technology Compliant Energy Management Unit

20154563

FIGURE 1. System Diagram

Connection Diagrams and Package Mark Information

LP5550

NS Package Number SQA16A

16 - Pin LLP

FIGURE 2. LP5550 Pinout

20154502

Package Mark

20154546

Note: The actual physical placement of the package marking will vary from part to part.

FIGURE 3. Top View

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Typical Application

LP5550

20154530

FIGURE 4. Typical Application Circuit

Pin Descriptions

Pin # Name I/O Type Description

1 SCLK I D PowerWise Interface (PWI) clock input

2 SPWI I/O D PowerWise Interface (PWI) bi-directional data

3 RESETN I D Reset, active low

4 VO2 O A LDO2 output, for supplying the I/O voltage on the SoC

5 VBAT1 P P Battery supply voltage

6 VO1 O A LDO1 output, for supplying a fixed voltage to a PLL etc. on the SoC

7 DGND G G Digital ground

8 PWROK O D Power OK, active high output signal

9 VBATSW P P Battery supply voltage for switching regulator

10 SW O A Switcher pin connected to coil

11 SWGND G G Switcher ground

12 VBAT2 P P Battery supply voltage

13 VO3 O A LDO3 output, on-chip memory supply voltage

14 VFB I A Switcher output voltage for supplying SoC core logic

15 AGND G G Analog Ground

16 ENABLE I D Enable, active high

A: Analog Pin D: Digital Pin I: Input Pin O: Output Pin I/O: Input/Output Pin P: Power Pin G: Ground Pin

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Ordering Information

LP5550

Voltage Option Order Number Package Marking Supplied As

LP5550SQ LP5550SQ 1000 units, Tape-and-Reel

LP5550SQX LP5550SQ 4500 units, Tape-and-Reel

*Released. Samples available.

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LP5550

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

ESD Rating (Note 3)

Human Body Model:

SW pin 1.0kV

All other pins 2.0kV

VBAT1, VBAT2, VBATSW -0.3 to +6.0V

VO1, VO2, VO3 to GND -0.3 to +VBAT1+0.3V

Operating Ratings (Notes 1, 2)

ENABLE, RESETN, VFB, SW,

SPWI, SCLK, PWROK -0.3 to VBAT2+0.3V

DGND, AGND, SWGND to

0.3V

GND SLUG

VBAT1, VBAT2, VBATSW 3.0V to 5.5V

Junction Temperature (T

)

−40˚C to +125˚C

Range

Ambient Temperature (T

)

−40˚C to +85˚C

Range(Note 5)

Junction Temperature (TJ-MAX)

Storage Temperature Range -65˚C to 150˚C

Maximum Continuous Power Dissipation

150˚C

1.0 W

Thermal Properties(Note 6)

Junction-to-Ambient Thermal Resistance (θ

)

39.8˚C/W

(PD-MAX) (Note 3)

Maximum Lead

Note 4

Temperature (Soldering)

General Electrical Characteristics Unless otherwise noted, V

BAT1,2,SW

, RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8, 9)

Symbol Parameter Conditions Min Typ Max Units

Shutdown Supply current V

Sleep State Supply Current

load 1 mA)

Acitve State Supply Current (No load, PFM mode)

BAT1,2,SW

PWI on. All other circuits off.

BAT1,2,SW

Switcher on, PWI on.

= 2.0V, all circuits off. 1 6 µA

= 3.6V, LDO3 (VO3) on,

= 3.6V, LDOs 1 and 2 on,

70 85 µA

140 165 µA

Thermal Shutdown Threshold 160 ˚C

Thermal Shutdown Hysteresis 10

LDO1 (PLL/Fixed Voltage) Characteristics Unless otherwise noted, V

BAT1,2,SW

Symbol Parameter Conditions Min Typ Max Units

OUT

Accuracy

Range Programmable Output Voltage

OUT

∆V

OUT

Output Voltage 1mA ≤ IOUT ≤ 100mA,V

≤ 5.5V

≤ 100mA, Programming

Range

3.0V ≤ V

0µA ≤ I

BAT1,2,SW

OUT

Resolution=100mV

OUT

= 2V,

-3% 2 3% V

0.7 1.2 2.2 V

Recommended Output Current 3.0V ≤ VBAT1,2,SW ≤ 5.5V 100 mA

Short Circuit Current Limit V

Quiescent Current I

Line Regulation 3.0V ≤ V

=0V 350

OUT

= 0mA(Note 11) 35 45 µA

OUT

BAT1,2,SW

≤ 5.5V, I

OUT

-0.0125 0.0125 %/V

50mA

Load Regulation VIN= 3.6V, 1mA ≤ I

Line Transient Regulation 3.6V ≤ V

≤ 3.9V, TRISE,FALL = 10

≤ 100mA -0.0085 0.0085 %/mA

OUT

27 mV

µs

Load Transient Regulation VIN= 3.6V, 10mA ≤ I

OUT

≤ 90 mA,

86 mV

TRISE,FALL = 100 ns

eN Output Noise Voltage 10Hz ≤ f ≤ 100kHz,C

= 2.2µF 0.103 mVRMS

OUT

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LDO1 (PLL/Fixed Voltage) Characteristics Unless otherwise noted, V

ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type

LP5550

apply over the entire junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8) (Continued)

BAT1,2,SW

, RESETN,

Symbol Parameter Conditions Min Typ Max Units

PSRR Power Supply Ripple Rejection

Ratio

OUT

Output CapacitanceOutput Capacitor ESR

START-UP

Start-Up Time from Shut-down C

f = 1kHz,C

f = 10kHz,C

0µA ≤ I

OUT

= 1µF, I

OUT

= 2.2µF 56 dB

OUT

= 2.2µF 36 dB

OUT

≤ 100mA 1 2.2 20 µF

5 500 mΩ

= 100mA 54 µs

OUT

LDO2 (I/O Voltage) Characteristics Unless otherwise noted, V

BAT1,2,SW

Symbol Parameter Conditions Min Typ Max Units

OUT

Output Voltage 1mA ≤ I

Accuracy

Range Programmable Output Voltage

OUT

Range

OUT

0µA ≤ I

≤ 250mA,V

OUT

+0.4V ≤ V

OUT

BAT1,2,SW

≤ 250mA, 1.5-2.3V

OUT

= 3.3V,

≤ 5.5V

=100mV step, 2.5V, 2.8V, 3.0V and

-3% 3.3 3% V

1.5 3.3 3.3 V

3.3V

OUT

Recommended Output Current V

Output Current Limit V

Dropout Voltage(Note 10) I

∆V

OUT

Quiescent Current I

Line Regulation V

Load Regulation V

Line Transient Regulation 3.6V ≤ V

Load Transient Regulation V

eN Output Noise Voltage 10Hz ≤ f ≤ 100kHz,C

PSRR Power Supply Ripple Rejection

Ratio

OUT

Output Capacitance 0µA ≤ I

+0.4V ≤ V

OUT

=0V 740

OUT

= 125mA 70 260 mV

OUT

= 0mA (Note 11) 55 60 µA

OUT

+0.4V ≤ V

OUT

= 125mA

OUT

= 3.6V, 1mA ≤ I

= 3.6V, 25mA ≤ I

RISE,FALL

f = 1kHz, C

f = 10kHz, C

OUT

BAT1,2,SW

≤ 3.9V, T

= 100 ns

= 4.7µF 46 dB

OUT

= 4.7µF 34

OUT

≤ 250mA 2 4.7 20 µF

≤ 5.5V 250 mA

≤ 5.5V,

≤ 250mA -0.011 0.011 %/mA

OUT

RISE,FALL

OUT

=10us 24 mV

≤ 225 mA,

= 4.7µF 0.120 mVRMS

-0.0125 0.0125 %/V

246 mV

Output Capacitor ESR 5 500 mΩ

START-UP

Start-Up Time from Shut-down C

OUT

= 4.7µF, I

= 250mA 144 µs

OUT

LDO3 (Memory Retention Voltage) Characteristics Unless otherwise noted, V

BAT1,2,SW

RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8)

Symbol Parameter Conditions Min Typ Max Units

OUT

Accuracy

OFFSET

Range Programmable Output Voltage

OUT

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Output Voltage Active state: Tracking V

AVS

Sleep state: Memory retention voltage regulation

Active State Buffer offset (=

O3-VFB

)

Range (Sleep state)

≤ 50mA,VOUT = 1.2V, 3.0V ≤

OUT

BAT1,2,SW

OUT

BAT1,2,SW

OUT

0µA ≤ I

≤ 5.5V

≤ 5mA,V

≤ 5.5V

=50mA,

= 0.6 V

=50mA,

= 1.2V

≤ 5mA, Programming

OUT

Resolution=50mV

Quiescent Current Active mode, I

Sleep mode, I

-3% 1.2 3% V

= 1.2V, 3.0V ≤

OUT

-3% 1.2 3% V

13 mV

28 mV

0.6 1.2 1.35 V

= 10µA (Note 11) 33 44 µA

OUT

= 10µA (Note 11) 10 16 µA

OUT

LP5550

LDO3 (Memory Retention Voltage) Characteristics Unless otherwise noted, V

BAT1,2,SW

Symbol Parameter Conditions Min Typ Max Units

OUT

Recommended Output Current,

3.0V ≤ V

BAT1,2,SW

≤ 5.5V 50 mA

Active state

Recommended Output Current,

3.0V ≤ V

BAT1,2,SW

≤ 5.5V 5

Sleep state

Short Circuit Current Limit,

=0V 230

OUT

Active state

eN Output Voltage Noise 10Hz ≤ f ≤ 100kHz,C

PSRR Power Supply Ripple Rejection

f = 217Hz, C

= 1.0µF 36 dB

OUT

= 1µF 0.158 mVRMS

OUT

Ratio

COUT Output Capacitance 0µA ≤ I

≤ 5mA 0.7 1 2.2 µF

OUT

Output Capacitor ESR 5 500 mΩ

Switcher (Core Voltage) Characteristics Unless otherwise noted, V

BAT1,2,SW

Symbol Parameter Conditions Min Typ Max Units

BAT1,2,SW

1.53% 2.70% V

-0.44% 2.70%

0.6 1.2 1.2 V

0.0019 %/mA

0.18 %/V

OUT

Output Voltage I

Accuracy

Range Programmable Output Voltage

OUT

Range

∆V

OUT

Line regulation 3.0V<V

Load regulation V

DSON(P)

DSON(N)

LIM

OSC

OUT

Quiescent current consumption I

P-FET resistance V

N-FET resistance V

Switch peak current limit 3.0V<V

Internal oscillator frequency PWM-mode 800 1000 1360 kHz

Output Capacitance 0mA ≤ I

= 1 mA, V

OUT

BAT1,2,SW

OUT

5.5V

0mA ≤ I

= 1-300 mA, 3.0V<V

OUT

= 1.2V, 3.0V

OUT

5.5V

≤ 300mA, Programming

Resolution = 4.7mV

BAT1,2,SW

=10mA

OUT

BAT1,2,SW

OUT

BAT1,2,SW

= 3.6V

= 100-300mA

= 0mA 15 30 µA

= VGS = 3.6V 360 690 mΩ

= VGS = 3.6V 250 660 mΩ

BAT1,2,SW

≤ 300mA 5 10 22 µF

OUT

5.5V,

5.5V 400 620 750 mA

Output Capacitor ESR 5 500 mΩ

L Inductor inductance 0uA ≤ I

VFB

VFBpin resistance to ground 150 650 kΩ

≤ 300mA 4.7 / 10 µH

OUT

Logic and Control Inputs Unless otherwise noted, V

BAT1,2,SW

Symbol Parameter Conditions Min Typ Max Units

Input Low Level ENABLE, RESETN, SPWI, SCLK

3.0V ≤ V

Input High Level ENABLE, RESETN 3.0V ≤ V

BAT1

≤ 5.5V

BAT1

≤

2 V

0.2 V

5.5V

IH_PWI

Input High Level, PWI SPWI, SCLK, 1.5V ≤VO2≤ 3.3V VO2-0.2V V

Logic Input Current ENABLE, RESETN, 0V ≤ V

BAT1

≤

-5 5 µA

5.5V

IL_PWI

Logic Input Current, PWI SPWI, SCLK, 1.5V ≤ VO2≤ 3.3V -5 15 µA

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Logic and Control Inputs Unless otherwise noted, V

and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction

LP5550

temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8, 9) (Continued)

BAT1,2,SW

, RESETN, ENABLE = 3.6V. Typical values

Symbol Parameter Conditions Min Typ Max Units

PD_PWI

Pull-down resistance for PWI

0.5 1 2 MΩ

signals

EN_LOW

Minimum low pulse width to enter STARTUP state

ENABLE pulsed high - low - high from SHUTDOWN state

ENABLE pulsed high - low - high

100 µsec

from SLEEP or ACTIVE state

Logic and Control Outputs Unless otherwise noted, V

BAT1,2,SW

Symbol Parameter Conditions Min Typ Max Units

OH_PWI

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pin.

Note 3: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula P = (TJ – TA)/θ

, (1) where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance.

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150˚C (typ.) and disengages at TJ=140˚C (typ.).

Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (LLP) (AN-1187).

Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).

Note 6: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2x1 array of thermal vias. The ground plane on the board is 50mm x 50mm. Thickness of copper layers are 36µm/18µm/18µm/36µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22˚C, still air. Power dissipation is 1W.

The value of θ dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.

Note 7: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

Note 8: Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

Note 9: Guaranteed by design.

Note 10: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply

in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V

Note 11: Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference.

Output low level PWROK, SPWI, I

Output high level PWROK, I

Output high level, PWI SPWI, I

of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum power

SOURCE

≤ 1mA 0.4 V

SINK

≤ 1mA V

-0.4V V

BAT1

≤ 1mA VO2-0.4V V

), as given by the

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