The LP5550 is a PWI 1.0 compliant Energy Management
System for reducing power consumption of stand-alone mobile phone processors such as base-band or applications
processors.
The LP5550 contains an advanced, digitally controlled
switching regulator for supplying variable voltage to processor core and memory. The device also incorporates 3 programmable LDO-regulators for powering I/O, PLLs and
maintaining memory retention in shutdown-mode.
The device is controlled via the PWI open-standard interface. The LP5550 operates cooperatively with PowerWise
technology compatible processors to optimize supply voltages adaptively over process and temperature variations or
dynamically using frequency/voltage pre-characterized
look-up tables.
System Diagram
Features
n Supports high-efficiency PowerWise Technology
Adaptive Voltage Scaling
n PWI open standard interface for system power
management
n Digitally controlled intelligent voltage scaling
n 1 MHz PWM switching frequency
n Auto or PWI controlled PFM mode transition
n Internal soft start/startup sequencing.
n 3 programmable LDOs for I/O, PLL, and memory
retention supply generation.
n Power OK output.
Applications
n GSM/GPRS/EDGE & UMTS cellular handsets
n Hand-held radios
n PDAs
n Battery powered devices
n Portable instruments
Note: The actual physical placement of the package marking will vary from part to part.
FIGURE 3. Top View
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Typical Application
LP5550
20154530
FIGURE 4. Typical Application Circuit
Pin Descriptions
Pin #NameI/OTypeDescription
1SCLKIDPowerWise Interface (PWI) clock input
2SPWII/ODPowerWise Interface (PWI) bi-directional data
3RESETNIDReset, active low
4VO2OALDO2 output, for supplying the I/O voltage on the SoC
5VBAT1PPBattery supply voltage
6VO1OALDO1 output, for supplying a fixed voltage to a PLL etc. on the SoC
7DGNDGGDigital ground
8PWROKODPower OK, active high output signal
9VBATSWPPBattery supply voltage for switching regulator
10SWOASwitcher pin connected to coil
11SWGNDGGSwitcher ground
12VBAT2PPBattery supply voltage
13VO3OALDO3 output, on-chip memory supply voltage
14VFBIASwitcher output voltage for supplying SoC core logic
15AGNDGGAnalog Ground
16ENABLEIDEnable, active high
A: Analog Pin
D: Digital Pin
I: Input Pin
O: Output Pin
I/O: Input/Output Pin
P: Power Pin
G: Ground Pin
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Ordering Information
LP5550
Voltage OptionOrder NumberPackage MarkingSupplied As
LP5550SQLP5550SQ1000 units, Tape-and-Reel
LP5550SQXLP5550SQ4500 units, Tape-and-Reel
*Released. Samples available.
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LP5550
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Rating (Note 3)
Human Body Model:
SW pin1.0kV
All other pins2.0kV
VBAT1, VBAT2, VBATSW-0.3 to +6.0V
VO1, VO2, VO3 to GND-0.3 to +VBAT1+0.3V
Operating Ratings (Notes 1, 2)
ENABLE, RESETN, VFB,
SW,
SPWI, SCLK, PWROK-0.3 to VBAT2+0.3V
±
DGND, AGND, SWGND to
0.3V
GND SLUG
VBAT1, VBAT2, VBATSW3.0V to 5.5V
Junction Temperature (T
)
J
−40˚C to +125˚C
Range
Ambient Temperature (T
)
A
−40˚C to +85˚C
Range(Note 5)
Junction Temperature
(TJ-MAX)
Storage Temperature Range-65˚C to 150˚C
Maximum Continuous
Power Dissipation
150˚C
1.0 W
Thermal Properties(Note 6)
Junction-to-Ambient
Thermal Resistance (θ
)
JA
39.8˚C/W
(PD-MAX) (Note 3)
Maximum Lead
Note 4
Temperature (Soldering)
General Electrical Characteristics Unless otherwise noted, V
BAT1,2,SW
, RESETN, ENABLE = 3.6V.
Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire
junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8, 9)
SymbolParameterConditionsMinTypMaxUnits
I
Q
T
SD
Shutdown Supply currentV
Sleep State Supply Current
load 1 mA)
(V
O3
Acitve State Supply Current
(No load, PFM mode)
BAT1,2,SW
V
BAT1,2,SW
PWI on. All other circuits off.
V
BAT1,2,SW
Switcher on, PWI on.
= 2.0V, all circuits off.16µA
= 3.6V, LDO3 (VO3) on,
= 3.6V, LDOs 1 and 2 on,
7085µA
140165µA
Thermal Shutdown Threshold160˚C
Thermal Shutdown Hysteresis10
LDO1 (PLL/Fixed Voltage) Characteristics Unless otherwise noted, V
BAT1,2,SW
, RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply
over the entire junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8)
SymbolParameterConditionsMinTypMaxUnits
V
OUT
Accuracy
V
RangeProgrammable Output Voltage
OUT
I
OUT
I
Q
∆V
OUT
Output Voltage1mA ≤ IOUT ≤ 100mA,V
≤ 5.5V
≤ 100mA, Programming
Range
3.0V ≤ V
0µA ≤ I
BAT1,2,SW
OUT
Resolution=100mV
OUT
= 2V,
-3%23%V
0.71.22.2V
Recommended Output Current 3.0V ≤ VBAT1,2,SW ≤ 5.5V100mA
Short Circuit Current LimitV
Quiescent CurrentI
Line Regulation3.0V ≤ V
=0V350
OUT
= 0mA(Note 11)3545µA
OUT
BAT1,2,SW
≤ 5.5V, I
OUT
=
-0.01250.0125 %/V
50mA
Load RegulationVIN= 3.6V, 1mA ≤ I
Line Transient Regulation3.6V ≤ V
≤ 3.9V, TRISE,FALL = 10
IN
≤ 100mA-0.00850.0085 %/mA
OUT
27mV
µs
Load Transient RegulationVIN= 3.6V, 10mA ≤ I
OUT
≤ 90 mA,
86mV
TRISE,FALL = 100 ns
eNOutput Noise Voltage10Hz ≤ f ≤ 100kHz,C
= 2.2µF0.103mVRMS
OUT
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LDO1 (PLL/Fixed Voltage) Characteristics Unless otherwise noted, V
ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type
LP5550
apply over the entire junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8) (Continued)
BAT1,2,SW
, RESETN,
SymbolParameterConditionsMinTypMaxUnits
PSRRPower Supply Ripple Rejection
Ratio
C
OUT
Output CapacitanceOutput
Capacitor ESR
t
START-UP
Start-Up Time from Shut-down C
f = 1kHz,C
f = 10kHz,C
0µA ≤ I
OUT
= 1µF, I
OUT
= 2.2µF56dB
OUT
= 2.2µF36dB
OUT
≤ 100mA12.220µF
5500mΩ
= 100mA54µs
OUT
LDO2 (I/O Voltage) Characteristics Unless otherwise noted, V
BAT1,2,SW
, RESETN, ENABLE = 3.6V.
Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire
junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8)
SymbolParameterConditionsMinTypMaxUnits
V
OUT
Output Voltage1mA ≤ I
Accuracy
V
RangeProgrammable Output Voltage
OUT
Range
V
OUT
0µA ≤ I
≤ 250mA,V
OUT
+0.4V ≤ V
OUT
BAT1,2,SW
≤ 250mA, 1.5-2.3V
OUT
= 3.3V,
≤ 5.5V
=100mV step, 2.5V, 2.8V, 3.0V and
-3%3.33%V
1.53.33.3V
3.3V
I
OUT
Recommended Output Current V
Output Current LimitV
Dropout Voltage(Note 10)I
I
Q
∆V
OUT
Quiescent CurrentI
Line RegulationV
Load RegulationV
Line Transient Regulation3.6V ≤ V
Load Transient RegulationV
eNOutput Noise Voltage10Hz ≤ f ≤ 100kHz,C
PSRRPower Supply Ripple Rejection
Ratio
C
OUT
Output Capacitance0µA ≤ I
+0.4V ≤ V
OUT
=0V740
OUT
= 125mA70260mV
OUT
= 0mA (Note 11)5560µA
OUT
+0.4V ≤ V
OUT
= 125mA
I
OUT
= 3.6V, 1mA ≤ I
IN
= 3.6V, 25mA ≤ I
IN
T
RISE,FALL
f = 1kHz, C
f = 10kHz, C
OUT
BAT1,2,SW
BAT1,2,SW
≤ 3.9V, T
IN
= 100 ns
= 4.7µF46dB
OUT
= 4.7µF34
OUT
≤ 250mA24.720µF
≤ 5.5V250mA
≤ 5.5V,
≤ 250mA-0.0110.011 %/mA
OUT
RISE,FALL
OUT
OUT
=10us24mV
≤ 225 mA,
= 4.7µF0.120mVRMS
-0.01250.0125 %/V
246mV
Output Capacitor ESR5500mΩ
t
START-UP
Start-Up Time from Shut-down C
OUT
= 4.7µF, I
= 250mA144µs
OUT
LDO3 (Memory Retention Voltage) Characteristics Unless otherwise noted, V
BAT1,2,SW
RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8)
SymbolParameterConditionsMinTypMax Units
V
OUT
Accuracy
V
OFFSET
V
RangeProgrammable Output Voltage
OUT
I
Q
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Output Voltage Active state:
Tracking V
AVS
Sleep state: Memory retention
voltage regulation
Active State Buffer offset (=
O3-VFB
)
V
Range (Sleep state)
I
≤ 50mA,VOUT = 1.2V, 3.0V ≤
OUT
V
BAT1,2,SW
I
OUT
V
BAT1,2,SW
I
OUT
V
OUT
I
OUT
V
OUT
0µA ≤ I
≤ 5.5V
≤ 5mA,V
≤ 5.5V
=50mA,
= 0.6 V
=50mA,
= 1.2V
≤ 5mA, Programming
OUT
Resolution=50mV
Quiescent CurrentActive mode, I
Sleep mode, I
-3%1.23%V
= 1.2V, 3.0V ≤
OUT
-3%1.23%V
13mV
28mV
0.61.21.35 V
= 10µA (Note 11)3344µA
OUT
= 10µA (Note 11)1016µA
OUT
,
LP5550
LDO3 (Memory Retention Voltage) Characteristics Unless otherwise noted, V
BAT1,2,SW
,
RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8) (Continued)
SymbolParameterConditionsMinTypMax Units
I
OUT
Recommended Output Current,
3.0V ≤ V
BAT1,2,SW
≤ 5.5V50mA
Active state
Recommended Output Current,
3.0V ≤ V
BAT1,2,SW
≤ 5.5V5
Sleep state
Short Circuit Current Limit,
V
=0V230
OUT
Active state
eNOutput Voltage Noise10Hz ≤ f ≤ 100kHz,C
PSRRPower Supply Ripple Rejection
f = 217Hz, C
= 1.0µF36dB
OUT
= 1µF0.158mVRMS
OUT
Ratio
COUTOutput Capacitance0µA ≤ I
≤ 5mA0.712.2µF
OUT
Output Capacitor ESR5500mΩ
Switcher (Core Voltage) Characteristics Unless otherwise noted, V
BAT1,2,SW
, RESETN, ENABLE
= 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over
the entire junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8)
Logic and Control Inputs Unless otherwise noted, V
BAT1,2,SW
, RESETN, ENABLE = 3.6V. Typical values
and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8, 9)
SymbolParameterConditionsMinTypMaxUnits
V
IL
V
IH
Input Low LevelENABLE, RESETN, SPWI, SCLK
3.0V ≤ V
Input High LevelENABLE, RESETN 3.0V ≤ V
BAT1
≤ 5.5V
BAT1
≤
2V
0.2V
5.5V
V
IH_PWI
I
IL
Input High Level, PWISPWI, SCLK, 1.5V ≤VO2≤ 3.3VVO2-0.2VV
Logic and Control Inputs Unless otherwise noted, V
and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction
LP5550
temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8, 9) (Continued)
BAT1,2,SW
, RESETN, ENABLE = 3.6V. Typical values
SymbolParameterConditionsMinTypMaxUnits
R
PD_PWI
Pull-down resistance for PWI
0.512MΩ
signals
T
EN_LOW
Minimum low pulse width to
enter STARTUP state
ENABLE pulsed high - low - high
from SHUTDOWN state
ENABLE pulsed high - low - high
100µsec
4
from SLEEP or ACTIVE state
Logic and Control Outputs Unless otherwise noted, V
BAT1,2,SW
, RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, -40 to +125˚C. (Notes 2, 7, 8, 9)
SymbolParameterConditionsMinTypMaxUnits
V
OL
V
OH
V
OH_PWI
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula P = (TJ
– TA)/θ
, (1) where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance.
JA
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care
must be paid to thermal dissipation issues in board design.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150˚C (typ.) and disengages at TJ=140˚C (typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (LLP)
(AN-1187).
Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ
following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).
Note 6: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC
standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2x1 array of thermal vias. The ground plane on the board
is 50mm x 50mm. Thickness of copper layers are 36µm/18µm/18µm/36µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22˚C, still air. Power
dissipation is 1W.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care
must be paid to thermal dissipation issues in board design.
The value of θ
dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application
Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
Note 7: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production
with TJ = 25C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process
control.
Note 8: Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics
Note 9: Guaranteed by design.
Note 10: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply
in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for
devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V
Note 11: Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference.
Output low levelPWROK, SPWI, I
Output high levelPWROK, I
Output high level, PWISPWI, I
of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum power
JA
SOURCE
SOURCE
≤ 1mA0.4V
SINK
≤ 1mAV
-0.4VV
BAT1
≤ 1mAVO2-0.4VV
), as given by the
JA
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