National Semiconductor LP3950 Technical data

LP3950 Color LED Driver with Audio Synchronizer

February 2005

General Description

The LP3950 is a color LED driver with a built-in audio synchronization feature for any analog audio input such as polyphonic ring tones and MP3 music. LEDs can be synchronized to an audio signal with two methods - amplitude and frequency. Also several fine tuning options are available for differentiation purposes. The chip also has an unique AGC (Automatic Gain Control) feature which tracks the input signal level and automatically adjusts the gain to an optimal value.

The LP3950 has a high efficiency magnetic DC/DC converter with programmable output voltage and switching frequency. The converter has high output current capability so it is also able to drive flash LEDs in camera phone applications.

The LP3950 is similar to LP3933 and LP3936 in that the color LEDs (or RGB LEDs) can also be programmed to generate light patterns (programmable color, intensity, on/off timing, slope and blinking cycle).

All functions are software controllable through a SPI or I compatible interface but the device also supports one pin control for enabling predefined (default) audio synchronization mode.

Typical Application

Features

n Audio synchronization for color LEDs with two modes:

Amplitude and Frequency

n Programmable frequency and amplitude response with

tracking speed control

n Automatic gain control or selectable gain for input signal

optimization

n RGB pattern generator similar to LP3933/LP3936 n Magnetic DC-DC boost converter with programmable

boost output voltage

n Selectable SPI or I n One pin default enable for non-serial interface users.

One pin selector for synchronization mode

n Space efficient 32-pin thin CSP laminate package

C compatible interface

Applications

n Cellular phones n MP3/CD/minidisc players n Toys

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Connection Diagrams and Package Mark Information

LP3950

32-Lead Thin CSP Package, 4.5 x 5.5 x 0.8 mm, 0.5 mm Pitch

See NS Package Number SLD32A

Top View

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Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” designates the date code. “UZ” and “TT” are NSC internal codes for die manufacturing and assembly traceability. Both will vary considerably.

Bottom View

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Package Mark — Top View

Ordering Information

Order Number Package Marking Supplied As

LP3950SL LP3950SL 1000 units, Tape-and-Reel

LP3950SLX LP3950SL 2500 units, Tape-and-Reel

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Pin Description

Pin # Name Type Description

1 FB Input Boost converter feedback.

2 GND_BOOST Ground Power switch ground.

3 SW Output Open drain, boost converter power switch.

DD2

5 GND2 Ground Ground return for V

6 DME Logic Input Default mode enable (internal pull down 1 MΩ).

7 AMODE Logic Input Audio mode selection (internal pull down 1 MΩ).

DDA

9 ASE Input Analog audio input, single-ended.

10 AD1 Input Analog audio input, differential.

11 AD2 Input Analog audio input, differential.

12 GNDA Ground Ground for analog audio inputs.

13 RT Input Oscillator resistor.

14 V

DD1

15 GND1 Ground Ground.

16 V

REF

17 GND3 Ground Ground.

18 NRST Logic Input Low active reset input.

19 SS/SDA Logic I/O SPI slave select/ I

20 SO Logic Output SPI serial data output.

21 SI Logic Input SPI serial data input.

22 SCK/SCL Logic Input SPI/ I

23 PWM_LED Logic Input Direct PWM control for LEDs.

24 V

DDIO

25 IF_SEL Logic Input SPI/I

26 B2 Output Open drain output, blue LED2.

27 G2 Output Open drain output, green LED2.

28 R2 Output Open drain output, red LED2.

29 GND_RGB Ground RGB driver ground.

30 R1 Output Open drain output, red LED1.

31 G1 Output Open drain output, green LED1.

32 B1 Output Open drain output, blue LED1.

Power Supply voltage for internal digital circuits.

(internal digital).

DD2

Power Supply voltage for audio circuits.

Power Supply voltage for internal analog circuits.

Output Internal reference bypass capacitor.

C data line.

C clock.

Power Supply voltage for logic IO signals.

C select (IF_SEL=1inSPImode).

LP3950

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Absolute Maximum Ratings (Notes 1,

LP3950

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Maximum Lead Temperature 260˚C

(Reflow soldering, 3 times) (Note 7)

ESD Rating (Note 8)

Human Body Model: 2 kV

Machine Model: 200V

V (SW, FB, R1–2, G1–2, B1–2)

(Notes 3, 4) −0.3V to +7.2V

DD1,VDD2,VDDIO,VDDA

−0.3V to +6.0V

Voltage on ASE, AD1, AD2 −0.3V to

+0.3V with 6.0V max

DD1

Voltage on Logic Pins −0.3V to V

DD_IO

+0.3V with 6.0V max

I (R1, G1, B1, R2, G2, B2)

150 mA

(Note 5)

I(V

)10µA

REF

Continuous Power Dissipation

Internally Limited

Operating Ratings (Notes 1, 2)

V (SW, FB, R1–2, G1– 2, B1–2) 0V to 6.0V

DD1,VDD2,VDDA

DDIO

Voltage on ASE, AD1, AD2 0.1V to V

Recommended Load Current 0 mA to 300 mA

Junction Temperature (T

Ambient Temperature (T

(Note 9) −40˚C to +85˚C

(Note 4) 2.7V to 2.9V

1.65V to V

) Range −40˚C to +125˚C

) Range

(Note 6)

Junction Temperature (T

Storage Temperature Range −65˚C to +150˚C

) 125˚C

J-MAX

Thermal Properties

Junction-to-Ambient Thermal Resistance 72˚C/W

(θ

), SLD32A Package (Note 10)

Electrical Characteristics (Notes 2, 11)

Limits in standard typeface are for TJ= +25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ T C

VDD2=CVDDA=CVDDIO

≤ +85˚C). Unless otherwise noted, specifications apply to Figure 1 with: V

= 100 nF, C

OUT=CIN

= 10 µF, C

= 100 nF, L1= 4.7 µH and f

VREF

DD1=VDD2=VDDA

BOOST

Symbol Parameter Condition Min Typ Max Units

VDD

VDDIO

VDDA

Standby Supply Current (V

DD1+VDD2+VDDA

current)

No-Load Supply Current (V

DD1+VDD2+VDDA

current, boost

off)

Full Load Supply Current (V

DD1+VDD2+VDDA

current, boost on) (Note 13)

Supply Current 1.0 MHz SCK Frequency

DDIO

Audio Circuitry Supply Current

NSTBY = L (register) SCK, SS, SI, NRST = H

NSTBY = H (reg.) EN_BOOST = L (reg.) SCK, SS, SI, NRST = H

NSTBY = H (reg.) EN_BOOST = H (reg.) SCK, SS, SI, NRST = H All Outputs Active

=50pFatSOPin

INPUT_SEL = [10] (register) 550 µA

(Note 14)

REF

Reference Voltage(Note 15) I

≤ 1.0 nA Only for Test

REF

1.230 V

Purpose

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pins (GND1–3, GND_BOOST, GND_RGB, GNDA).

Note 3: Battery/Charger voltage should be above 6.0V no more than 10% of the operational lifetime.

Note 4: Voltage tolerance of LP3950 above 6.0V relies on fact that V

not available (ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device. Also, V at the same electric potential.

Note 5: The total load current of the boost converter should be limited to 300 mA.

Note 6: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T

140˚C (typ.).

Note 7: For detailed package and soldering specifications and information, please refer to National Semiconductor Application Note 1125: Laminate CSP/FBGA.

Note 8: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged

directly into each pin. MIL-STD-883 3015.7

DD1,VDD2

and V

(2.8V) are available (ON) at all conditions. If V

DDA

= 160˚C (typ.) and disengages at TJ=

= 2.8V, C

= 2.0 MHz (Note 12).

1 5 µA

300 400 µA

850 µA

20 µA

DD1,VDD2

and V

DD1

VDD1

and V

DDA

DD1,2

- 0.1V

DDA

must be

are

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Electrical Characteristics (Notes 2, 11) (Continued)

Note 9: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (T dissipation of the device in the application (P following equation: T

Note 10: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

Note 11: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 12: Low-ESR Surface-Mount Ceramic Capacitors are used in setting electrical characteristics.

Note 13: Audio block inactive.

Note 14: In single-ended and in differential mode one audio buffer only is active and I

Note 15: V

A-MAX=TJ-MAX-OP

pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between V

REF

) is dependent on the maximum operating junction temperature (T

A-MAX

), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the

D-MAX

−(θJAxP

D-MAX

will be reduced by 90 µA (typ).

VDDA

= 125˚C), the maximum power

J-MAX-OP

and GND1.

REF

LP3950

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LP3950

Block Diagram

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FIGURE 1. LP3950 Block Diagram

Modes of Operation

RESET: In the RESET mode all the internal registers are reset to the default values. RESET is entered always if

input NRST is LOW or internal Power On Reset is active.

STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW and RESET is not active. This is the low

power consumption mode, when all the circuit functions are disabled. Registers can be written in this mode and the control bits are effective immediately after start up.

STARTUP: INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (V

ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine. Thermal shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal shutdown event is present.

BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the boost output is

raised in PFM mode during the 10 ms delay generated by the state-machine. All RGB outputs are off during the 10 ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH.

NORMAL: During the NORMAL mode the user controls the chip using the control registers. Registers can be written

in any sequence and any number of bits can be altered in a register within one write cycle . If the default mode is selected, default control register values are used.

, oscillator, etc.). To

REF

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Modes of Operation (Continued)

LP3950

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Logic Interface Characteristics

(1.80V ≤ V ambient temperature range (−40˚C ≤ T

Symbol Parameter Conditions Min Typ Max Units

LOGIC INPUTS SS, SI, SCK/SCL, PWM_LED, IF_SEL

SCL

LOGIC OUTPUT SO

LOGIC I/O SDA

LOGIC INPUTS DME, AMODE (Internal pull down 1 MΩ)

DDIO

≤ V

V). Limits in standard typeface are for TJ= +25˚C. Limits in boldface type apply over the operating

DD1,2

≤ +85˚C).

Input Low Level 0.5 V

Input High Level V

− 0.5 V

DDIO

Logic Input Current −1.0 1.0 µA

Clock Frequency I2C Mode 400 kHz

SPI Mode 8 MHz

Output Low Level ISO= 3.0 mA 0.3 0.5 V

Output High Level ISO= −3.0 mA V

− 0.5 V

DDIO

− 0.3 V

DDIO

Output Leakage Current VSO= 2.8V 1.0 µA

Output Low Level I

= 3.0 mA 0.3 0.5 V

SDA

Input Low Level 0.5 V

Input High Level V

− 0.5 V

DDIO

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Logic Interface Characteristics (Continued)

(1.80V ≤ V

LP3950

ambient temperature range (−40˚C ≤ T

Symbol Parameter Conditions Min Typ Max Units

LOGIC INPUTS DME, AMODE (Internal pull down 1 MΩ)

DDIO

≤ V

V). Limits in standard typeface are for TJ= +25˚C. Limits in boldface type apply over the operating

DD1,2

≤ +85˚C).

Logic Input Current −1.0 6.0 µA

Logic Interface Characteristics, Low I/O Voltage

(1.65V ≤ V

Symbol Parameter Conditions Min Typ Max Units

LOGIC INPUTS SCL, PWM_LED, IF_SEL

SCL

LOGIC I/O SDA

LOGIC INPUTS DME, AMODE (Internal pull down 1 MΩ)

1.80V) . I2C compatible interface only.

DDIO

Input Low Level 0.35 V

Input High Level V

− 0.35 V

DDIO

Logic Input Current −1.0 1.0 µA

Clock Frequency I2C Mode 200 kHz

Output Low Level I

= 3.0 mA 0.3 0.5 V

SDA

Input Low Level 0.35 V

Input High Level V

− 0.35 V

DDIO

Logic Input Current −1.0 6.0 µA

Logic Input NRST Characteristics

(1.65V ≤ V

Symbol Parameter Conditions Min Typ Max Units

NRST

DDIO

≤ V

DD1,2

V).

Input Low Level 0.5 V

Input High Level 1.3 V

Logic Input Current −1.0 1.0 µA

Reset Pulse Width Note: Guaranteed by

design

10 µs

Control Interface

The LP3950 supports three different interface modes:

1) SPI interface (4 wire, serial)

2) I

C compatible interface (2 wire, serial)

3) Direct enable (2 wire, enable lines)

IF_SEL Interface Pin Configuration Comment

HIGH SPI SCK

SI SO SS

LOW I

C Compatible SCL

SDA SI SO

(clock) (data in) (data out) (chip select)

(clock) (data in/out)

address)

(I (NC)

User can define the serial interface by the IF_SEL pin. The following table shows the pin configuration for both interface modes. Note that the pin configurations will be based on the status of the IF_SEL pin.

Use pull up resistor for SCL. Use pull up resistor for SDA. SI HIGH→address is 51’h; SI LOW→address is 50’h; Unused pin SO can be left unconnected.

SPI Interface

The transmission consists of 16-bit write and read cycles. One cycle consists of seven address bits, one read/write (R/W) bit and eight data bits. R/W bit high state defines a write cycle and low defines a read cycle. SO output is normally in high-impedance state and it is active only during

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when data is sent out during a read cycle. A pull-up or pull-down resistor may be needed for SO line if a floating logic signal can cause unintended current consumption in the circuitry.

The address and data are transmitted Most Significant Byte (MSB) first. The Slave Select signal (SS) must be low during the cycle transmission. SS resets the interface when high

SPI Interface (Continued)

and it has to be taken high between successive cycles. Data

FIGURE 2. SPI Write Cycle

LP3950

is clocked in on the rising edge of the SCK clock signal, while data is clocked out on the falling edge of SCK.

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FIGURE 3. SPI Read Cycle

FIGURE 4. SPI Timing Diagram

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LP3950

SPI Timing Parameters

DD1=VDD2=VDDA

Symbol Parameter

= 2.70V to 2.90V, V

= 1.80V to V

DDIO

DD1,2

Min Max

Limit

1 Cycle Time 80 ns

2 Enable Lead Time 40 ns

3 Enable Lag Time 40 ns

4 Clock Low Time 40 ns

5 Clock High Time 40 ns

6 Data Setup Time 0 ns

7 Data Hold Time 20 ns

8 Data Access Time 27 ns

9 Output Disable Time 27 ns

10 Output Data Valid 37 ns

11 Output Data Hold Time 0 ns

12 SS Inactive Time 15 ns

Note: Data guaranteed by design.

Units

I2C Compatible Interface

I2C SIGNALS

C compatible mode, the LP3950 pin SCL is used for the

In I

C clock and the SDA pin is used for the I2C data. Both

I these signals need a pull-up resistor according to I fication. The values of the pull-up resistors are determined

by the capacitance of the bus (typ. specifications are shown in Table I

1.8k). Signal timing

C Timing Parameters .

Unused pin SO can be left unconnected and pin SI must be

C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of

C session. START condition is defined as SDA signal

the I transition from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transition from LOW to HIGH while SCL is HIGH. The I

C master always generates

C speci-

FIGURE 5. I2C Signals: Data Validity

connected to V rate is 400 kbit/s (V interface can be used down to 1.65 V

or GND (address selector). Maximum bit

DDIO

1.80V to V

V). I2C compatible

DD1,2

with maximum bit

DDIO

rate of 200 kbit/s.

C DATA VALIDITY

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW.

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START and STOP bits. The I after START condition and free after STOP condition. During data transmission, the I

C bus is considered to be busy

C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.

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