June 2006
LP3879
Micropower 800mA Low Noise "Ceramic Stable" Voltage
Regulator for Low Voltage Applications
LP3879 Micropower 800mA Low Noise "Ceramic Stable" Voltage Regulator for Low Voltage
Applications
General Description
The LP3879 is a 800 mA fixed-output voltage regulator
designed to provide high performance and low noise in
applications requiring output voltages between 1.0V and
1.2V.
™
Using an optimized VIP
cess, the LP3879 delivers superior performance:
Ground Pin Current: Typically 5.5 mA
200 µA
Low Power Shutdown: The LP3879 draws less than 10 µA
quiescent current when shutdown pin is pulled low.
Precision Output: Guaranteed output voltage accuracy is
1% at room temperature.
Low Noise: Broadband output noise is only 18 µV (typical)
with 10 nF bypass capacitor.
@
100 µA load.
(Vertically Integrated PNP) pro-
@
800 mA load, and
Basic Application Circuit
Features
n Standard output voltage: 1.00V, 1.20V
n Custom voltages available from 1.0V to 1.2V (50 mV
increments)
n Input voltage: 2.5 to 6V
n 1% initial output accuracy
n Designed for use with low ESR ceramic capacitors
n Very low output noise
n Sense option improves load regulation
n 8 Lead PSOP and LLP surface mount packages
<
n
10 µA quiescent current in shutdown
n Low ground pin current at all loads
n High peak current capability
n Over-temperature/over-current protection
n -40˚C to +125˚C junction temperature range
Applications
n ASIC Power Supplies In:
- Desktops, Notebooks and Graphic Cards
- Set Top Boxes, Printers and Copiers
n DSP and FPGA Power Supplies
n SMPS Post-Regulator
n Medical Instrumentation
*Capacitance values shown are minimum required to assure stability. Larger output capacitor provides improved dynamic response. Output capacitor must
meet ESR requirements (see Application Information).
**The Shutdown pin must be actively terminated (see Application Information). Tie to INPUT (Pin 4) if not used.
VIP™is a trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation DS201613 www.national.com
20161303
Connection Diagrams
LP3879
8 Lead PSOP Package (MRA) 8 Lead LLP Surface Mount Package (SD)
Top View
See NS Package Number MRA08A
20161330
Top View
See NS Package Number SDC08A
Ordering Information
TABLE 1. Package Marking and Ordering Information
Output Voltage Grade Order Information Supplied as:
1.00 STD LP3879MR-1.0 95 Units per Rail
1.00 STD LP3879MRX-1.0 2500 Units on Tape and Reel
1.00 STD LP3879SD-1.0 1000 Units on Tape and Reel
1.00 STD LP3879SDX-1.0 4500 Units on Tape and Reel
1.20 STD LP3879MR-1.2 95 Units per Rail
1.20 STD LP3879MRX-1.2 2500 Units on Tape and Reel
1.20 STD LP3879SD-1.2 1000 Units on Tape and Reel
1.20 STD LP3879SDX-1.2 4500 Units on Tape and Reel
Pin Descriptions
Pin Name Function
1 BYPASS The capacitor connected between BYPASS and GROUND lowers
output noise voltage level and is required for loop stability.
2 N/C DO NOT CONNECT. This pin is used for post package test and must
be left floating.
3 GROUND Device ground.
4 INPUT Input source voltage.
5 OUTPUT Regulated output voltage.
6 SENSE Remote Sense. Tie directly to output or remotely at point of load for
best regulation.
7 N/C No internal connection.
8 SHUTDOWN Output is enabled above turn-on threshold voltage. Pull down to turn off
regulator output.
PSOP, LLP
DAP
SUBSTRATE
GROUND
The exposed die attach pad should be connected to a thermal pad at
ground potential. For additional information on using National
Semiconductor’s Non Pull Back LLP package, please refer to LLP
application note AN-1187
20161350
www.national.com 2
LP3879
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range −65˚C to +150˚C
Operating Junction Temperature
Range -40˚C to +125˚C
Lead Temperature (Soldering, 5
seconds) 260˚C
ESD Rating (Note 2) 2 kV
Power Dissipation (Note 3) Internally Limited
Input Supply Voltage (Survival) −0.3V to +16V
Input Supply Voltage (Typical
Operating) 2.5V to +6V
SENSE Pin −0.3V to +6V
Output Voltage (Survival) (Note 4) −0.3V to +6V
I
(Survival) Short Circuit
OUT
Protected
Input-Output Voltage (Survival)
(Note 5) −0.3V to +16V
Shutdown Pin 1kV
Electrical Characteristics
Limits in standard typeface are for TJ= 25˚C, and limits in boldface type apply over the temperature range of -40˚C to 125˚C.
Limits are guaranteed through design, testing, or correlation. The limits are used to calculate National’s Average Outgoing
Quality Level (AOQL). Unless otherwise specified: V
BYPASS
=10nF.
C
= 3.0V, V
IN
Symbol Parameter Conditions
V
O
Output Voltage
Tolerance
Output Voltage Line
1mA≤ IL≤ 800 mA
3.0V ≤ V
≤ 6V
IN
3.0V ≤ VIN≤ 6V
Regulation
= 800 mA
I
L
≥ V
V
OUT
Minimum Input
V
(min)
IN
Voltage Required
To Maintain Output
Regulation
I
GND
I
(PK) Peak Output
O
Ground Pin Current IL= 100 µA
I
L
V
0 ≤ T
I
L
V
I
L
I
L
V
= 800 mA
≥ V
OUT
≤ 125˚C
J
= 750 mA
≥ V
OUT
= 200 mA
= 800 mA
≥ V
OUT
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT(NOM)
Current
IO(MAX) Short Circuit
RL= 0 (Steady State)
Current
e
n
Output Noise
Voltage (RMS)
BW = 100 Hz to 100 kHz
BYPASS
=10nF
C
Ripple Rejection f=1kHz
-1%
-1%
-1%
−5%
= 1V, IL= 1 mA, C
OUT
Min
(Note 6)
-1.0 1.00 1.0
-2.0
-3.0
= 10 µF, CIN= 4.7 µF, V
OUT
Typical
(Note 7)
1.00
Max
(Note 6)
2.0
3.0
0.014
0.007
0.032
2.5 3.1
2.5 2.8
2.5 3.0
200
1.5
5.5
250
275
2
3.3
8.5
15
1200
1400
18 µV(RMS)
60 dB
S/D
= 2V,
Units
%V
%/V
V
µA
mA
mA
nom
www.national.com3
Electrical Characteristics (Continued)
Limits in standard typeface are for TJ= 25˚C, and limits in boldface type apply over the temperature range of -40˚C to 125˚C.
LP3879
Limits are guaranteed through design, testing, or correlation. The limits are used to calculate National’s Average Outgoing
Quality Level (AOQL). Unless otherwise specified: V
BYPASS
=10nF.
C
= 3.0V, V
IN
Symbol Parameter Conditions
SHUTDOWN INPUT
V
S/D
I
S/D
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the
device outside of its rated operating conditions.
Note 2: ESD testing was performed using Human Body Model, a 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T
and the ambient temperature, T
S/D Input Voltage VH= Output ON 1.4 1.6
V
= Output OFF
L
≤ 10 µA
I
IN
V
≤ 10 mV
OUT
≤ 50 µA
I
IN
S/D Input Current V
. The maximum allowable power dissipation at any ambient temperature is calculated using:
A
= 0 0.02 −1
S/D
V
=5V 5 15
S/D
= 1V, IL= 1 mA, C
OUT
Min
(Note 6)
= 10 µF, CIN= 4.7 µF, V
OUT
Typical
(Note 7)
Max
(Note 6)
0.1 0.50
0.6
(MAX), the junction-to-ambient thermal resistance, θ
J
S/D
= 2V,
Units
V
µA
J−A
,
The value of θ
vias. If a four layer board is used with maximum vias from the IC center to the heat dissipating copper layers, values of θ
60˚C/W for the PSOP-8 and 40˚C/W for the LLP-8 package. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown.
Note 4: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP3879 output must be diode-clamped to ground.
Note 5: The output PNP structure contains a diode between the V
on this diode and may induce a latch-up mode which can damage the part (see Application Hints).
Note 6: Limits are guaranteed through testing, statistical correlation, or design.
Note 7: Typical numbers reperesent the most likely norm for 25˚C operation.
for the LLP (SD) and PSOP (MRA) packages are specifically dependent on PCB trace area, trace material, and the number of layers and thermal
J−A
IN
and V
terminals that is normally reverse-biased. Forcing the output above the input will turn
OUT
which can be obtained are approximately
J−A
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LP3879
Typical Performance Characteristics Unless otherwise specified: V
= 4.7 µF, C
C
IN
OUT
I
= 10 µF, V
vs Temperature Minimum VINOver Temperature
GND
I
GND
S/D
vs I
= 2V, C
Load
= 10 nF, TJ= 25˚C.
BYP
20161320
V
OUT
= 3.3V, V
IN
OUT
vs Temperature
= 1V, IL= 1 mA,
20161321
20161322
V
vs Temperature Ripple Rejection
OUT
20161328
20161359
20161354
www.national.com5
Typical Performance Characteristics Unless otherwise specified: V
C
IN
LP3879
= 4.7 µF, C
OUT
= 10 µF, V
S/D
= 2V, C
= 10 nF, TJ= 25˚C. (Continued)
BYP
Ripple Rejection Line Transient Response
20161358
Line Transient Response Line Transient Response
= 3.3V, V
IN
= 1V, IL= 1 mA,
OUT
20161331
20161333
Line Transient Response Line Transient Response
20161335
www.national.com 6
20161332
20161336
LP3879
Typical Performance Characteristics Unless otherwise specified: V
= 4.7 µF, C
C
IN
OUT
= 10 µF, V
S/D
= 2V, C
= 10 nF, TJ= 25˚C. (Continued)
BYP
Line Transient Response Load Transient Response
20161334
Load Transient Response Turn-On Characteristics
= 3.3V, V
IN
= 1V, IL= 1 mA,
OUT
20161345
20161343
20161355
www.national.com7
Block Diagram
LP3879
Application Information
PACKAGE INFORMATION
The LP3879 is offered in the 8 lead PSOP or LLP surface
mount packages to allow for increased power dissipation
compared to the SO-8 and Mini SO-8.
20161301
EXTERNAL CAPACITORS
Like any low-dropout regulator, the LP3879 requires external
capacitors for regulator stability. These capacitors must be
correctly selected for good performance.
INPUT CAPACITOR: A capacitor whose value is at least 4.7
±
20%) is required between the LP3879 input and
µF (
ground. A good quality X5R / X7R ceramic capacitor should
be used.
Capacitor tolerance and temperature variation must be considered when selecting a capacitor (see Capacitor Charac-
teristics section) to assure the minimum requirement of
input capacitance is met over all operating conditions.
The input capacitor must be located not more than 0.5" from
the input pin and returned to a clean analog ground. Any
good quality ceramic or tantalum capacitor may be used,
assuming the minimum input capacitance requirement is
met.
OUTPUT CAPACITOR: The LP3879 requires a ceramic
output capacitor whose size is at least 10 µF (
quality X5R / X7R ceramic capacitor should be used. Capacitance tolerance and temperature characteristics must be
considered when selecting an output capacitor.
The LP3879 is designed specifically to work with ceramic
output capacitors, utilizing circuitry which allows the regulator to be stable across the entire range of output current with
an ultra low ESR output capacitor.
The output capacitor selected must meet the requirement for
minimum amount of capacitance and also have an ESR
(equivalent series resistance) value which is within the
stable range. A curve is provided which shows the stable
ESR range as a function of load current (see Figure 1).
±
20%). A good
20161338
FIGURE 1. Stable Region For Output Capacitor ESR
Important: The output capacitor must maintain its ESR
within the stable region over the full operating temperature
range of the application to assure stability.
The output capacitor ESR forms a zero which is required to
add phase lead near the loop gain crossover frequency,
typically in the range of 50kHz to 200 kHz. The ESR at lower
frequencies is of no importance. Some capacitor manufacturers list ESR at low frequencies only, and some give a
formula for Dissipation Factor which can be used to calculate
a value for a term referred to as ESR. However, since the DF
formula is usually at a much lower frequency than the range
listed above, it will give an unrealistically high value. If good
quality X5R or X7R ceramic capacitors are used, the actual
ESR in the 50 kHz to 200 kHz range will not exceed 25 milli
Ohms. If these are used as output capacitors for the LP3879,
the regulator stability requirements are satisfied.
It is important to remember that capacitor tolerance and
variation with temperature must be taken into consideration
www.national.com 8
Application Information (Continued)
when selecting an output capacitor so that the minimum
required amount of output capacitance is provided over the
full operating temperature range. (See Capacitor Characteristics section).
The output capacitor must be located not more than 0.5"
from the output pin and returned to a clean analog ground.
NOISE BYPASS CAPACITOR: The 10 nF capacitor on the
Bypass pin significantly reduces noise on the regulator output and is required for loop stability. However, the capacitor
is connected directly to a high-impedance circuit in the bandgap reference.
Because this circuit has only a few microamperes flowing in
it, any significant loading on this node will cause a change in
the regulated output voltage. For this reason, DC leakage
current through the noise bypass capacitor must never exceed 100 nA, and should be kept as low as possible for best
output voltage accuracy.
The types of capacitors best suited for the noise bypass
capacitor are ceramic and film. High-quality ceramic capacitors with either NPO or COG dielectric typically have very
low leakage. 10 nF polypropolene and polycarbonate film
capacitors are available in small surface-mount packages
and typically have extremely low leakage current.
CAPACITOR CHARACTERISTICS
CERAMIC: The LP3879 was designed to work with ceramic
capacitors on the output to take advantage of the benefits
they offer: for capacitance values in the 10 µF range, ceramics are the least expensive and also have the lowest ESR
values (which makes them best for eliminating highfrequency noise). The ESR of a typical 10 µF ceramic capacitor is in the range of 5 mΩ to 10 mΩ, which meets the
ESR limits required for stability by the LP3879.
One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Many large value ceramic
capacitors (≥ 2.2 µF) are manufactured with the Z5U or Y5V
temperature characteristic, which results in the capacitance
dropping by more than 50% as the temperature goes from
25˚C to 85˚C.
Another significant problem with Z5U and Y5V dielectric
devices is that the capacitance drops severely with applied
voltage. A typical Z5U or Y5V capacitor can lose 60% of its
rated capacitance with half of the rated voltage applied to it.
For these reasons, X7R and X5R type ceramic capacitors must be used on the input and output of the
LP3879.
SHUTDOWN INPUT OPERATION
The LP3879 is shut off by pulling the Shutdown input low,
and turned on by pulling it high. If this feature is not to be
used, the Shutdown input should be tied to V
to keep the
IN
regulator output on at all times.
To assure proper operation, the signal source used to drive
the Shutdown input must be able to swing above and below
the specified turn-on/turn-off voltage thresholds listed in the
Electrical Characteristics section under V
ON/OFF
.
REVERSE INPUT-OUTPUT VOLTAGE
The PNP power transistor used as the pass element in the
LP3879 has an inherent diode connected between the regulator output and input.
During normal operation (where the input voltage is higher
than the output) this diode is reverse-biased.
However, if the output is pulled above the input, this diode
will turn ON and current will flow into the regulator output.
In such cases, a parasitic SCR can latch which will allow a
high current to flow into V
(and out the ground pin), which
IN
can damage the part.
In any application where the output may be pulled above the
input, an external Schottky diode must be connected from
to V
V
IN
(cathode on VIN, anode on V
OUT
), to limit the
OUT
reverse voltage across the LP3879 to 0.3V (see Absolute
Maximum Ratings).
LP3879
www.national.com9
Physical Dimensions inches (millimeters) unless otherwise noted
LP3879
8 Lead LLP Surface Mount PackagePackage
NS Package Number SDC08A
8-Lead PSOP Package (PSOP-8)
NS Package Number MRA08A
www.national.com 10
Notes
LP3879 Micropower 800mA Low Noise "Ceramic Stable" Voltage Regulator for Low Voltage
Applications
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
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and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:
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