National Semiconductor LP3879 Technical data

June 2006

LP3879 Micropower 800mA Low Noise "Ceramic Stable" Voltage Regulator for Low Voltage Applications

LP3879 Micropower 800mA Low Noise "Ceramic Stable" Voltage Regulator for Low Voltage

Applications

General Description

The LP3879 is a 800 mA fixed-output voltage regulator designed to provide high performance and low noise in applications requiring output voltages between 1.0V and

1.2V.

™

Using an optimized VIP cess, the LP3879 delivers superior performance:

Ground Pin Current: Typically 5.5 mA 200 µA

Low Power Shutdown: The LP3879 draws less than 10 µA quiescent current when shutdown pin is pulled low.

Precision Output: Guaranteed output voltage accuracy is 1% at room temperature.

Low Noise: Broadband output noise is only 18 µV (typical) with 10 nF bypass capacitor.

100 µA load.

(Vertically Integrated PNP) pro-

800 mA load, and

Basic Application Circuit

Features

n Standard output voltage: 1.00V, 1.20V n Custom voltages available from 1.0V to 1.2V (50 mV

increments)

n Input voltage: 2.5 to 6V n 1% initial output accuracy n Designed for use with low ESR ceramic capacitors n Very low output noise n Sense option improves load regulation n 8 Lead PSOP and LLP surface mount packages

10 µA quiescent current in shutdown

n Low ground pin current at all loads n High peak current capability n Over-temperature/over-current protection n -40˚C to +125˚C junction temperature range

Applications

n ASIC Power Supplies In:

- Desktops, Notebooks and Graphic Cards

- Set Top Boxes, Printers and Copiers

n DSP and FPGA Power Supplies n SMPS Post-Regulator n Medical Instrumentation

*Capacitance values shown are minimum required to assure stability. Larger output capacitor provides improved dynamic response. Output capacitor must meet ESR requirements (see Application Information). **The Shutdown pin must be actively terminated (see Application Information). Tie to INPUT (Pin 4) if not used.

VIP™is a trademark of National Semiconductor Corporation.

20161303

Connection Diagrams

LP3879

8 Lead PSOP Package (MRA) 8 Lead LLP Surface Mount Package (SD)

Top View

See NS Package Number MRA08A

20161330

Top View

See NS Package Number SDC08A

Ordering Information

TABLE 1. Package Marking and Ordering Information

Output Voltage Grade Order Information Supplied as:

1.00 STD LP3879MR-1.0 95 Units per Rail

1.00 STD LP3879MRX-1.0 2500 Units on Tape and Reel

1.00 STD LP3879SD-1.0 1000 Units on Tape and Reel

1.00 STD LP3879SDX-1.0 4500 Units on Tape and Reel

1.20 STD LP3879MR-1.2 95 Units per Rail

1.20 STD LP3879MRX-1.2 2500 Units on Tape and Reel

1.20 STD LP3879SD-1.2 1000 Units on Tape and Reel

1.20 STD LP3879SDX-1.2 4500 Units on Tape and Reel

Pin Descriptions

Pin Name Function

1 BYPASS The capacitor connected between BYPASS and GROUND lowers

output noise voltage level and is required for loop stability.

2 N/C DO NOT CONNECT. This pin is used for post package test and must

be left floating.

3 GROUND Device ground.

4 INPUT Input source voltage.

5 OUTPUT Regulated output voltage.

6 SENSE Remote Sense. Tie directly to output or remotely at point of load for

best regulation.

7 N/C No internal connection.

8 SHUTDOWN Output is enabled above turn-on threshold voltage. Pull down to turn off

regulator output.

PSOP, LLP

DAP

SUBSTRATE

GROUND

The exposed die attach pad should be connected to a thermal pad at ground potential. For additional information on using National Semiconductor’s Non Pull Back LLP package, please refer to LLP application note AN-1187

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LP3879

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Storage Temperature Range −65˚C to +150˚C

Operating Junction Temperature Range -40˚C to +125˚C

Lead Temperature (Soldering, 5 seconds) 260˚C

ESD Rating (Note 2) 2 kV

Power Dissipation (Note 3) Internally Limited

Input Supply Voltage (Survival) −0.3V to +16V

Input Supply Voltage (Typical Operating) 2.5V to +6V

SENSE Pin −0.3V to +6V

Output Voltage (Survival) (Note 4) −0.3V to +6V

(Survival) Short Circuit

OUT

Protected

Input-Output Voltage (Survival) (Note 5) −0.3V to +16V

Shutdown Pin 1kV

Electrical Characteristics

Limits in standard typeface are for TJ= 25˚C, and limits in boldface type apply over the temperature range of -40˚C to 125˚C. Limits are guaranteed through design, testing, or correlation. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Unless otherwise specified: V

BYPASS

=10nF.

= 3.0V, V

Symbol Parameter Conditions

Output Voltage Tolerance

Output Voltage Line

1mA≤ IL≤ 800 mA

3.0V ≤ V

≤ 6V

3.0V ≤ VIN≤ 6V

Regulation

= 800 mA

≥ V

OUT

Minimum Input

(min)

Voltage Required To Maintain Output Regulation

GND

(PK) Peak Output

Ground Pin Current IL= 100 µA

V 0 ≤ T

= 800 mA

≥ V

OUT

≤ 125˚C

= 750 mA

≥ V

OUT

= 200 mA

= 800 mA

≥ V

OUT

OUT(NOM)

Current

IO(MAX) Short Circuit

RL= 0 (Steady State)

Current

Output Noise Voltage (RMS)

BW = 100 Hz to 100 kHz

BYPASS

=10nF

Ripple Rejection f=1kHz

-1%

−5%

= 1V, IL= 1 mA, C

OUT

Min

(Note 6)

-1.0 1.00 1.0

-2.0

-3.0

= 10 µF, CIN= 4.7 µF, V

OUT

Typical

(Note 7)

1.00

Max

(Note 6)

2.0

3.0

0.014

0.007

0.032

2.5 3.1

2.5 2.8

2.5 3.0

200

1.5

5.5

250

275

3.3

8.5

1200

1400

18 µV(RMS)

60 dB

S/D

= 2V,

Units

%/V

µA

nom

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Electrical Characteristics (Continued)

Limits in standard typeface are for TJ= 25˚C, and limits in boldface type apply over the temperature range of -40˚C to 125˚C.

LP3879

Limits are guaranteed through design, testing, or correlation. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Unless otherwise specified: V

BYPASS

=10nF.

= 3.0V, V

Symbol Parameter Conditions

SHUTDOWN INPUT

S/D

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions.

Note 2: ESD testing was performed using Human Body Model, a 100 pF capacitor discharged through a 1.5 kΩ resistor.

Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T

and the ambient temperature, T

S/D Input Voltage VH= Output ON 1.4 1.6

= Output OFF

≤ 10 µA

≤ 10 mV

OUT

≤ 50 µA

S/D Input Current V

. The maximum allowable power dissipation at any ambient temperature is calculated using:

= 0 0.02 −1

S/D

=5V 5 15

S/D

= 1V, IL= 1 mA, C

OUT

Min

(Note 6)

= 10 µF, CIN= 4.7 µF, V

OUT

Typical

(Note 7)

Max

(Note 6)

0.1 0.50

0.6

(MAX), the junction-to-ambient thermal resistance, θ

S/D

= 2V,

Units

µA

J−A

The value of θ vias. If a four layer board is used with maximum vias from the IC center to the heat dissipating copper layers, values of θ 60˚C/W for the PSOP-8 and 40˚C/W for the LLP-8 package. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.

Note 4: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP3879 output must be diode-clamped to ground.

Note 5: The output PNP structure contains a diode between the V

on this diode and may induce a latch-up mode which can damage the part (see Application Hints).

Note 6: Limits are guaranteed through testing, statistical correlation, or design.

Note 7: Typical numbers reperesent the most likely norm for 25˚C operation.

for the LLP (SD) and PSOP (MRA) packages are specifically dependent on PCB trace area, trace material, and the number of layers and thermal

J−A

and V

terminals that is normally reverse-biased. Forcing the output above the input will turn

OUT

which can be obtained are approximately

J−A

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