National Semiconductor LP3878-ADJ Technical data

May 2005

LP3878-ADJ
Micropower 800mA Low Noise "Ceramic Stable"
Adjustable Voltage Regulator for 1V to 5V Applications

LP3878-ADJ Micropower 800mA Low Noise "Ceramic Stable" Adjustable Voltage Regulator for 1V

to 5V Applications

General Description

The LP3878-ADJ is an 800 mA adjustable output voltage
regulator designed to provide high performance and low
noise in applications requiring output voltages as low as

1.0V.

™

Using an optimized VIP
cess, the LP3878-ADJ delivers superior performance:

Ground Pin Current: Typically 5.5 mA
180 µA

Low Power Shutdown: The LP3878-ADJ draws less than
10 µA quiescent current when shutdown pin is pulled low.

Precision Output: Guaranteed output voltage accuracy is
1% at room temperature.

Low Noise: Broadband output noise is only 18 µV (typical)
with 10 nF bypass capacitor.

@

100 µA load.

(Vertically Integrated PNP) pro-

@

800 mA load, and

Basic Application Circuit

Features

n 1.0V to 5.5V output
n Designed for use with low ESR ceramic capacitors
n Very low output noise
n 8 Lead PSOP and LLP surface mount package

<

n

10 µA quiescent current in shutdown

n Low ground pin current at all loads
n Over-temperature/over-current protection
n -40˚C to +125˚C operating junction temperature range

Applications

n ASIC Power Supplies In:

- Desktops, Notebooks and Graphic Cards

- Set Top Boxes, Printers and Copiers

n DSP and FPGA Power Supplies
n SMPS Post-Regulator
n Medical Instrumentation

*Capacitance values shown are minimum required to assure stability. Larger output capacitor provides improved dynamic response. Output capacitor must
meet ESR requirements (see Application Information).
**The Shutdown pin must be actively terminated (see Application Information). Tie to INPUT (Pin 4) if not used.

VIP™is a trademark of National Semiconductor Corporation.

© 2005 National Semiconductor Corporation DS201209 www.national.com

20120903

Connection Diagrams

8 Lead PSOP Package (MRA) 8 Lead LLP Surface Mount Package (SD)

LP3878-ADJ

Top View

See NS Package Number MRA08A

20120930

Top View

See NS Package Number SDC08A

Ordering Information

TABLE 1. Package Marking and Ordering Information

Output Voltage Grade Order Information Supplied as:

ADJ STD LP3878MR-ADJ 95 Units per Rail

ADJ STD LP3878MRX-ADJ 2500 Units on Tape and Reel

ADJ STD LP3878SD-ADJ 1000 Units on Tape and Reel

ADJ STD LP3878SDX-ADJ 4500 Units on Tape and Reel

Pin Description

PIN NAME FUNCTION

1 BYPASS The capacitor connected between BYPASS and GROUND lowers

output noise voltage level and is required for loop stability.

2 N/C DO NOT CONNECT. This pin is used for post package test and must

be left floating.

3 GROUND Device ground.

4 INPUT Input source voltage.

5 OUTPUT Regulated output voltage.

6 ADJ Provides feedback to error amplifier from the resistive divider that sets

the output voltage.

7 N/C No internal connection.

8 SHUTDOWN Output is enabled above turn-on threshold voltage. Pull down to turn off

regulator output.

PSOP, LLP

DAP

SUBSTRATE

GROUND

The exposed die attach pad should be connected to a thermal pad at
ground potential. For additional information on using National
Semiconductor’s Non Pull Back LLP package, please refer to LLP
application note AN-1187

20120950

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LP3878-ADJ

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Storage Temperature Range −65˚C to +150˚C

Operating Junction Temperature
Range -40˚C to +125˚C

Lead Temperature (Soldering, 5
seconds) 260˚C

ESD Rating (Note 2) 2 kV

Power Dissipation (Note 3) Internally Limited

Input Supply Voltage (Survival) −0.3V to +16V

Input Supply Voltage (Typical
Operating) 2.5V to +16V

ADJ Pin −0.3V to +6V

Output Voltage (Survival) (Note 4) −0.3V to +6V

I

(Survival) Short Circuit

OUT

Protected

Input-Output Voltage (Survival)
(Note 5) −0.3V to +16V

Shutdown Pin 1kV

Electrical Characteristics

Limits in standard typeface are for TJ= 25˚C, and limits in boldface type apply over the temperature range of -40˚C to 125˚C.
Limits are guaranteed through design, testing, or correlation. The limits are used to calculate National’s Average Outgoing
Quality Level (AOQL). Unless otherwise specified: V

BYPASS

=10nF.

C

= 3.0V, V

IN

Symbol Parameter Conditions Min Typical Max Units

V

ADJ

Adjust Pin Voltage 0.99 1.00 1.01

Output Voltage Line

1mA≤ I

3.0V ≤ V

3.0V ≤ VIN≤ 16V

≤ 800 mA

L

≤ 6V

IN

Regulation

= 800 mA

I

L

Minimum Input

V

(min)

IN

Voltage Required
To Maintain Output
Regulation

Dropout Voltage

V

DO

I

GND

I

(PK) Peak Output

O

(Note 6)

= 3.8V

V

OUT

Ground Pin Current IL= 100 µA

≥ V

V

OUT

OUT(NOM)

I

= 800 mA

L

≥ V

V

OUT

OUT(NOM)

≤ 125˚C

0 ≤ T

J

I

= 750 mA

L

≥ V

V

OUT

OUT(NOM)

I

= 100 µA 1 2

L

IL= 200 mA 150 200

= 800 mA 475 600

I

L

I

= 200 mA

L

I

= 800 mA

L

V

≥ V

OUT

OUT(NOM)

-1%

-1%

-1%

−5%

Current

IO(MAX) Short Circuit

RL= 0 (Steady State)

Current

e

n

Output Noise
Voltage (RMS)

BW = 100 Hz to 100 kHz

BYPASS

=10nF

C

Ripple Rejection f=1kHz

= 1V, IL= 1 mA, C

OUT

0.98

0.97

= 10 µF, CIN= 4.7 µF, V

OUT

1.00

1.02

1.03

0.014

0.007

0.032

2.5 3.1

2.5 2.8

2.5 3.0

3

300

1100

180

1.5

5.5

200

225

2

3.5

8.5

15

1200

1300

18 µV(RMS)

60 dB

S/D

= 2V,

V

%/V

V

mV

µA

mA

mA

I

ADJ

ADJ Pin Bias
Current (Sourcing)

IL= 800 mA

200 nA

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Electrical Characteristics (Continued)

Limits in standard typeface are for TJ= 25˚C, and limits in boldface type apply over the temperature range of -40˚C to 125˚C.
Limits are guaranteed through design, testing, or correlation. The limits are used to calculate National’s Average Outgoing
Quality Level (AOQL). Unless otherwise specified: V

LP3878-ADJ

C

BYPASS

=10nF.

= 3.0V, V

IN

Symbol Parameter Conditions Min Typical Max Units

SHUTDOWN INPUT

V

S/D

I

S/D

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the
device outside of its rated operating conditions.

Note 2: ESD testing was performed using Human Body Model, a 100 pF capacitor discharged through a 1.5 kΩ resistor.

Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T

and the ambient temperature, T

S/D Input Voltage VH= Output ON 1.4 1.6

V

= Output OFF

L

≤ 10 µA

I

IN

V

≤ 10 mV

OUT

≤ 50 µA

I

IN

S/D Input Current V

. The maximum allowable power dissipation at any ambient temperature is calculated using:

A

= 0 0.02 −1

S/D

V

=5V 5 15

S/D

= 1V, IL= 1 mA, C

OUT

= 10 µF, CIN= 4.7 µF, V

OUT

0.04 0.20

0.6

(MAX), the junction-to-ambient thermal resistance, θ

J

S/D

= 2V,

V

µA

J−A

,

The value of θ
vias. If a four layer board is used with maximum vias from the IC center to the heat dissipating copper layers, values of θ
60˚C/W for the PSOP-8 and 40˚C/W for the LLP-8 package. For improved thermal resistance and power dissipation for the LLP package, refer to Application Note
AN-1187. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.

Note 4: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP3878-ADJ output must be diode-clamped to ground.

Note 5: The output PNP structure contains a diode between the V

on this diode and may induce a latch-up mode which can damage the part (see Application Hints).

Note 6: Dropout voltage spec applies only if V

for the LLP (SD) and PSOP (MRA) packages are specifically dependent on PCB trace area, trace material, and the number of layers and thermal

J−A

and V

IN

is sufficient so that it does not limit regulator operation.

IN

terminals that is normally reverse-biased. Forcing the output above the input will turn

OUT

which can be obtained are approximately

J−A

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