Datasheet LP38691-ADJ Datasheet (National Semiconductor)

查询LP38691-ADJ供应商

LP38691-ADJ/LP38693-ADJ
500mA Low Dropout CMOS Linear Regulators with
Adjustable Output

Stable with Ceramic Output Capacitors

PRELIMINARY

January 2005

LP38691-ADJ/LP38693-ADJ 500mA Low Dropout CMOS Linear Regulators with Adjustable Output

Stable with Ceramic Output Capacitors

General Description

The LP38691/3-ADJ low dropout CMOS linear regulators
provide 2.0% precision reference voltage, extremely low
dropout voltage (250mV
and excellent AC performance utilizing ultra low ESR ce­ramic output capacitors.

The low thermal resistance of the LLP and SOT-223 pack­ages allow the full operating current to be used even in high
ambient temperature environments.

The use of a PMOS power transistor means that no DC base
drive current is required to bias it allowing ground pin current
to remain below 100 µA regardless of load current, input
voltage, or operating temperature.

Dropout Voltage: 250 mV (typ)
Ground Pin Current: 55 µA (typ) at full load.
Adjust Pin Voltage: 2.0% (25˚C) accuracy.

@

500mA load current, V

@

500mA (typ. 5V out).

OUT

= 5V)

Typical Application Circuits

Features

n Output voltage range of 1.25V - 9V
n 2.0% adjust pin voltage accuracy (25˚C)
n Low dropout voltage: 250mV
n Wide input voltage range (2.7V to 10V)
n Precision (trimmed) bandgap reference
n Guaranteed specs for -40˚C to +125˚C
n 1µA off-state quiescent current
n Thermal overload protection
n Foldback current limiting
n SOT-223 and 6-Lead LLP packages
n Enable pin (LP38693-ADJ)

@

500mA (typ, 5V out)

Applications

n Hard Disk Drives
n Notebook Computers
n Battery Powered Devices
n Portable Instrumentation

20126801

20126802

V

Note: *Minimum value required for stability.

© 2005 National Semiconductor Corporation DS201268 www.national.com

OUT=VADJ

x (1 + R1/R2)

Connection Diagrams

LP38691-ADJ/LP38693-ADJ

6-Lead LLP, Bottom View

LP38691SD-ADJ

Pin Description

PIN DESCRIPTION

V

IN

GND Circuit ground for the regulator. This is connected to the die through the lead frame, and also

V

OUT

V

EN

ADJ The adjust pin is used to set the regulated output voltage by connecting it to the external

SOT-223, Top View

20126803

LP38693MP-ADJ

20126804

20126805

6-Lead LLP, Bottom View

LP38693SD-ADJ

This is the input supply voltage to the regulator. For LLP package devices, both VINpins must be
tied together for full current operation (250mA maximum per pin).

functions as the heat sink when the large ground pad is soldered down to a copper plane.

Regulated output voltage.

The enable pin allows the part to be turned ON and OFF by pulling this pin high or low.

resistors R1 and R2 (see Typical Application Circuit).

Ordering Information

Order Number Package Marking Package Type Package Drawing Supplied As

LP38691SD-ADJ L117B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38693SD-ADJ L127B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38693MP-ADJ LJUB SOT-223 MP05A 1000 Units Tape and Reel

LP38691SDX-ADJ L117B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38693SDX-ADJ L127B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38693MPX-ADJ LJUB SOT-223 MP05A 2000 Units Tape and Reel

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LP38691-ADJ/LP38693-ADJ

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

I

OUT

Internally Limited

Junction Temperature −40˚C to +150˚C

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Operating Ratings

Storage Temperature Range −65˚C to +150˚C

Lead Temp. (Soldering, 5 seconds) 260˚C

ESD Rating (Note 3) 2 kV

Power Dissipation (Note 2) Internally Limited

V(max) All pins (with respect to GND) -0.3V to 12V

Electrical Characteristics Limits in standard typeface are for T

over the full operating temperature range. Unless otherwise specified: V
Min/Max limits are guaranteed through testing, statistical correlation, or design.

Symbol Parameter Conditions Min

V

= 2.7V 1.225 1.25 1.275

IN

V

ADJ

∆V

/∆V

O

∆V

/∆I

O

L

V

IN-VO

I

Q

(MIN) Minimum Load Current VIN-VO≤ 4V 100

I

L

I

FB

PSRR Ripple Rejection V

T

SD

TSD(HYST) Thermal Shutdown Hysteresis

I

ADJ

ADJ Pin Voltage

Output Voltage Line Regulation

IN

(Note 6)

Output Voltage Load Regulation
(Note 7)

Dropout Voltage (Note 8)

3.2V ≤ V
100 µA

<

IN

≤ 10V

I

L

VO+ 0.5V ≤ VIN≤ 10V

= 25mA

I

L

1mA<I
V

IN=VO

(V

O

= 0.1A

I

L

= 0.5A

I

L

(V

O

= 0.1A

I

L

= 0.5A

I

L

(V

O

= 0.1A

I

L

= 0.5A

I

L

L

= 2.5V)

= 3.3V)

= 5V)

<

+1V

Quiescent Current VIN≤ 10V, IL= 100 µA - 0.5A 55 100

V

≤ 0.4V,

EN

(LP38693-ADJ Only)

IN-VO

IN=VO

>

5V 350

O

<

4V 850

+ 2V(DC), with 1V(p-p)

Foldback Current Limit VIN-V

V

/ 120Hz Ripple

Thermal Shutdown Activation
(Junction Temp)

(Junction Temp)

ADJ Input Leakage Current V

ADJ

V

IN

= 0 - 1.5V

= 10V

VINSupply Voltage 2.7V to 10V

Operating Junction

Temperature Range

= 25˚C, and limits in boldface type apply

J

IN=VOUT

+ 1V, CIN=C

OUT

= 10 µF, I

Typ

(Note 4)

<

0.5A

1.200 1.25 1.300

0.03 0.1 %/V

0.5A

1.8 5 %/A

80

430

65

330

45

250

0.001 1

55 dB

160

10

-100 0.01 100 nA

−40˚C to +125˚C

= 10mA.

LOAD

Max Units

V

145
725

110
550

mV

100
450

µA

mA

˚C

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Electrical Characteristics Limits in standard typeface are for T

over the full operating temperature range. Unless otherwise specified: V

IN=VOUT

= 25˚C, and limits in boldface type apply

J

+ 1V, CIN=C

Min/Max limits are guaranteed through testing, statistical correlation, or design. (Continued)

OUT

= 10 µF, I

LOAD

= 10mA.

Symbol Parameter Conditions Min

e

n

Output Noise BW = 10Hz to 10kHz

= 3.3V

V

O

VO(LEAK) Output Leakage Current VO=VO(NOM) + 1V@10V

V

EN

LP38691-ADJ/LP38693-ADJ

I

EN

Enable Voltage (LP38693-ADJ
Only)

Enable Pin Leakage

Output = OFF 0.4

Output = ON, V

Output = ON, V

Output = ON, V

=4V 1.8

IN

=6V 3.0

IN

= 10V 4.0

IN

VEN= 0V or 10V, VIN= 10V -1 0.001 1

IN

Typ

(Note 4)

Max Units

0.7 µV/

0.5 2 µA

(LP38693-ADJ Only)

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not
apply when operating the device outside of its rated operating conditions.

Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). The
junction-to-ambient thermal resistance (θ
area (less than 0.1 square inch). If one square inch of copper is used as a heat dissipator for the SOT-223, the θ
for the LLP package are also dependent on trace area, copper thickness, and the number of thermal vias used (refer to application note AN-1187). If power disspation
causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.

Note 3: ESD is tested using the human body model which is a 100pF capacitor discharged through a 1.5k resistor into each pin.

Note 4: Typical numbers represent the most likely parametric norm for 25˚C operation.

Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load.

Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value.

) for the SOT-223 is approximately 125 ˚C/W for a PC board mounting with the device soldered down to minimum copper

J-A

drops to approximately 70 ˚C/W. The θ

J-A

J-A

V

µA

values

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Block Diagrams

LP38691-ADJ/LP38693-ADJ

20126806

FIGURE 1. LP38691-ADJ Functional Diagram (LLP)

FIGURE 2. LP38693-ADJ Functional Diagram (SOT-223, LLP)

20126807

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Typical Performance Characteristics Unless otherwise specified: T

enable pin is tied to V

LP38691-ADJ/LP38693-ADJ

(LP38693-ADJ only), VO= 1.25V, VIN= 2.7V, IL= 10mA.

IN

Noise vs Frequency Noise vs Frequency

= 25˚C, CIN=C

J

OUT

=10µF,

20126835

Noise vs Frequency Ripple Rejection

20126837

Ripple Rejection Ripple Rejection

20126836

20126817

20126819

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20126821

LP38691-ADJ/LP38693-ADJ

Typical Performance Characteristics Unless otherwise specified: T

enable pin is tied to V

(LP38693-ADJ only), VO= 1.25V, VIN= 2.7V, IL= 10mA. (Continued)

IN

V

vs Temperature Line Transient Response

REF

20126830

Line Transient Response Line Transient Response

= 25˚C, CIN=C

J

OUT

=10µF,

20126823

20126824 20126825

Line Transient Response Line Transient Response

20126826 20126827

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Typical Performance Characteristics Unless otherwise specified: T

enable pin is tied to V

LP38691-ADJ/LP38693-ADJ

(LP38693-ADJ only), VO= 1.25V, VIN= 2.7V, IL= 10mA. (Continued)

IN

Line Transient Response Load Transient Response

= 25˚C, CIN=C

J

OUT

=10µF,

20126828

Load Transient Response Enable Voltage vs Temperature

20126844

Load Regulation vs Temperature Line Regulation vs Temperature

20126842

20126853

20126854

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20126855

LP38691-ADJ/LP38693-ADJ

Typical Performance Characteristics Unless otherwise specified: T

enable pin is tied to V

(LP38693-ADJ only), VO= 1.25V, VIN= 2.7V, IL= 10mA. (Continued)

IN

Dropout Voltage vs I

MIN V

vs I

IN

OUT

20126856

(V

= 25˚C, CIN=C

J

= 1.8V)

OUT

OUT

OUT

=10µF,

20126857

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Application Hints

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are re­quired to assure stability. These capacitors must be correctly
selected for proper performance.

INPUT CAPACITOR: An input capacitor of at least 1µF is
required (ceramic recommended). The capacitor must be
located not more than one centimeter from the input pin and
returned to a clean analog ground.

OUTPUT CAPACITOR: An output capacitor is required for

LP38691-ADJ/LP38693-ADJ

loop stability. It must be located less than 1 centimeter from
the device and connected directly to the output and ground
pins using traces which have no other currents flowing
through them.

The minimum amount of output capacitance that can be
used for stable operation is 1µF. Ceramic capacitors are
recommended (the LP38691/3-ADJ was designed for use
with ultra low ESR capacitors). The LP38691/3-ADJ is stable
with any output capacitor ESR between zero and 100 Ohms.

SETTING THE OUTPUT VOLTAGE: The output voltage is
set using the external resistors R1 and R2 (see Typical
Application Circuit). The output voltage will be given by the
equation:

V

OUT=VADJ

Because the part has a minimum load current requirement of
100 µA, it is recommended that R2 always be 12k Ohms or
less to provide adequate loading. Even if a minimum load is
always provided by other means, it is not recommended that
very high value resistors be used for R1 and R2 because it
can make the ADJ node susceptible to noise pickup. A
maximum Ohmic value of 100k is recommended for R2 to
prevent this from occurring.

ENABLE PIN (LP38693-ADJ only): The LP38693-ADJ has
an enable pin which turns the regulator output on and off.
Pulling the enable pin down to a logic low will turn the part
off. The voltage the pin has to be pulled up to in order to
assure the part is on depends on input voltage (refer to
Electrical Characteristics section). This pin should be tied to

if the enable function is not used.

V

IN

FOLDBACK CURRENT LIMITING: Foldback current limit­ing is built into the LP38691/3-ADJ which reduces the
amount of output current the part can deliver as the output
voltage is reduced. The amount of load current is dependent
on the differential voltage between V
when this differential voltage exceeds 5V, the load current
will limit at about 350 mA. When the V
reduced below 4V, load current is limited to about 850 mA.

SELECTING A CAPACITOR

It is important to note that capacitance tolerance and varia­tion with temperature must be taken into consideration when
selecting a capacitor so that the minimum required amount
of capacitance is provided over the full operating tempera­ture range.

Capacitor Characteristics
CERAMIC: For values of capacitance in the 10 to 100 µF

range, ceramics are usually larger and more costly than
tantalums but give superior AC performance for bypassing
high frequency noise because of very low ESR (typically less
than 10 mΩ). However, some dielectric types do not have
good capacitance characteristics as a function of voltage
and temperature.

X (1 + R1/R2)

and V

IN

IN-VOUT

. Typically,

OUT

differential is

Z5U and Y5V dielectric ceramics have capacitance that
drops severely with applied voltage. A typical Z5U or Y5V
capacitor can lose 60% of its rated capacitance with half of
the rated voltage applied to it. The Z5U and Y5V also exhibit
a severe temperature effect, losing more than 50% of nomi­nal capacitance at high and low limits of the temperature
range.

X7R and X5R dielectric ceramic capacitors are strongly rec­ommended if ceramics are used, as they typically maintain a

±

capacitance range within

20% of nominal over full operat­ing ratings of temperature and voltage. Of course, they are
typically larger and more costly than Z5U/Y5U types for a
given voltage and capacitance.

TANTALUM: Solid Tantalum capacitors have good tempera­ture stability: a high quality Tantalum will typically show a
capacitance value that varies less than 10-15% across the
full temperature range of -40˚C to 125˚C. ESR will vary only
about 2X going from the high to low temperature limits.

The increasing ESR at lower temperatures can cause oscil­lations when marginal quality capacitors are used (if the ESR
of the capacitor is near the upper limit of the stability range at
room temperature).

PCB LAYOUT

Good PC layout practices must be used or instability can be
induced because of ground loops and voltage drops. The
input and output capacitors must be directly connected to the
input, output, and ground pins of the regulator using traces
which do not have other currents flowing in them (Kelvin
connect).

The best way to do this is to lay out C
device with short traces to the V

IN,VOUT

and C

IN

, and ground pins.

OUT

near the

The regulator ground pin should be connected to the exter­nal circuit ground so that the regulator and its capacitors
have a "single point ground".

It should be noted that stability problems have been seen in
applications where "vias" to an internal ground plane were
used at the ground points of the IC and the input and output
capacitors. This was caused by varying ground potentials at
these nodes resulting from current flowing through the
ground plane. Using a single point ground technique for the
regulator and it’s capacitors fixed the problem. Since high
current flows through the traces going into V
from V

, Kelvin connect the capacitor leads to these pins

OUT

and coming

IN

so there is no voltage drop in series with the input and output
capacitors.

RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic
interference) can degrade any integrated circuit’s perfor­mance because of the small dimensions of the geometries
inside the device. In applications where circuit sources are
present which generate signals with significant high fre-

>

quency energy content (

1 MHz), care must be taken to

ensure that this does not affect the IC regulator.
If RFI/EMI noise is present on the input side of the regulator

(such as applications where the input source comes from the
output of a switching regulator), good ceramic bypass ca­pacitors must be used at the input pin of the IC.

If a load is connected to the IC output which switches at high
speed (such as a clock), the high-frequency current pulses
required by the load must be supplied by the capacitors on
the IC output. Since the bandwidth of the regulator loop is
less than 100 kHz, the control circuitry cannot respond to

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Application Hints (Continued)

load changes above that frequency. This means the effective
output impedance of the IC at frequencies above 100 kHz is
determined only by the output capacitor(s).

In applications where the load is switching at high speed, the
output of the IC may need RF isolation from the load. It is
recommended that some inductance be placed between the
output capacitor and the load, and good RF bypass capaci­tors be placed directly across the load.

PCB layout is also critical in high noise environments, since
RFI/EMI is easily radiated directly into PC traces. Noisy
circuitry should be isolated from "clean" circuits where pos­sible, and grounded through a separate path. At MHz fre­quencies, ground planes begin to look inductive and RFI/
EMI can cause ground bounce across the ground plane. In
multi-layer PCB applications, care should be taken in layout
so that noisy power and ground planes do not radiate directly
into adjacent layers which carry analog power and ground.

LP38691-ADJ/LP38693-ADJ

OUTPUT NOISE

Noise is specified in two ways- Spot Noise or Output Noise
density is the RMS sum of all noise sources, measured at
the regulator output, at a specific frequency (measured with
a 1Hz bandwidth). This type of noise is usually plotted on a
curve as a function of frequency. Total Output Noise or
Broad-Band Noise is the RMS sum of spot noise over a
specified bandwidth, usually several decades of frequencies.

Attention should be paid to the units of measurement. Spot
noise is measured in units µV/root-Hz or nV/root-Hz and total
output noise is measured in µV(rms)

The primary source of noise in low-dropout regulators is the
internal reference. Noise can be reduced in two ways: by
increasing the transistor area or by increasing the current
drawn by the internal reference. Increasing the area will
decrease the chance of fitting the die into a smaller package.
Increasing the current drawn by the internal reference in­creases the total supply current (ground pin current).

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Physical Dimensions inches (millimeters) unless otherwise noted

LP38691-ADJ/LP38693-ADJ

6-lead, LLP Package

NS Package Number SDE06A

SOT-223 Package

NS Package Number MP05A

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Notes

LP38691-ADJ/LP38693-ADJ 500mA Low Dropout CMOS Linear Regulators with Adjustable Output

Stable with Ceramic Output Capacitors

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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