3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low
LMX2487 High Performance Delta-Sigma Low Power Dual PLLatinum Frequency Synthesizer
February 2006
Power Dual PLLatinum
™
Frequency Synthesizers with
3.0 GHz Integer PLL
General Description
The LMX2487 is a low power, high performance delta-sigma
fractional-N PLL with an auxiliary integer-N PLL. It is fabricated using National Semiconductor’s advanced process.
With delta-sigma architecture, fractional spurs at lower offset
frequencies are pushed to higher frequencies outside the
loop bandwidth. The ability to push close in spur and phase
noise energy to higher frequencies is a direct function of the
modulator order. Unlike analog compensation, the digital
feedback technique used in the LMX2487 is highly resistant
to changes in temperature and variations in wafer processing. The LMX2487 delta-sigma modulator is programmable
up to fourth order, which allows the designer to select the
optimum modulator order to fit the phase noise, spur, and
lock time requirements of the system.
Serial data for programming the LMX2487 is transferred via
a three line high speed (20 MHz) MICROWIRE interface.
The LMX2487 offers fine frequency resolution, low spurs,
fast programming speed, and a single word write to change
the frequency. This makes it ideal for direct digital modulation applications, where the N counter is directly modulated
with information. The LMX2487 is available in a 24 lead
4.0 X 4.0 X 0.8 mm LLP package.
Applications
n Cellular phones and base stations
n Direct digital modulation applications
n Satellite and cable TV tuners
n WLAN Standards
Features
Quadruple Modulus Prescalers for Lower Divide Ratios
n RF PLL: 16/17/20/21 or 32/33/36/37
n IF PLL: 8/9 or 16/17
Advanced Delta Sigma Fractional Compensation
n 12 bit or 22 bit selectable fractional modulus
n Up to 4th order programmable delta-sigma modulator
Features for Improved Lock Times and Programming
n Fastlock / Cycle slip reduction
n Integrated time-out counter
n Single word write to change frequencies with Fastlock
Wide Operating Range
n LMX2487 RF PLL: 3.0 GHz to 6.0 GHz
Useful Features
n Digital lock detect output
n Hardware and software power-down control
n On-chip crystal reference frequency doubler.
n RF phase comparison frequency up to 50 MHz
n 2.5 to 3.6 volt operation with I
= 8.5 mA at 3.0 V
CC
Functional Block Diagram
20154701
PLLatinum™is a trademark of National Semiconductor Corporation.
0GND-Ground Substrate. This is on the bottom of the package and must be grounded.
1CPoutRFORF PLL charge pump output.
2GND-RF PLL analog ground.
3VddRF1-RF PLL analog power supply.
4FinRFIRF PLL high frequency input pin.
5FinRF*IRF PLL complementary high frequency input pin. Shunt to ground with a 100 pF
6LEIMICROWIRE Load Enable. High impedance CMOS input. Data stored in the shift
7DATAIMICROWIRE Data. High impedance binary serial data input.
8CLKIMICROWIRE Clock. High impedance CMOS Clock input. Data for the various counters is
9VddRF2-Power supply for RF PLL digital circuitry.
10CEIChip Enable control pin. Must be pulled high for normal operation.
11VddRF5IPower supply for RF PLL digital circuitry.
12Ftest/LDOTest frequency output / Lock Detect.
13FinIFIIF PLL high frequency input pin.
14VddIF1-IF PLL analog power supply.
15GND-IF PLL digital ground.
16CPoutIFOIF PLL charge pump output
17VddIF2-IF PLL power supply.
18OSCoutOBuffered output of the OSCin signal.
19ENOSCIOscillator enable. When this is set to high, the OSCout pin is enabled regardless of the
20OSCinIReference Input.
21NCIThis pin must be left open.
22VddRF3-Power supply for RF PLL digital circuitry.
23FLoutRFORF PLL Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
24VddRF4-RF PLL analog power supply.
Name
Top View
24-Pin LLP (SQ)
20154722
I/OPin Description
capacitor.
registers is loaded into the internal latches when LE goes HIGH
clocked into the 24 bit shift register on the rising edge
state of other pins or register bits.
www.national.com2
Absolute Maximum Ratings (Notes 1, 2)
LMX2487
ParameterSymbol
Power Supply VoltageV
Voltage on any pin with GND = 0VV
Storage Temperature RangeT
Lead Temperature (Solder 4 sec.)T
MinTypMax
CC
i
s
L
-0.34.25V
-0.3VCC+0.3V
-65+150˚C
Value
Units
+260˚C
Recommended Operating Conditions
ParameterSymbol
Power Supply Voltage (Note 1)V
Operating TemperatureT
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. "Recommended Operating Conditions" indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. The voltage at all the power supply pins of VddRF1, VddRF2, VddRF3,
VddRF4, VddRF5, VddIF1 and VddIF2 must be the same. V
through all these power pins.
Note 2: This Device is a high performance RF integrated circuit with an ESD rating
be done at ESD-free workstations.
Electrical Characteristics (V
CC
A
will be used to refer to the voltage at these pins and ICCwill be used to refer to the sum of all currents
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
High-Level Input Voltage1.6V
CC
Low-Level Input Voltage0.4V
High-Level Input Current VIH=V
CC
-1.01.0µA
Low-Level Input Current VIL= 0 V-1.01.0µA
High-Level Output
Voltage
Low-Level Output
Voltage
= -500 µAVCC-0.4V
I
OH
= 500 µA0.4V
I
OL
MICROWIRE INTERFACE TIMING
t
CS
t
CH
t
CWH
t
CWL
t
ES
t
EW
Note 3: For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required.
Note 4: Refer to table in Section 2.4.2 RF_CPG -- RF PLL Charge Pump Gain for complete listing of charge pump currents.
Note 5: In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one. The spur offset
frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth must be sufficiently wide to negate the
impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency =
20 MHz, RF_CPG = 7, DITH = 0, VCO Frequency = 3 GHz, and a 4th Order Modulator (FM = 0). These are relatively consistent over tuning range.
Note 6: Normalized Phase Noise Contribution is defined as: L
measured at an offset frequency, f, ina1HzBandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough
to avoid substantial phase noise contribution from the reference source. Measurement conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for
RF_CPG = 7, Fraction = 1/2000, Comparison Frequency = 20 MHz, FM = 0, DITH = 0, VCO Frequency = 3 GHz.
Data to Clock Set Up
Time
See MICROWIRE Input Timing25ns
Data to Clock Hold Time See MICROWIRE Input Timing8ns