National Semiconductor LMX2350, LMX2352 Technical data

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LMX2350/LMX2352 PLLatinumTM Fractional N RF / Integer N IF Dual Low Power Frequency

Synthesizer

LMX2350/LMX2352
PLLatinum

™

Fractional N RF / Integer N IF

Dual Low Power Frequency Synthesizer

LMX2350 2.5 GHz/550 MHz
LMX2352 1.2 GHz/550 MHz

General Description

The LMX2350/2352 is part of a family of monolithic inte­grated fractional N/ Integer N frequency synthesizers de­signed to be used in a local oscillator subsystem for a radio
transceiver. It is fabricated using National’s 0.5µ ABiC V sili­con BiCMOS process. The LMX2350/2352 contains dual
modulus prescalers along with modulo 15 or 16 fractional
compensation circuitry in the RF divider. A 16/17 or 32/33
prescale ratio can be selected for the LMX2350, and the
LMX2352 provides 8/9 or 16/17 prescale ratios. The IF cir­cuitry for both the LMX2350 and LMX2352 contains an 8/9
prescaler, and is fully programmable. Using a fractional N
phase locked loop technique, the LMX2350 /52 can gener­ate very stable low noise control signals for UHF and VHF
voltage controlled oscillators (VCO’s).

For the RF PLL, a highly flexible 16 level programmable
charge pump supplies output current magnitudes from
100µA to 1.6mA. Two uncommitted CMOS outputs can be
used to provide external control signals, or configured to

™

FastLock
LMX2350/2352 via a three wire interface (Data, LE, Clock).
Supply voltage can range from 2.7 V to 5.5 V.TheLMX2350/

mode. Serial data is transferred into the

2352 family features very low current consumption; typically
LMX2350 (2.5 GHz) 6.75 mA, LMX2352 (1.2 GHz) 5.00 mA
at 3.0V.TheLMX2350/2352areavailablein a 24-pin TSSOP
surface mount plastic package.

Features

n 2.7 V to 5.5 V operation
n Low current consumption

LMX2350: Icc = 6.75mA typ at 3v
LMX2352: Icc = 5.00mA typ at 3v

n Programmable or logical power down mode

Icc=5µAtypat3v

n Modulo 15 or 16 fractional RF N divider supports ratios

of 1, 2, 3, 4, 5, 8, 15, or 16

n Programmable charge pump current levels

RF 100µA to 1.6mA in 100µA steps
IF 100µA or 800 µA

n Digital filtered lock detect

Applications

n Portable wireless communications (PCS/PCN, cordless)
n Dual mode cellular telephone systems
n Zero blind slot TDMA systems
n Spread spectrum communication systems (CDMA)
n Cable TV Tuners (CATV)

PRELIMINARY

June 1999

Block Diagram

DS100831-1

FastLock™is a trademark of National Semiconductor Corporation.

™

MICROWIRE
PLLatinum
TRI-STATE

© 1999 National Semiconductor Corporation DS100831 www.national.com

is a trademark of National Semiconductor Corporation.

™

is a trademark of National Semiconductor Corporation.

®

is a registered trademark of National Semiconductor Corporation.

Connection Diagram

DS100831-2

Order Number LMX2350TM or LMX2352TM

NS Package Number MTC24

Pin Descriptions

Pin
No.

Pin

I/O Description

Name

1 OUT0 O Programmable CMOS output. Level of the output is controlled by IF_N [17] bit.
2 Vcc

RF

- RF PLL power supply voltage input. Must be equal to VccIF. May range from 2.7 V to 5.5 V.
Bypass capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane.

3V
4CP

p

RF

o

RF

- Power supply for RF charge pump. Must be ≥V

O RF charge pump output. Connected to a loop filter for driving the control input of an external

VCO.

and V

cc

RF

.

cc

IF

5 GND - Ground for RF PLL digital circuitry.
6 fin RF I RF prescaler input. Small signal input from the VCO.
7 fin RF

I RF prescaler complimentary input. A bypass capacitor should be placed as close as possible

to this pin and be connected directly to the ground plane.

8 GND - Ground for RF PLL analog circuitry.
9 OSCx I/O Dual mode oscillator output or RF R counter input. Has a Vcc/2 input threshold when

configured as an input and can be driven from an external CMOS or TTL logic gate. Can also
be configured as an output to work in conjunction with OSCin to form a crystal oscillator. (See
functional description 1.1 and programming description 3.1.)

10 OSCin I Oscillator input which can be configured to drive both the IF and RF R counter inputs or only

the IF R counter depending on the state of the OSC programming bit. (See functional
description 1.1 and programming description 3.1.)

11 FoLD O Multiplexed output of N or R divider and RF/IF lock detect. Active High/Low CMOS output

except in analog lock detect mode. (See programming description 3.1.5.)

®

12 RF_EN I RF PLL Enable. Powers down RF N and R counters, prescaler, and will TRI-STATE

the
charge pump output when LOW. Bringing RF_EN high powers up RF PLL depending on the
state of RF_CTL_WORD. (See functional description 1.9.)

13 IF_EN I IF PLL Enable. Powers down IF N and R counters, prescaler, and will TRI-STATE the charge

pump output when LOW. Bringing IF_EN high powers up IF PLL depending on the state of
IF_CTL_WORD. (See functional description 1.9.)

14 CLOCK I High impedance CMOS Clock input. Data for the various counters is clocked into the 24 - bit

shift register on the rising edge.

15 DATA I Binary serial data input. Data entered MSB first. The last two bits are the control bits. High

impedance CMOS input.

16 LE I Load enable high impedance CMOS input. Data stored in the shift registers is loaded into one

of the 4 internal latches when LE goes HIGH. (See functional description 1.7.)

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Connection Diagram (Continued)

Pin
No.

Pin
Name

I/O Description

17 GND - Ground for IF analog circuitry.
18 fin IF

I IF prescaler complimentary input. A bypass capacitor should be placed as close as possible

to this pin and be connected directly to the ground plane.
19 fin IF I IF prescaler input. Small signal input from the VCO.
20 GND - Ground for IF digital circuitry.
21 CPo
22 Vp
23 Vcc

IF

IF

IF

O IF charge pump output. For connection to a loop filter for driving the input of an external VCO.

- Power supply for IF charge pump. Must be ≥ V

and V

cc

RF

.

cc

IF

- IF power supply voltage input. Must be equal to VccRF. Input may range from 2.7 V to 5.5 V.
Bypass capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane.

24 OUT1 O Programmable CMOS output. Level of the output is controlled by IF_N [18] bit.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Value

Parameter Symbol Min Typ Max Units

Power Supply Voltage Vcc

Vcc
Vp

Vp

RF

IF

RF

IF

-0.3 6.5 V

-0.3 6.5 V

-0.3 6.5 V

-0.3 6.5 V
Voltage on any pin with GND = 0 volts Vi -0.3 Vcc + 0.3 V
Storage Temperature Range Ts -65 +150 C˚
Lead Temperature (Solder 4 sec.) T

L

+260 C˚

ESD - Whole Body Model (Note 2) 2 Kev

Recommended Operating Conditions

Value

Parameter Symbol Min Typ Max Units

Power Supply Voltage Vcc

Vcc
Vp

Vp

RF

IF

RF

IF

Operating Temperature TA -40 + 85 C

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur. Operating Ratings indicate conditions for which the
device is intended to be functional, but do not guarantee specific perfor­mance limits.Forguaranteed specifications and test conditions, see the Elec­trical Characteristics. The guaranteed specifications apply only for the test
conditions listed.

=

Electrical Characteristics (V

Sym-

Parameter Conditions Min Typ Max Units

cc

=

V

cc

RF

IF

bol
General

I

cc

Power Supply Current LMX2350 RF and IF,

V

LMX2352 RF and IF,

V

LMX2350/52 IF only, V

I

CC-PWDN

f

in

Power Down Current RF_EN = IF_EN = LOW 5 µA

RF RF Operating LMX2350 Prescaler = 32 (Note 3) 1.2 2.5 GHz

Frequency Prescaler = 16 (Note 3) 0.5 1.2 GHz

LMX2352 Prescaler = 16 (Note 3) 0.5 1.2 GHz

Prescaler = 8 (Note 3) 0.25 0.5 GHz

f

IF IF Operating Frequency 10 550 MHz

in

f

OSC

Oscillator Frequency No load on OSCx (Note 3) 2 50 MHz

With resonator load on

OSCx (Note 3)
fφ Phase Detector Frequency RF and IF 10 MHz
Pf

in RF

RF Input Sensitivity VCC= 3.0V −15 0 dBm

V
Pf

in IF

V

OSC

IF Input Sensitivity 2.7 V≤VCC≤ 5.5V −10 0 dBm
Oscillator Sensitivity OSCin, OSCx 0.5 V

2.7 5.5 V

Vcc

RF

Vcc

RF

V
Vcc 5.5 V
Vcc 5.5 V

Note 2: ThisDevice is a high performance RF integrated circuit and is ESD
sensitive. Handling and assembly of this device should only be done at ESD­free workstations.

=

V

=

V

P

RF

3.0V; −40˚ C

P

IF

<

<

T

85˚ C except as specified)

A

6.75 7.75 mA

=

2.7V to 5.5V

cc

5.0 6.0 mA

=

2.7V to 5.5V

cc

=

2.7V to 5.5V 1.25 1.45 mA

cc

2 20 MHz

= 5.0V −10 0 dBm

CC

CC

V

PP

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Electrical Characteristics (V

(Continued)

V

cc

RF

V

cc

IF

=

V

P

RF

3.0V; −40˚ C

P

IF

<

<

T

85˚ C except as specified)

A

=

=

=

Symbol Parameter Conditions Min Typ Max Units
Charge Pump

ICPo-

RF

ICPo­ICPo-

RF

ICPo­ICPo-

IF

ICPo­ICPo-

IF

ICPo­ICPo-

ICPo­vs.
ICPo-

ICPo vs.
VCPo

ICPo vs. T CP Current vs

RF Charge Pump

source

Output Current (see
Programming

sink RF

Description 3.2.2)

source

sink RF

IF Charge Pump Output

source

Current (see
Programming

sink IF

Description 3.1.4)

source

sink IF

Charge Pump

Tri

TRI-STATE Current
CP Sink vs. Source

sink

Mismatch

source

CP Current vs. Voltage 0.5 ≤ VCPo ≤ Vp -

Temperature

VCPo Vp/2, RF_CP_WORD = 0000 −100 µA

VCPo = Vp/2, RF_CP_WORD = 0000 100 µA
VCPo = Vp/2, RF_CP_WORD = 1111 −1.6 mA

VCPo = Vp/2, RF_CP_WORD = 1111 1.6 mA
VCPo = Vp/2, CP_GAIN_8 = 0 −100 µA

VCPo = Vp/2, CP_GAIN_8 = 0 100 µA
VCPo = Vp/2, CP_GAIN_8 = 1 −800 µA

VCPo = Vp/2, CP_GAIN_8 = 1 800 µA

0.5 ≤ VCPo ≤ Vp - 0.5

<TA<

-40˚ C

85˚ C

VCPo = Vp/2
TA = 25˚ C

0.5
= 25˚ C

T

A

VCPo = Vp/2

<TA<

-40˚ C

85˚ C

RFICPo
= 400 µA - 1.6 mA

RFICPo
= 800 µA - 1.6 mA

-2.5 2.5 nA

310

815

8

%

%

%

Digital Interface

V

IH

V

IL

I

IH

I

IL

I

IH

I

IL

V

OH

V

OL

High-level Input Voltage (Note 4) 0.8 Vcc V
Low-level Input Voltage (Note 4) 0.2 Vcc V

=

High-level Input Current V
Low-level Input Current V
Oscillator Input Current V
Oscillator Input Current V
High-level Output

Voltage
High-level Output

Voltage

I

I

=

V

IH
IL
IH
IL

OH

OL

5.5 V, (Note 4) −1.0 1.0 µA

CC

=

=

0, V

5.5 V, (Note 4) −1.0 1.0 µA

CC

=

=

V

5.5 V 100 µA

CC

=

=

0, V

5.5 V −100 µA

CC

=

−500 µA V

=

500 µA 0.4 V

−0.4 V

CC

MICROWIRE Timing

t

CS

t

CH

t

CWH

t

CWL

t

ES

t

EW

Note 3: Minimum operating frequencies are not production tested - only characterized.
Note 4: except fin, OSCin and OSCx

Data to Clock Setup

See Data Input Timing 50 ns

Time
Data to Clock Hold

See Data Input Timing 10 ns

Time
Clock Pulse Width High See Data Input Timing 50 ns
Clock Pulse Width Low See Data Input Timing 50 ns
Clock to Load Enable

See Data Input Timing 50 ns

Set Up Time
Load Enable Pulse

See Data Input Timing 50 ns

Width

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Charge Pump Current Specification Definitions

I1=CP sink current at V
I2=CP sink current at V
I3=CP sink current at V
I4=CP source current at V
I5=CP source current at V
I6=CP source current at V
∆V=Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V

Note 5: I
||6|}]

Note 6: I
Note 7: I

25˚C|]/||5@25˚C|*100

vs V

Do

*

%

100

Do-sink

vs T

Do

=

Vp − ∆V

Do

=

Vp/2

Do

=

∆V

Do

=

Vp − ∆V

Do

=

Vp/2

Do

=

∆V

Do

=

Charge Pump Output Current magnitude variation vs Voltage=[

Do

vs V

A

=

Charge Pump Output Current Sink vs Source Mismatch=[||2| − ||5|]/[

Do-source

=

Charge Pump Output Current magnitude variation vs Temperature=[||2

%

1

*

⁄

2

{||1| − ||3|}]/[1⁄

@

DS100831-7

and ground. Typical values are between 0.5V and 1.0V.

CC

*

2

{||1| + ||3|}]*100%and [1⁄

1

*

⁄

2

{||2| + ||5|}]*100

%

*

2

{||4| − ||6|}]/[1⁄

*

2

{||4| +

temp| − ||2@25˚C|]/||2@25˚C|*100%and [||5@temp| − ||5

@

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