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LMX2335L/LMX2336L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal
Communications
LMX2335L/LMX2336L
PLLatinum
™
Low Power Dual Frequency Synthesizer for
RF Personal Communications
LMX2335L 1.1 GHz/1.1 GHz
LMX2336L 2.0 GHz/1.1 GHz
General Description
The LMX2335L and LMX2336L are monolithic, integrated
dual frequency synthesizers, including two high frequency
prescalers, and are designed for applications requiring two
RF phase-lock loops. They are fabricated using National’s
0.5µ ABiC V silicon BiCMOS process.
The LMX2335L/36Lcontains twodual modulusprescalers. A
64/65 or a 128/129 prescaler can be selected for each RF
synthesizer. A second reference divider chain is included in
the IC for improved system noise. The LMX2335L/36L combined with a high quality reference oscillator, two loop filters,
and two external voltage controlled oscillators generates
very stable low noise RF local oscillator signals.
Serial data is transferred into the LMX2335L/36L via a three
wire interface (Data, Enable, Clock). Supply voltage can
range from 2.7V to 5.5V. The LMX2335L/36L feature very
low current consumption; LMX2335L 4.0 mA at 5V,
LMX2336L 5.5 mA at 5V. The LMX2335L is available in SO,
TSSOP and CSP 16-pin surface mount plastic packages.
The LMX2336L is available in a TSSOP 20-pin and CSP
24-pin surface mount plastic package.
PRELIMINARY
June 1999
Features
n Ultra low current consumption
n 2.7V to 5.5V operation
n Selectable synchronous and asynchronous powerdown
mode:
=
I
1 µA (typ)
CC
n Dual modulus prescaler: 64/65 or 128/129
n Selectable charge pump TRI-STATE
n Selectable charge pump current levels
n Selectable Fastlock
n Upgrade and compatible to LMX2335/36
n Small-outline, plastic, surface mount TSSOP package
n LMX2336 available in CSP package
™
mode
®
mode
Applications
n Cellular telephone systems (AMPS, ETACS, RCR-27)
n Cordless telephone systems
(DECT, ISM , PHS, CT-1+)
n Personal Communication Systems
(DCS-1800, PCN-1900)
n Dual Mode PCS phones
n Cable TV Tuners (CATV)
n Other wireless communication systems
Functional Block Diagram
DS012807-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
Fastlock
, MICROWIRE™and PLLatinum™are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012807 www.national.com
Connection Diagrams
LMX2335L
(Top View)
DS012807-2
Order Number LMX2335LM or LM2335LTM
NS Package Number M16A and MTC16
LMX2335L
(Top View)
DS012807-38
Order Number LMX2335LSLB
NS Package Number SLB16A
LMX2336L
(Top View)
DS012807-3
Order Number LMX2336LTM
NS Package Number MTC20
LMX2336L
(Top View)
DS012807-36
Order Number LMX2336LSLB
NS Package Number SLB24A
Pin Descriptions
Pin No. Pin No. Pin No. Pin No. Pin I/O Description
2336LTM 2336LSLB 2335LTM 2335LSLB Name
1 24 1 16 V
2221V
3332D
4443GNDLMX2335L: Ground for RF1 analog and RF1 digital circuits.
5554f
66XX/f
7 7 X X GND Ground for RF1 analog circuitry.
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1 Power supply voltage input for RF1 analog and RF1 digital
CC
1 Power supply for RF1 charge pump. Must be ≥ VCC.
p
1 O RF1 charge pump output. For connection to a loop filter for
o
circuits. Input may range from 2.7V to 5.5V. V
2. Bypass capacitors should be placed as close as possible
V
CC
to this pin and be connected directly to the ground plane.
CC
driving the input of an external VCO.
LMX2336L: Ground for RF digital circuits.
1 I RF1 prescaler input. Small signal input from the VCO.
IN
1 I RF1 prescaler complementary input. A bypass capacitor should
IN
be placed as close as possible to this pin and be connected
directly to the ground plane. Capacitor is optional with loss of
some sensitivity.
1 must equal
Pin Descriptions (Continued)
Pin No. Pin No. Pin No. Pin No. Pin I/O Description
2336LTM 2336LSLB 2335LTM 2335LSLB Name
8865OSC
9 10 7 6 OSC
10 11 8 7 F
o
11 12 9 8 Clock I High impedance CMOS Clock input. Data for the various latches
12 14 10 9 Data I Binary serial data input. Data entered MSB first. The last two bits
13 15 11 10 LE I Load enable high impedance CMOS input. When LE goes HIGH,
14 16 X X GND Ground for RF2 analog circuitry.
15 17 X X /f
16 18 12 11 f
IN
IN
17 19 13 12 GND LMX2335L: Ground for RF2 analog, RF2 digital, MICROWIRE,
18 20 14 13 D
19 22 15 14 V
20 23 16 15 V
X 1,9,13,
X X NC No connect.
p
CC
21
I Oscillator input. The input has a VCC/2 input threshold and can
in
out
be driven from an external CMOS or TTL logic gate.
O Oscillator output.
LD O Multiplexed output of the programmable or reference dividers,
lock detect signals and Fastlock mode. CMOS output
(see
Programmable Modes).
is clocked in on the rising edge, into the 20-bit shift register.
are the control bits. High impedance CMOS input.
data stored in the shift registers is loaded into one of the 4
appropriate latches (control bit dependent).
2 I RF2 prescaler complementary input. A bypass capacitor should
be placed as close as possible to this pin and be connected
directly to the ground plane. Capacitor is optional with loss of
some sensitivity.
2 I RF2 prescaler input. Small signal input from the VCO.
F
LD and Oscillator circuits. LMX2336L: Ground for IF digital,
o
MICROWIRE, F
2 O RF2 charge pump output. For connection to a loop filter for
o
driving the input of an external VCO.
LD and oscillator circuits.
o
2 Power supply for RF2 charge pump. Must be ≥ VCC.
2 Power supply voltage input for RF2 analog, RF2 digital,
MICROWIRE, F
2.7V to 5.5V. V
be placed as close as possible to this pin and be connected
LD and oscillator circuits. Input may range from
o
2 must equal VCC1. Bypass capacitors should
CC
directly to the ground plane.
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Block Diagram
Note 1: VCC1 supplies power to the RF1 prescaler, N-counter, R-counter, and phase detector. VCC2 supplies power to the RF2 prescaler, N-counter, phase
detector, R-counter along with the OSCinbuffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same
voltage level.
1 and VP2 can be run separately as long as VP≥ VCC.
Note 2: V
P
LMX2335L Pin
→
#
8/10←LMX2336L Pin
#
Pin Name→FoLD
X signifies a function not bonded out to a pin
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DS012807-4
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
V
CC
V
P
Voltage on Any Pin
with GND=0V (V
Storage Temperature Range (T
) −0.3V to VCC+0.3V
I
) −65˚C to +150˚C
S
Lead Temperature (solder 4 sec.) (T
−0.3V to +6.5V
−0.3V to +6.5V
) +260˚C
L
Recommended Operating
Conditions
Power Supply Voltage
V
CC
V
P
Operating Temperature (T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD
<
2 keV and is ESD sensitive. Handling and assembly of this device
rating
should only be done at ESD protected work stations.
) −40˚C to +85˚C
A
2.7V to 5.5V
VCCto +5.5V
Electrical Characteristics
=
V
5.0V, V
CC
Symbol Parameter Conditions Value Units
I
CC
I
CC
I
CC
f
1 Operating
IN
f
2 0.050 1.1 GHz
IN
f
1 LMX2336L 0.200 2.0 GHz
IN
f
2 0.050 1.1 GHz
IN
I
CC-PWDN
f
OSC
f
OSC
f
φ
Pf
IN
Pf
IN
V
OSC
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
I
Do-SOURCE
I
Do-SINK
I
Do-SOURCE
I
Do-SINK
I
Do-TRI
V
OH
V
OL
=
P
5.0V; T
=
25˚C, except as specified
A
Min Typ Max
Power Supply LMX2335L V
=
2.7V to 5.5V 4.0 5.2 mA
CC
Current RF1 and RF2
LMX2335L RF1 only 2.0 2.6 mA
LMX2336L 5.5 7 mA
RF1 and RF2
LMX2336L RF1 only 3.3 4.3 mA
LMX2335L 0.100 1.1 GHz
Frequency
Powerdown Current LMX2335L/2336L V
Oscillator Frequency With resonator load on OSC
=
5.5V 1 10 µA
CC
No load on OSC
out
out
5 20 MHz
5 40 MHz
Maximum Phase Detector Frequency 10 MHz
RF Input Sensitivity V
Oscillator Sensitivity OSC
=
CC
=
V
CC
in
High-Level Input Voltage (Note 4) 0.8 V
Low-Level Input Voltage (Note 4) 0.2 V
High-Level Input Current V
Low-Level Input Current V
Oscillator Input Current V
Oscillator Input Current V
Charge Pump Output Current V
=
IH
=
IL
=
IH
=
IL
=
Do
(Note 3)
=
V
Do
(Note 3)
=
V
Do
(Note 3)
=
V
Do
(Note 3)
>
3.0V, f
5.0V, f
100 MHz −15 0 dBm
>
100 MHz −10 0
0.5 V
CC
=
V
5.5V (Note 4) −1.0 1.0 µA
CC
=
0V, V
V
0V, V
V
V
V
V
5.5V (Note 4) −1.0 1.0 µA
CC
=
5.5V 100 µA
CC
=
5.5V −100 µA
CC
=
/2, I
P
/2, I
P
/2, I
P
/2, I
P
CPo
CPo
CPo
CPo
=
=
=
LOW
LOW
HIGH
HIGH
−1.25 mA
1.25 mA
−4.25 mA
4.25 mA
CC
Charge Pump 0.5V ≤ VDo≤ VCC− 0.5V −5.0 5.0 nA
TRI-STATE Current T=25˚C
High-Level Output Voltage I
Low-Level Output Voltage I
=
−500 µA V
OH
=
500 µA 0.4 V
OL
CC
0.4
−
PP
V
V
V
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Electrical Characteristics (Continued)
=
V
CC
Symbol Parameter Conditions Value Units
t
CS
t
CH
t
CWH
t
CWL
t
ES
t
EW
Note 3: See PROGRAMMABLE MODES for I
Note 4: Clock, Data and LE does not include f
5.0V, V
=
P
5.0V; T
=
25˚C, except as specified
A
Min Typ Max
Data to Clock Set Up Time See Data Input Timing 50 ns
Data to Clock Hold Time See Data Input Timing 10 ns
Clock Pulse Width High See Data Input Timing 50 ns
Clock Pulse Width Low See Data Input Timing 50 ns
Clock to Load Enable Set Up Time See Data Input Timing 50 ns
Load Enable Pulse Width See Data Input Timing 50 ns
description.
CPo
1, fIN2 and OSCin.
IN
Charge Pump Current Specification Definitions
I1=CP sink current at V
I2=CP sink current at V
I3=CP sink current at V
I4=CP source current at V
I5=CP source current at V
I6=CP source current at V
V=Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V
1. I
2. I
3. I
=
vs V
Do
Do
1
*
[
⁄
2
{|I1| − |I3|}]/[1⁄
vs I
Do-sink
Do-source
1
[|I2| − |I5|]/[
⁄
2
=
vs T
Do
A
@
[|I2
temp| − |I2@25˚C|]/|I2@25˚C|*100%and [|I5@temp| − |I5@25˚C|]/|I5@25˚C|*100
=
− ∆V
V
Do
P
=
/2
V
Do
P
=
∆V
Do
=
− ∆V
V
Do
P
=
/2
V
Do
P
=
∆V
Do
Charge Pump Output Current magnitude variation vs Voltage
*
2
{|I1| + |I3|}]*100%and [1⁄
=
Charge Pump Output Current Sink vs Source Mismatch
*
{|I2| + |I5|}]*100
Charge Pump Output Current magnitude variation vs Temperature
%
*
2
{|I4| − |I6|}]/[1⁄
*
2
{|I4| + |I6|}]*100
=
=
=
www.national.com 6
DS012807-18
and ground. Typical values are between 0.5V and 1.0V.
CC
%
%
RF Sensitivity Test Block Diagram
Note 5: N=10,000R=50P=64
Note 6: Sensitivity limit is reached when the error of the divided RF output, F
Typical Performance Characteristics
ICCvs V
CC
LMX2335L
DS012807-20
Charge Pump Current vs DoVoltage
=
I
HIGH
cp
LD, is ≥ 1 Hz.
o
ICCvs V
CC
LMX2336L
Charge Pump Current vs DoVoltage
=
I
LOW
cp
DS012807-19
DS012807-21
DS012807-22
DS012807-23
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Typical Performance Characteristics (Continued)
LMX2335L Input Impedance (for SO package)
=
V
2.7V to 5.5V, I
CC
Marker 1=1 GHz, Real=94, Imaginary=−118
Marker 2=1.2 GHz, Real=72, Imaginary=−88
Marker 3=1.5 GHz, Real=53, Imaginary=−45
Marker 4=500 MHz, Real=201, Imaginary=−224
LMX2335L Input Impedance (for TSSOP package)
=
V
2.7V to 5.5V, f
CC
=
50 MHz to 1.5 GHz
IN
=
50 MHz to 2.5 GHz
IN
DS012807-24
LMX2336L Input Impedance (for TSSOP package)
=
V
2.7V to 5.5V, f
CC
Marker 1=1 GHz, Real=97, Imaginary=−146
Marker 2=1.89 GHz, Real=43, Imaginary=−67
Marker 3=2.5 GHz, Real=30, Imaginary=−33
Marker 4=500 MHz, Real=189, Imaginary=−233
=
50 MHz to 2.5 GHz
IN
DS012807-25
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DS012807-31
Typical Performance Characteristics (Continued)
TRI-STATE
I
DO
vs D
Voltage
o
LMX2335L RF1 Sensitivity vs Frequency
LMX2335L RF2 Sensitivity vs Frequency
LMX2336L RF2 Sensitivity vs Frequency
DS012807-26
DS012807-28
DS012807-27
LMX2336L RF1 Sensitivity vs Frequency
DS012807-29
Oscillator Input Sensitivity vs Frequency
DS012807-30
DS012807-37
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Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and two 18-bit N Counters (intermediate
latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register,MSB first. The data stored
in the shift register is loaded into one of the 4 appropriate latches on the rising edge of LE. The last two bits are the Control Bits.
The DATA is transferred into the counters as follows:
Control Bits DATA Location
C1 C2
0 0 RF2 R Counter
0 1 RF1 R Counter
1 0 RF2 N Counter
1 1 RF1 N Counter
DS012807-5
PROGRAMMABLE REFERENCE DIVIDERS (RF1 AND RF2 R COUNTERS)
If the Control Bits are 00 or 01 (00 for RF2 and 01 for RF1) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
DS012807-6
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide RRRRRRRRRRRRRRR
Ratio 15 14 13 12 11 10 987654321
3 000000000000011
4 000000000000100
• •••••••••••••••
32767 111111111111111
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
www.national.com 10
Functional Description (Continued)
PROGRAMMABLE DIVIDER (N COUNTER)
Each N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for RF2 counter and 11 for RF1 counter) data is transferred from the 20-bit shift register into a 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bitlatch (which sets the 11-bitprogrammable (B) Counter), MSB first. Serial data
format is shown below.
DS012807-7
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
Divide N7N6N5N4N3N2N
Ratio
A
0 0000000
1 0000001
• •••••••
127 1111111
Notes:
Divide ratio: 0 to 127
B ≥ A
<
P
A
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
Divide N18N17N16N15N14N13N12N11N10N9N
Ratio
B
3 00000000011
4 00000000100
• •••••••••••
2047 11111111111
Note:
Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
B ≥ A
PULSE SWALLOW FUNCTION
=
f
[(PxB)+A]xf
VCO
: Output frequency of external voltage controlled oscillator (VCO)
f
VCO
OSC
/R
B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter
(0 ≤ A ≤ P; A ≤ B)
: Output frequency of the external reference frequency oscillator
f
OSC
R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual moduIus prescaler (P=64 or 128)
PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump tristate
and the output of the F
modes are shown in
LD pin. The prescaler and power down modes are selected with bits N19 and N20. The programmable
o
Table 1
. Truth table for the programmable modes and FoLD output are shown in
1
8
Table 2
and
Table 3
.
www.national.com11
Functional Description (Continued)
TABLE 1. Programmable Modes
C1 C2 R16 R17 R18 R19 R20
0 0 RF2 Phase RF2 I
Detector Polarity TRI-STATE
0 1 RF1 Phase RF1 I
Detector Polarity TRI-STATE
C1 C2 N19 N20
1 0 RF2 Pwdn
Prescaler RF2
1 1 RF1 Pwdn
Prescaler RF1
TABLE 2. Mode Select Truth Table
Phase Detector DoTRI-STATE I
Polarity (Note 9) (Note 7) (Note 8) Prescaler Prescaler (Note 7)
0 Negative Normal Operation LOW 64/65 64/65 pwrd up
1 Positive TRI-STATE HIGH 128/129 128/129 pwrd dn
Note 7: Refer to POWERDOWN OPERATION in Functional Description.
Note 8: The I
Note 9: PHASE DETECTOR POLARITY
LOW current state=1/4xI
CPo
Depending upon VCO characteristics, the R16 bits should be set accordingly:
When VCO characteristics are positive like (1), R16 should be set HIGH;
When VCO characteristics are negative like (2), R16 should be set LOW.
HIGH current.
CPo
VCO Characteristics
CPo
CPo
CPo
RF2 D
RF1 D
RF2 LD RF2 F
o
RF1 LD RF1 F
o
RF1 RF2 Pwdn
o
o
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DS012807-8
Functional Description (Continued)
TABLE 3. The F
RF1 R[19] RF2 R[19] RF1 R[20] RF2 R[20] FoLD
(RF1 LD) (RF2 LD) (RF1 F
0000Disabled (Note 10)
0100RF2Lock Detect (Note 11)
1000RF1Lock Detect (Note 11)
1100RF1/RF2 Lock Detect (Note 11)
X 0 0 1 RF2 Reference Divider Output
X 0 1 0 RF1 Reference Divider Output
X 1 0 1 RF2 Programmable Divider Output
X 1 1 0 RF1 Programmable Divider Output
0011Fastlock (Note 12)
0111RF2Counter Reset (Note 13)
1011RF1Counter Reset (Note 13)
1111RF1andRF2Counter Reset (Note 13)
X— don’t care condition
Note 10: When the F
Note 11: Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked.
Note 12: The Fastlock mode utilized the F
occurs whenever the RF loop’s Icpo magnitude bit
Note 13: The RF2 counter reset mode resets RF2 PLL’s R and N counters and brings RF2 charge pump output to a TRI-STATE condition. The RF1 counter reset
mode resets RF1 PLL’s R and N counters and brings RF1 charge pump output to a TRI-STATE condition. The RF1 and RF2 counter reset mode resets all counters
and brings both charge pump output to a TRI-STATE condition. Upon removal of the Reset bits the N counter resumes counting in “close” alignment with the R
counter. (The maximum error is one prescaler cycle).
LD output is disabled it is actively pulled to a low logic state.
o
LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
o
#
17 is selected HIGH (while the#19 and#20 mode bits are set for Fastlock).
LD Output Truth Table
o
) (RF2 FO) Output State
O
POWERDOWN OPERATION
Synchronous and asynchronous powerdown modes are
both available by microwire selection. Synchronously powerdown occurs if the respective loop’s R18 bit (Do TRI-STATE)
is LOW when its N20 bit (Pwdn) becomes HI. Asynchronous
powerdown occurs if the loop’s R18 bit is HI when its N20 bit
becomes HI.
In the synchronous powerdown mode, the powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program bit N20 is
loaded, the part will go into powerdown mode when the
charge pump reaches a TRI-STATE condition.
In the asynchronous powerdown mode, the device powers
down immediately after the LE pin latches in a HI condition
on the powerdown bit N20.
Activation of either the IF or RF PLL powerdown conditions
in either synchronous or asynchronous modes forces the respective loop’sR&Ndividers to their load state condition
and debiasing of it’s respective Fin input to a high impedance state. The oscillator circuitry function does not become
disabled until both IF and RF powerdown bits are activated.
The MICROWIRE control register remains active and capable of loading and latching data during all of the powerdown modes.
The device returns to an actively powered up condition in either synchronous ar asynchronous modes immediately upon
LE latching LOW data into bit N20.
Powerdown Mode Select Table
R18 N20 Powerdown Status
0 0 PLL Active
1 0 PLL Active (Charge Pump Output
TRI-STATE)
0 1 Synchronous Powerdown Initiated
1 1 Asynchronous Powerdown Initiated
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Functional Description (Continued)
SERIAL DATA INPUT TIMING
Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
=
Data to Clock Set Up Time
t
CS
=
Data to Clock Hold Time
t
CH
=
Clock Pulse Width High
t
CWH
=
Clock Pulse Width Low
t
CWL
=
Clock to Load Enable Set Up Time
t
ES
=
Load Enable Pulse Width
t
EW
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V
amplitudes of 2.2V@V
=
CC
2.7V and 2.6V
=
@
V
5.5V.
CC
/2. The test waveform has an edge rate of 0.6V/ns with
CC
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
Notes: Phase difference detection range: −2π to +2π
The minimum width pump up and pump down current pulses occur at the D
pin when the loop is locked.
o
DS012807-9
DS012807-10
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Typical Application Example
Operational Notes:
*
VCO is assumed AC coupled.
**
RINincreases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω
to 200Ω depending on the VCO power level. f
***
50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products a
CMOS clock is used and no terminating resistor is required. OSC
mended because the input circuit provides its own bias. (See
****
R2 configured FoLD for use in FastLock mode.
*****
Adding RC filters to the VCClines is recommended to reduce loop-to-loop noise coupling.
Application Hints:
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board
layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.
RF impedance ranges from 40Ω to 100Ω.fINIF impedances are higher.
IN
may be AC or DC coupled. AC coupling is recom-
in
Figure
below).
DS012807-12
DS012807-11
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Application Information
A block diagram of the basic phase locked loop is shown in
FIGURE 1. Conventional PLL Architecture
Loop Gain Equations
A linear control system model of the phase feedback for a
PLL in the locked state is shown in
gain is the product of the phase comparator gain (K
VCO gain (K
the gain of the feedback counter modulus (N). The passive
/s), and the loop filter gain Z(s) divided by
VCO
loop filter configuration used is displayed in
the complex impedance of the filter is given in equation 2.
FIGURE 2. PLL Linear Model
FIGURE 3. Passive Loop Filter
The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time contants T1 and T2, and
the design constants Kφ,K
VCO
Figure 2
DS012807-15
, and N.
. The open loop
), the
φ
Figure 3
, WHILE
DS012807-14
(1)
(2)
(3)
Figure 1
.
DS012807-13
From
Equation (3)
we can see that the phase term will be dependent on the single pole and zero such that the phase
margin is determined in
φ(ω)=tan
Equation (1)
−1
(ω•T2) −tan−1(ω•T1) + 180˚C (5)
.
A plot of the magnitude and phase of G(s) H(s) for a stable
loop, is shown in
eter φ
shows the amount of phase margin that exists at the
p
point the gain drops below zero (the cutoff frequency wp of
Equation (4)
with a solid trace. The param-
the loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop bandwidth, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison frequency also diminishes, the spurs would have increased by
approximately 6 dB. In the proposed Fastlock scheme, the
higher spur levels and wider loop filter conditions would exist
only during the initial lock-on phase —just long enough to
reap the benefits of locking faster. The objective would be to
open up the loop bandwidth but not introduce any additional
complications or compromises related to our original design
criteria. We would ideally like to momentarily shift the curve
Figure 4
over to a different cutoff frequency, illustrated by
dotted line, without affecting the relative open loop gain and
phase relationships. To maintain the same gain/phase relationship at twice the original cutoff frequency, other terms in
the gain and phase equations 4 and 5 will have to compensate by the corresponding “1/w” or “1/w
2
” factor.Examination
of equations 3 and 5 indicates the damping resistor variable
R2 could be chosen to compensate with “w” terms for the
phase margin. This implies that another resistor of equal
value to R2 will need to be switched in parallel with R2 during
the initial lock period. We must also insure that the magnitude of the open loop gain, H(s)G(s) is equal to zero at wp’
2 wp. K
changed by a factor of 4, to counteract with w
,Kφ, N, or the net product of these terms can be
VCO
in the denominator of equation 3. The Kφ term was chosen to
complete the transformation because it can readily be
switched between 1X and 4X values. This is accomplished
by increasing the charge pump output current from 1 mA in
the standard mode to 4 mA in Fastlock.
2
term present
(4)
=
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Application Information (Continued)
Fastlock Circuit Implementation
A diagram of the Fastlock scheme as implemented in National Semiconductors LMX2335L/36L PLL is shown in
ure 5
. When a new frequency is loaded, and the RF1 I
is set high, the charge pump circuit receives an input to deliver 4 times the normal current per unit phase error while an
open drain NMOS on chip device switches in a second R2
resistor element to ground. The user calculates the loop filter
component values for the normal steady state consider-
FIGURE 4. Open Loop Response Bode Plot
Fig-
CPo
ations. The device configuration ensures that as long as a
second identical damping resistor is wired in appropriately,
the loop will lock faster without any additional stability considerations to account for. Once locked on the correct frequency, the user can return the PLL to standard low noise
bit
operation by sending a MICROWIRE instruction with the
RF1 I
charge on the loop filter capacitors and is enacted synchro-
bit set low. This transition does not affect the
CPo
nous with the charge pump output. This creates a nearly
seamless change between Fastlock and standard mode.
DS012807-16
FIGURE 5. Fastlock PLL Architecture
DS012807-17
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Pin Chip Scale Package
Order Number LMX2336LSLB
*For Tape and Reel (2500 Units Per Reel)
Order Number LMX2336LSLBX
NS Package Number SLB24A
www.national.com 18
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
JEDEC 16-Lead (0.150" Wide) Small Outline Molded Package (M)
Order Number LMX2335LM
*
For Tape and Reel (2500 Units Per Reel)
Order Number LMX2335LMX
NS Package Number M16A
www.national.com19
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TM)
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Order Number LMX2335LTM
*
For Tape and Reel (2500 Units Per Reel)
Order Number LMX2335LTMX
NS Package Number MTC16
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM)
Order Number LMX2336LTM
*
For Tape and Reel (2500 Units Per Reel)
Order Number LMX2336LTMX
NS Package Number MTC20
www.national.com21
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Communications
16-Pin Chip Scale Package
Order Number LMX2335LSLB
*
For Tape and Reel (2500 Units Per Reel)
Order Number LMX2335LSLBX
NS Package Number SLB16A
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LMX2335L/LMX2336L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal
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