LMX2335L/LMX2336L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal
Communications
LMX2335L/LMX2336L
PLLatinum
™
Low Power Dual Frequency Synthesizer for
RF Personal Communications
LMX2335L1.1 GHz/1.1 GHz
LMX2336L2.0 GHz/1.1 GHz
General Description
The LMX2335L and LMX2336L are monolithic, integrated
dual frequency synthesizers, including two high frequency
prescalers, and are designed for applications requiring two
RF phase-lock loops. They are fabricated using National’s
0.5µ ABiC V silicon BiCMOS process.
The LMX2335L/36Lcontains twodual modulusprescalers. A
64/65 or a 128/129 prescaler can be selected for each RF
synthesizer. A second reference divider chain is included in
the IC for improved system noise. The LMX2335L/36L combined with a high quality reference oscillator, two loop filters,
and two external voltage controlled oscillators generates
very stable low noise RF local oscillator signals.
Serial data is transferred into the LMX2335L/36L via a three
wire interface (Data, Enable, Clock). Supply voltage can
range from 2.7V to 5.5V. The LMX2335L/36L feature very
low current consumption; LMX2335L 4.0 mA at 5V,
LMX2336L 5.5 mA at 5V. The LMX2335L is available in SO,
TSSOP and CSP 16-pin surface mount plastic packages.
The LMX2336L is available in a TSSOP 20-pin and CSP
24-pin surface mount plastic package.
PRELIMINARY
June 1999
Features
n Ultra low current consumption
n 2.7V to 5.5V operation
n Selectable synchronous and asynchronous powerdown
mode:
=
I
1 µA (typ)
CC
n Dual modulus prescaler: 64/65 or 128/129
n Selectable charge pump TRI-STATE
n Selectable charge pump current levels
n Selectable Fastlock
n Upgrade and compatible to LMX2335/36
n Small-outline, plastic, surface mount TSSOP package
n LMX2336 available in CSP package
™
mode
®
mode
Applications
n Cellular telephone systems (AMPS, ETACS, RCR-27)
n Cordless telephone systems
(DECT, ISM , PHS, CT-1+)
n Personal Communication Systems
(DCS-1800, PCN-1900)
n Dual Mode PCS phones
n Cable TV Tuners (CATV)
n Other wireless communication systems
Functional Block Diagram
DS012807-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
Fastlock
, MICROWIRE™and PLLatinum™are trademarks of National Semiconductor Corporation.
4443GNDLMX2335L: Ground for RF1 analog and RF1 digital circuits.
5554f
66XX/f
77XXGNDGround for RF1 analog circuitry.
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1Power supply voltage input for RF1 analog and RF1 digital
CC
1Power supply for RF1 charge pump. Must be ≥ VCC.
p
1O RF1 charge pump output. For connection to a loop filter for
o
circuits. Input may range from 2.7V to 5.5V. V
2. Bypass capacitors should be placed as close as possible
V
CC
to this pin and be connected directly to the ground plane.
CC
driving the input of an external VCO.
LMX2336L: Ground for RF digital circuits.
1IRF1 prescaler input. Small signal input from the VCO.
IN
1IRF1 prescaler complementary input. A bypass capacitor should
IN
be placed as close as possible to this pin and be connected
directly to the ground plane. Capacitor is optional with loss of
some sensitivity.
1 must equal
Pin Descriptions (Continued)
Pin No.Pin No.Pin No. Pin No.PinI/ODescription
2336LTM 2336LSLB 2335LTM 2335LSLB Name
8865OSC
91076OSC
101187F
o
111298ClockIHigh impedance CMOS Clock input. Data for the various latches
1214109DataIBinary serial data input. Data entered MSB first. The last two bits
13151110LEILoad enable high impedance CMOS input. When LE goes HIGH,
1416XXGNDGround for RF2 analog circuitry.
1517XX/f
16181211f
IN
IN
17191312GNDLMX2335L: Ground for RF2 analog, RF2 digital, MICROWIRE,
18201413D
19221514V
20231615V
X1,9,13,
XXNCNo connect.
p
CC
21
IOscillator input. The input has a VCC/2 input threshold and can
in
out
be driven from an external CMOS or TTL logic gate.
O Oscillator output.
LDO Multiplexed output of the programmable or reference dividers,
lock detect signals and Fastlock mode. CMOS output
(see
Programmable Modes).
is clocked in on the rising edge, into the 20-bit shift register.
are the control bits. High impedance CMOS input.
data stored in the shift registers is loaded into one of the 4
appropriate latches (control bit dependent).
2IRF2 prescaler complementary input. A bypass capacitor should
be placed as close as possible to this pin and be connected
directly to the ground plane. Capacitor is optional with loss of
some sensitivity.
2IRF2 prescaler input. Small signal input from the VCO.
F
LD and Oscillator circuits. LMX2336L: Ground for IF digital,
o
MICROWIRE, F
2O RF2 charge pump output. For connection to a loop filter for
o
driving the input of an external VCO.
LD and oscillator circuits.
o
2Power supply for RF2 charge pump. Must be ≥ VCC.
2Power supply voltage input for RF2 analog, RF2 digital,
MICROWIRE, F
2.7V to 5.5V. V
be placed as close as possible to this pin and be connected
LD and oscillator circuits. Input may range from
o
2 must equal VCC1. Bypass capacitors should
CC
directly to the ground plane.
www.national.com3
Block Diagram
Note 1: VCC1 supplies power to the RF1 prescaler, N-counter, R-counter, and phase detector. VCC2 supplies power to the RF2 prescaler, N-counter, phase
detector, R-counter along with the OSCinbuffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same
voltage level.
1 and VP2 can be run separately as long as VP≥ VCC.
Note 2: V
P
LMX2335L Pin
→
#
8/10←LMX2336L Pin
#
Pin Name→FoLD
X signifies a function not bonded out to a pin
www.national.com4
DS012807-4
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
V
CC
V
P
Voltage on Any Pin
with GND=0V (V
Storage Temperature Range (T
)−0.3V to VCC+0.3V
I
)−65˚C to +150˚C
S
Lead Temperature (solder 4 sec.) (T
−0.3V to +6.5V
−0.3V to +6.5V
)+260˚C
L
Recommended Operating
Conditions
Power Supply Voltage
V
CC
V
P
Operating Temperature (T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD
<
2 keV and is ESD sensitive. Handling and assembly of this device
rating
should only be done at ESD protected work stations.
Note 3: See PROGRAMMABLE MODES for I
Note 4: Clock, Data and LE does not include f
5.0V, V
=
P
5.0V; T
=
25˚C, except as specified
A
MinTypMax
Data to Clock Set Up TimeSee Data Input Timing50ns
Data to Clock Hold TimeSee Data Input Timing10ns
Clock Pulse Width HighSee Data Input Timing50ns
Clock Pulse Width LowSee Data Input Timing50ns
Clock to Load Enable Set Up TimeSee Data Input Timing50ns
Load Enable Pulse WidthSee Data Input Timing50ns
description.
CPo
1, fIN2 and OSCin.
IN
Charge Pump Current Specification Definitions
I1=CP sink current at V
I2=CP sink current at V
I3=CP sink current at V
I4=CP source current at V
I5=CP source current at V
I6=CP source current at V
V=Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V