查询LMX2335供应商
LMX2335/LMX2336/LMX2337
PLLatinum
Personal Communications
LMX2335 1.1 GHz/1.1 GHz
LMX2336 2.0 GHz/1.1 GHz
LMX2337 550 MHz/550 MHz
General Description
The LMX2335, LMX2336 and LMX2337 are monolithic, integrated dual frequency synthesizers, including two high frequency prescalers, and are designed for applications requiring two RF phase-lock loops. They are fabricated using
National’s ABiC IV silicon BiCMOS process.
The LMX2335/36/37 contains two dual modulus prescalers.
A 64/65 or a 128/129 prescaler can be selected for each RF
synthesizer. A second reference divider chain is included in
the IC for improved system noise. LMX2335/36/37, which
employ a digitalphaselocked loop technique, combined with
a high quality reference oscillator and loop filters, provide the
tuning voltages for voltage controlled oscillators to generate
very stable low noise RF local oscillator signals.
Serial data is transferred into the LMX2335/36/37 via a three
wire interface (Data, Enable, Clock). Supply voltage can
range from 2.7V to 5.5V. The LMX2335/36/37 feature very
low current consumption; LMX2335/37 −10 mA at 3V,
LMX2336 −13 mA at 3V. The LMX2335/37 are available in
™
Dual Frequency Synthesizer for RF
both a JEDEC SO and TSSOP 16-pin surface mount plastic
package. The LMX2336 is available in a TSSOP 20-pin surface mount plastic package.
Features
n 2.7V to 5.5V operation
n Low current consumption
n Selectable powerdown mode:
=
I
1 µA (typ)
CC
n Dual modulus prescaler: 64/65 or 128/129
n Selectable charge pump TRI-STATE
n Selectable charge pump current levels
n Selectable FastLock
™
mode
Applications
n Cellular telephone systems (AMPS, ETACS, RCR-27)
n Cordless telephone systems (DECT, ISM, PHS, CT-1+)
n Personal Communication Systems
(DCS-1800, PCN-1900)
n Dual Mode PCS phones
n CATV
n Other wireless communication systems
September 1996
®
mode
LMX2335/LMX2336/LMX2337 PLLatinum Dual Frequency Synthesizer for RF Personal
Communications
Functional Block Diagram
DS012332-1
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
Fastlock
, MICROWIRE™and PLLatinum™are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012332 www.national.com
Connection Diagrams
LMX2335/LMX2337
DS012332-2
Order Number LMX2335M/LMX2335TM or
LMX2337M/LMX2337TM
NS Package Number M16A and MTC16
Order Number LMX2336TM
LMX2336
DS012332-16
NS Package Number MTC20
Pin Descriptions
Pin No.
2335/37
10 12 Data I Binary serial data input. Data entered MSB first. The last two bits are the control bits.
11 13 LE I Load enable high impedance CMOS input. When LE goes HIGH, data stored in the
12 16 f
13 17 GND LMX2335/37: Ground for RF2 analog, RF2 digital, MICROWIRE
14 18 D
15 19 V
Pin No.
2336
11V
22V
33D
Pin
I/O Description
Name
1 Power supply voltage input for RF1 analog and RF1 digital circuits. Input may range
CC
from 2.7V to 5.5V. V
close as possible to this pin and be connected directly to the ground plane.
1 Power supply for RF1 charge pump. Must be ≥ VCC.
p
1 O RF1 charge pump output. For connection to a loop filter for driving the input of an
o
external VCO.
1 must equal VCC2. Bypass capacitors should be placed as
CC
4 4 GND LMX2335/37: Ground for RF1 analog and RF1 digital circuits. LMX2336: Ground for RF
digital circuitry.
55f
X6f
1 I First RF prescaler input. Small signal input from the VCO.
IN
1 I RF1 prescaler complementary input. A bypass capacitor should be placed as close as
IN
possible to this pin and be connected directly to the ground plane. Capacitor is optional
with loss of some sensitivity.
X 7 GND Ground for RF1 analog circuitry.
6 8 OSC
7 9 OSC
810F
I Oscillator input. The input has a VCC/2 input threshold and can be driven from an
in
out
LD O Multiplexed output of the programmable or reference dividers, lock detect signals and
o
external CMOS or TTL logic gate.
O Oscillator output.
Fastlock mode. CMOS output
(see Programmable Modes)
.
9 11 Clock I High impedance CMOS Clock input. Data for the various latches is clocked in on the
rising edge, into the 20-bit shift register.
High impedance CMOS input.
shift registers is loaded into one of the 4 appropriate latches (control bit dependent).
X 14 GND Ground for RF2 analog circuitry.
X15f
2 I RF2 prescaler complementary input. A bypass capacitor should be placed as close as
IN
possible to this pin and be connected directly to the ground plane. Capacitor is optional
with loss of some sensitivity.
2 I RF2 prescaler input. Small signal input from the VCO.
IN
circuits. LMX2336: Ground for RF2 digital, MICROWIRE, F
2 O RF2 charge pump output. For connection to a loop filter for driving the input of an
o
2 Power supply for RF2 charge pump. Must be ≥ VCC.
p
external VCO.
™
,FoLD and Oscillator
LD and Oscillator circuits.
o
www.national.com 2
Pin Descriptions (Continued)
Pin No.
2335/37
Pin No.
2336
16 20 V
Block Diagram
Pin
I/O Description
Name
2 Power supply voltage input for RF2 analog. RF2 digital, MICROWIRE, FoLD and
CC
Oscillator circuits. Input may range from 2.7V to 5.5V. V
capacitors should be placed as close as possible to this pin and be connected directly
2 must equal VCC1. Bypass
CC
to the ground plane.
Note: VCC1 supplies power to the RF1 prescaler, N-counter, R-counter, and phase detector. VCC2 supplies power to the RF2 prescaler, N-counter, phase
detector, R-counter along with the OSCinbuffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same
voltage level.
1 and VP2 can be run separately as long as VP≥ VCC.
V
P
LMX2335/37 Pin
→
#
8/10←LMX2336 Pin
#
DS012332-17
Pin Name→FoLD
X signifies a function not available
www.national.com3
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
V
CC
V
P
Voltage on Any Pin
with GND=0V (V
) −0.3V to VCC+0.3V
I
Storage Temperature Range (T
) −65˚C to +150˚C
S
−0.3V to +6.5V
−0.3V to +6.5V
Lead Temperature (solder 4 sec.) (T
) +260˚C
L
Recommended Operating
Conditions
Power Supply Voltage
V
CC
V
P
Operating Temperature (T
) −40˚C to +85˚C
A
2.7V to 5.5V
VCCto +5.5V
Electrical Characteristics
=
V
CC
Symbol Parameter Conditions
I
CC
I
CC
I
CC
f
1 Operating
IN
f
2 0.050 1.1 GHz
IN
f
1 LMX2336 0.200 2.0 GHz
IN
f
2 0.050 1.1 GHz
IN
f
1 LMX2337 100 550 MHz
IN
f
2 50 550 MHz
IN
I
CC-PWDN
f
OSC
f
OSC
f
φ
Pf
1
IN
and Pf
in
V
OSC
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
I
Do-SOURCE
I
Do-SINK
I
Do-SOURCE
I
Do-SINK
5.0V, V
=
p
5.0V; T
=
25˚C, except as specified
A
Value
Min Typ Max
Power Supply
Current
LMX2335/37
RF1 and RF2
LMX2335/37 RF1
only
LMX2336
RF1 and RF2
VCC= 2.7V to 5.5V
10 15 mA
68mA
13 18 mA
LMX2336 RF1 only 7 11 mA
LMX2335 0.100 1.1 GHz
Frequency
Powerdown Current LMX2335/2336 VCC= 5.5V 1 25
LMX2337 100
Oscillator Frequency With resonator load on OSC
No load on OSC
OUT
out
5 20 MHz
5 40 MHz
Phase Detector Frequency 10 MHz
RF Input Sensitivity V
2
Oscillator Sensitivity OSC
= 3.0V, f>100 MHz −15 +4
CC
= 5.0V, f>100 MHz −10 +4
V
CC
V
= 2.7 to 5.5V,
CC
>
f
100 MHz
IN
−10 0
0.5 V
High-Level Input Voltage (Note 4) 0.8
V
CC
Low-Level Input Voltage (Note 4) 0.2
High-Level Input Current VIH=VCC= 5.5V (Note 4) −1.0 1.0 µA
Low-Level Input Current VIL= 0V, VCC= 5.5V (Note 4) −1.0 1.0 µA
Oscillator Input Current VIH=VCC= 5.5V 100 µA
Oscillator Input Current VIL= 0V, VCC= 5.5V −100 µA
Charge Pump Output Current V
=Vp/2, I
D
o
(Note 3)
V
=Vp/2, I
D
o
(Note 3)
V
=Vp/2, I
D
o
(Note 3)
V
=Vp/2, I
D
o
(Note 3)
CP
CP
CP
CP
= LOW
o
= LOW
o
= HIGH
o
= HIGH
o
−1.25 mA
1.25 mA
−5.0 mA
5.0 mA
V
CC
Units
µA
dBm
PP
V
V
www.national.com 4
Electrical Characteristics (Continued)
=
V
CC
Symbol Parameter Conditions
I
Do-TRI
I
Do-TRI
V
OH
V
OL
t
CS
I
CH
t
CWH
t
CWL
t
ES
t
EW
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which
the device is intended to be functional, but do not guarantee specific performanced limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD rating
be done at ESD protected workstations.
Note 3: See PROGRAMMABLE MODES for I
Note 4: Clock, Data and LE does not include f
5.0V, V
=
p
5.0V; T
=
25˚C, except as specified
A
Value
Min Typ Max
Charge Pump
TRI-STATE
LMX2335
LMX2336
0.5V ≤ V
T = 25˚C −5.0 5.0 nA
≤ Vp− 0.5V
D
o
CURRENT
Charge Pump
TRI-STATE
LMX2337 0.5V ≤ V
T = 25˚C
≤ Vp− 0.5V
D
o
±
5nA
CURRENT
High-Level Output Voltage IOH= −500 µA VCC−
0.4
Low-Level Output Voltage IOL= 500 µA 0.4 V
Data to Clock Setup Time See Data Input Timing 50 ns
Data to Clock Hold Time See Data Input Timing 10 ns
Clock Pulse Width High See Data Input Timing 50 ns
Clock Pulse Width Low See Data Input Timing 50 ns
Clock to Load Enable Set Up Time See Data Input Timing 50 ns
Load Enable Pulse Width See Data Input Timing 50 ns
<
2 keV and is ESD sensitive. Handling and assembly of this device should only
description.
CP
o
1, fIN2 and OSCin.
IN
Typical Performance Characteristics
Units
V
ICC vs V
CC
LMX2335/37
DS012332-19
ICCvs V
LMX2336
CC
DS012332-20
www.national.com5
Typical Performance Characteristics (Continued)
Charge Pump Current vs D
=
I
HIGH
CP
LMX2335/37 Input Impedance (for SO package)
=
V
2.7V to 5.5V, f
CC
Voltage
o
=
50 MHz to 1.5 GHz
IN
DS012332-21
Charge Pump Current vs DoVoltage
=
I
LOW
CP
DS012332-22
LMX2335/37 Input Impedance (for TSSOP package)
LMX2336 Input Impedance V
=
f
50 MHz to 2.5 GHz
IN
=
CC
2.7V to 5.5V,
Marker 1=1 GHz, Real=94, Imaginary=−118
Marker 2=1.2 GHz, Real=72, Imaginary=−88
Marker 3=1.5 GHz, Real=53, Imaginary=−45
Marker 4=500 MHz, Real=201, Imaginary=−224
www.national.com 6
DS012332-23
Marker 1=1 GHz, Real=97, Imaginary=−146
Marker 2=1.89 GHz, Real=43, Imaginary=−67
Marker 3=2.5 GHz, Real=30, Imaginary=−33
Marker 4=500 MHz, Real=189, Imaginary=−233
DS012332-24
Typical Performance Characteristics (Continued)
TRI-STATE
I
Do
vs D
Voltage
o
LMX2335/37 RF1 Sensitivity vs Frequency
LMX2335/37 RF2 Sensitivity vs Frequency
LMX2336 RF2 Sensitivity vs Frequency
DS012332-25
DS012332-27
DS012332-26
LMX2336 RF1 Sensitivity vs Frequency
DS012332-28
Oscillator Input Sensitivity vs Frequency
DS012332-29
DS012332-30
www.national.com7
Functional Description
The simplified block diagram below shows the 22-bit data register,two 15-bit R Counters and two 18-bit N Counters (intermediate
latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATAregister, MSB first. The data stored
in the shift register is loaded into one of the 4 appropriate latches on the rising edge of LE. The last two bits are the Control Bits.
The DATAis transferred into the counters as follows:
Control Bits DATA Location
C1 C2
0 0 RF2 R Counter
0 1 RF1 R Counter
1 0 RF2 N Counter
1 1 RF1 N Counter
DS012332-1
PROGRAMMABLE REFERENCE DIVIDERS (RF1 AND RF2 R COUNTERS)
If the Control Bits are 00 or 01 (00 for RF2 and 01 for RF1) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
DS012332-4
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide
RatioR15R14R13R12R11R10R9R8R7R6R5R4R3R2R1
3 000000000000011
4 000000000000100
• •••••••••••••••
32767 111111111111111
Notes: Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
www.national.com 8
Functional Description (Continued)
PROGRAMMABLE DIVIDER (N COUNTER)
Each N counter consists of the 7-bit swallow counter (Acounter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for RF2 counter and 11 for RF1 counter) data is transferred from the 20-bit shift register into a 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bitlatch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data
format is shown below.
DS012332-5
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
Divide
N7N6N5N4N3N2N
Ratio
A
0 0000000
1 0000001
• •••••••
127 1111111
Notes: Divide ratio: 0 to 127
B ≥ A
<
P
A
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
Divide
Ratio
B
N
18
N
17
N
16
N
15
N
14
N
13
3 00000000011
4 00000000100
• •••••••••••
2047 11111111111
Notes: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
B ≥ A
PULSE SWALLOW FUNCTION
=
f
[(PxB)+A]xf
VCO
: Output frequency of external voltage controlled oscillator (VCO)
f
VCO
OSC
/R
B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter
(0 ≤ A ≤ P; A ≤ B)
: Output frequency of the external reference frequency oscillator
f
OSC
R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual moduIus prescaler (P=64 or 128)
PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump tristate
and the output of the F
modes are shown in
LD pin. The prescaler and power down modes are selected with bits N19 and N20. The programmable
o
Table 1
. Truth table for the programmable modes and FoLD output are shown in
1
N
12
N
11
N
10
Tables 2, 3
N
9
N
8
.
www.national.com9
Functional Description (Continued)
TABLE 1. Programmable Modes
C1 C2 R16 R17 R18 R19 R20
0 0 RF2 Phase
Detector Polarity
0 1 RF1 Phase
Detector Polarity
RF2 I
RF1 I
CP
CP
o
O
RF2 D
TRI-STATE
RF1 D
TRI-STATE
C1 C2 N19 N20
10
11
RF2
Prescaler
RF1
Prescaler
TABLE 2. Mode Select Truth Table
Phase Detector Polarity
(Note 7)
TRI-STATE
D
o
I
CP
o
(Note 5)
0 Negative Normal Operation LOW 64/65 64/65 pwrd up
1 Positive TRI-STATE HIGH 128/129 128/129 pwrd dn
Note 5: The I
Note 6: Activation of the RF2 PLL or RF1 PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective f
(to a high impedance state). The powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program mode is
loaded, the part will go into powerdown mode when the charge pump reaches a TRI-STATE condition. The R counter and Oscillator functionality does not become
disabled until
dition exists. The MICROWIRE control register remains active and capable of loading and latching data during all of the powerdown modes.
Note 7: PHASE DETECTOR POLARITY
Depending upon VCO characteristics, the R16 bits should be set accordingly:
When VCO characteristics are positive like (1), R16 should be set HIGH;
When VCO characteristics are negative like (2), R16 should be set LOW.
Note 8:
LOW current state=1/4xI
CP
o
both
RF2 and RF1 powerdown bits are activated. The OSCinis connected to VCCthrough 100 kΩ resistor and the OSC
HIGH current.
CP
o
RF2 LD RF2 F
o
RF1 LD RF1 F
o
Pwdn
RF2
Pwdn
RF1
RF1
Prescaler
RF2
Prescaler
o
o
Pwdn
(Note 6)
goes HIGH when this con-
out
IN
inputs
VCO Characteristics
TABLE 3. The FoLD Output Truth Table
RF1 R[19]
(RF1 LD)
RF2 R[19]
(RF2 LD)
RF1 R[20]
(RF1 F
RF2 R[20]
)
o
0000Disabled (Note 9)
0100RF2Lock Detect (Note 10)
1000RF1Lock Detect (Note 10)
1100RF1/RF2 Lock Detect (Note 10)
X 0 0 1 RF2 Reference Divider Output
X 0 1 0 RF1 Reference Divider Output
X 1 0 1 RF2 Programmable Divider Output
X 1 1 0 RF1 Programmable Divider Output
0011Fastlock (Note 11)
0111ForInternal use only
1011ForInternal use only
1111Counter Reset (Note 12)
X— don’t care condition
www.national.com 10
(RF2 Fo)
DS012332-7
F
LD
o
Output State
Functional Description (Continued)
Note 9: When the FoLD output is disabled it is actively pulled to a low logic state.
Note 10: Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked.
Note 11: The Fastlock mode utilized the F
occurs whenever the RF loop’s Icpo magnitude bit
Note 12: The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits the N counter resumes counting in “close”
alignment with the R counter. (The maximum error is one prescaler cycle). If the Reset bits are activated the R counter is also forced to Reset, allowing smooth acquisition upon powering up.
SERIAL DATA INPUT TIMING
LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
o
#
17 is selected HIGH (while the#19 and#20 mode bits are set for Fastlock).
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V
amplitudes of 2.2V@V
=
2.7V and 2.6V
CC
=
@
V
5.5V.
CC
/2. The test waveform has an edge rate of 0.6V/ns with
CC
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
Notes: Phase difference detection range: −2π to +2π
The minimum width pump up and pump down current pulses occur at the D
pin when the loop is locked.
o
DS012332-8
DS012332-9
www.national.com11
Typical Application Example
Operational Notes:
*
VCO is assumed AC coupled.
**
RINincreases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to
200Ω depending on the VCO power level. f
***
50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products a
CMOS clock is used and no terminating resistor is required. OSC
mended because the input circuit provides its own bias. (See
****
Adding RC filters to the VCClines is recommended to reduce loop-to-loop noise coupling.
Application Hints:
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board
layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.
RF impedance ranges from 40Ω to 100Ω.fINIF impedances are higher.
IN
may be AC or DC coupled. AC coupling is recom-
in
Figure
below).
DS012332-11
DS012332-10
Application Information
A block diagram of the basic phase locked loop is shown in
Figure 1
.
FIGURE 1. Conventional PLL Architecture
www.national.com 12
DS012332-12
Application Information (Continued)
Loop Gain Equations
A linear control system model of the phase feedback for a
PLL in the locked state is shown in
gain is the product of the phase comparator gain (K
VCO gain (K
the gain of the feedback counter modulus (N). The passive
/s), and the loop filter gain Z(s) divided by
VCO
loop filter configuration used is displayed in
the complex impedance of the filter is given in
FIGURE 2. PLL Linear Model
FIGURE 3. Passive Loop Filter
The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as
T2=R2
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time contants T1 and T2, and
the design constants Kφ,K
From
Equation (3)
we can see that the phase term will be dependent on the single pole and zero such that the phase
margin is determined in
φ(ω)=tan
Equation (5)
−1
(ω•T2) −tan−1(ω•T1) + 180˚C (6)
Figure 2
DS012332-13
C2 (4)
•
, and N.
VCO
.
. The open loop
), the
φ
Figure 3
, while
Equation (2)
DS012332-14
(1)
(2)
(3)
(5)
A plot of the magnitude and phase of G(s) H(s) for a stable
loop, is shown in
φ
shows the amount of phase margin that exists at the point
p
the gain drops below zero (the cutoff frequency wp of the
Figure 4
with a solid trace. The parameter
loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop bandwidth, wp, the loop response time would be approximately
.
halved. Because the filter attenuation at the comparison frequency also diminishes, the spurs would have increased by
approximately 6 dB. In the proposed Fastlock scheme, the
higher spur levels and wider loop filter conditions would exist
only during the initial lock-on phase— just long enough to
reap the benefits of locking faster. The objective would be to
open up the loop bandwidth but not introduce any additional
complications or compromises related to our original design
criteria. We would ideally like to momentarily shift the curve
Figure 4
over to a different cutoff frequency, illustrated by
dotted line, without affecting the relative open loop gain and
phase relationships. To maintain the same gain/phase relationship at twice the original cutoff frequency, other terms in
the gain and phase
sate by the corresponding “1/w” or “1/w
of
Equations (3), (4), (5)
Equations (5), (6)
will have to compen-
2
” factor. Examination
indicates the damping resistor variable R2 could be chosen to compensate with “w” terms for
the phase margin. This implies that another resistor of equal
value to R2 will need to be switched in parallel with R2 during
the initial lock period. We must also ensure that the magnitude of the open loop gain, H(s)G(s) is equal to zero at wp’
2 wp. K
changed by a factor of 4, to counteract with w
in the denominator of
,Kφ, N, or the net product of these terms can be
VCO
Equations (3), (4)
. The Kφ term was
chosen to complete the transformation because it can
readily be switched between 1X and 4X values. This is accomplished by increasing the charge pump output current
from 1 mA in the standard mode to 4 mA in Fastlock.
Fastlock Circuit Implementation
A diagram of the Fastlock scheme as implemented in National Semiconductors LMX2335/36/37 PLL is shown in
ure 5
. When a new frequency is loaded, and the RF1 I
is set high, the charge pump circuit receives an input to deliver 4 times the normal current per unit phase error while an
open drain NMOS on chip device switches in a second R2
resistor element to ground. The user calculates the loop filter
component values for the normal steady state considerations. The device configuration ensures that as long as a
second identical damping resistor is wired in appropriately,
the loop will lock faster without any additional stability considerations to account for. Once locked on the correct frequency, the user can return the PLL to standard low noise
operation by sending a MICROWIRE instruction with the
RF1 I
charge on the loop filter capacitors and is enacted synchro-
bit set low. This transition does not affect the
CPo
nous with the charge pump output. This creates a nearly
seamless change between Fastlock and standard mode.
2
term present
CPo
=
Fig-
bit
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Application Information (Continued)
FIGURE 4. Open Loop Response Bode Plot
DS012332-15
FIGURE 5. Fastlock PLL Architecture
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DS012332-18
Physical Dimensions inches (millimeters) unless otherwise noted
JEDEC 16-Lead (0.150" Wide) Small Outline Molded Package (M)
Order Number LMX2335M or LMX2337M
*
For Tape and Reel (2500 Units Per Reel)
Order Number LMX2335MX or LMX2337MX
NS Package Number M16A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TM)
Order Number LMX2335TM or LMX2337TM
*
For Tape and Reel (2500 Units Per Reel)
Order Number LMX2335TMX or LMX2337TMX
NS Package Number MTC16
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM)
Order Number LMX2336TM
*
For Tape and Reel (2500 Units Per Reel)
Order Number LMX2336TMX
NS Package Number MTC20
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Communications
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
LMX2335/LMX2336/LMX2337 PLLatinum Dual Frequency Synthesizer for RF Personal
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National Semiconductor
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