Datasheet LMX2324 Datasheet (National Semiconductor)

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LMX2324
PLLatinum
Personal Communications

™

2.0 GHz Frequency Synthesizer for RF

LMX2324 PLLatinum 2.0 GHz Frequency Synthesizer for RF Personal Communications

PRELIMINARY

November 1999

General Description

The LMX2324 is a high performance frequency synthesizer
with integrated 32/33 dual modulus prescaler designed for
RF operation up to 2.0 GHz. Using a proprietary digital
phase locked loop technique, the LMX2324’s linear phase
detector characteristics can generate very stable, low noise
control signals for UHF and VHF voltage controlled oscilla­tors.

Serial data is transferred into the LMX2324 via a three-line
MICROWIRE
range is from 2.7V to 5.5V. The LMX2324 features very low
current consumption, typically 3.5 mA at 3V. The charge
pump provides 4 mA output current.

The LMX2324 is manufactured using National’s ABiC V
BiCMOS process and is packaged in a 16-pin TSSOP and a
16-pin Chip Scale Package (CSP).

™

interface (Data, LE, Clock). Supply voltage

Functional Block Diagram

Features

n RF operation up to 2.0 GHz
n 2.7V to 5.5V operation
n Low current consumption: I

3.0V

n Dual modulus prescaler: 32/33
n Internal balanced, low leakage charge pump

= 3.5 mA (typ) at VCC=

CC

Applications

n Cellular telephone systems (GSM, NADC, CDMA, PDC)
n Personal wireless communications (DCS-1800, DECT,

CT-1+)

n Wireless local area networks (WLANs)
n Other wireless communication systems

DS101030-1

TRI-STATE®is a registered trademark of National SemiconductorCorporation.

™

MICROWIRE

© 1999 National Semiconductor Corporation DS101030 www.national.com

and PLLatinum™are trademarks of National Semiconductor Corporation.

Connection Diagrams

LMX2324

TSSOP 16-Pin Package

DS101030-2

Order Number LMX2324TM, LM2324TMX

See NS Package Number MTC16

CSP 16-Pin Package

Top View

Order Number LMX2324SLBX

See NS Package Number SLB16A

Pin Descriptions

Pin No.

TSSOP16 CSP16

21V
32CP

4 3 GND — Ground.
54f

65f
7 6 NC No Connect
8 7 NC No Connect
9 8 OSC

10 9 NC No Connect
12 10 Clock I High impedance CMOS Clock input. Data is clocked in on the rising edge,

13 11 Data I Binary serial data input. Data entered MSB first. LSB is control bit. High

14 12 LE I Load Enable input. When Load Enable transitions HIGH, data is loaded

15 13 NC No Connect
11 14 NC No Connect
16 15 CE I CHIP Enable. A LOW on CE powers down the device asynchronously and

116V

Pin

Name

P

o

INB

IN

CC

I/O Description

— Power supply for charge pump. Must be ≥ V

CC

O Internal charge pump output. For connection to a loop filter for driving the

voltage control input of an external oscillator.

I RF prescaler complimentary input. In single-ended mode, a bypass

capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane. The LMX2324 can be driven
differentially when the bypass capacitor is omitted.

I RF prescaler input. Small signal input from the voltage controlled oscillator.

I Oscillator input. A CMOS inverting gate input. The input has a VCC/2 input

in

threshold and can be driven from an external CMOS or TTL logic gate.

into the various counters and registers.

impedance CMOS input.

into either the N or R register (control bit dependent). See timing diagram.

will TRI-STATE

®

the charge pump output.

I Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass

capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.

DS101030-3

www.national.com 2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Power Supply Voltage (V
Power Supply for Charge Pump (V
Voltage on Any Pin with

GND=0V (V

) −0.3V to VCC+ 0.3V

I

Storage Temperature Range (T
Lead Temperature (solder, 4 sec.) (T
ESD - Human Body Model (Note 2) 2 kV

Electrical Characteristics (V

) −0.3V to 6.5V

CC

)V

P

) −65˚C to +150˚C

S

) +260˚C

L

CC

=

3V, V

CC

to 6.5V

P

Recommended Operating
Conditions

Power Supply Voltage (V
Power Supply for Charge Pump (V
Operating Temperature (T

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate condi­tions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test condi­tions, see the Electrical Characteristics.

Note 2: This device is a high performance RF integrated circuit and is ESD
sensitive. Handling and assembly of this device should on be done on ESD
protected workstations.

=

3V; −40˚C

<

T

A

(Note 1)

) 2.7V to 5.5V

CC

) −40˚C to +85˚C

A

<

85˚C except as specified).

)V

P

CC

to 5.5V

Symbol Parameter Conditions Min Typ Max Units

GENERAL

I

CC

I

-PWDN Power Down Current 10 µA

CC

f

IN

OSC

in

f

PD

Pf

IN

V

OSC

Power Supply Current VCC= 2.7V to 5.5V 3.5 mA

fINOperating Frequency 0.1 2.0 GHz
Oscillator Operating Frequency 5 40 MHz
Phase Detector Frequency 10 MHz
Input Sensitivity f

through a 10 pF capacitor

INB

grounded

VCC= 3.0V −15 0

= 5.0V −10 0

V

CC

Oscillator Sensitivity 0.4 1.0 VCC−0.3 V

CHARGE PUMP

ICP

o-source

ICP

o-sink

ICP

o-Tri

vs.

ICP

o

VCP

o

ICP

o-sink

ICP

o-source

vs. T Charge Pump Output Current

ICP

o

Charge Pump Output Current VCPo=VP/2 −4.0 mA

4.0 mA

Charge Pump TRI-STATE
Current

Charge Pump Output Current
Variation vs. Voltage (Note 4)

vs.

Charge Pump Output Current
Sink vs. Source Mismatch

0.5 ≤ VCPo≤ VP- 0.5
T = 25˚C

0.5 ≤ VCPo≤ VP- 0.5
T = 25˚C

o=VP

/2

VCP
T = 25˚C 5

0.1 nA

10

(Note 4)

Magnitude Variation vs.

VCP

−40˚C ≤ T ≤ +85˚C 10

o=VP

/2

Temperature (Note 4)

DIGITAL INTERFACE (DATA, CLK, LE, CE)

V

IH

V

IL

I

IH

I

IL

I

IH

I

IL

High-Level Input Voltage (Note 3) 0.8 V
Low-Level Input Voltage (Note 3) 0.2 V

CC

CC

High-Level Input Current VIH=VCC= 5.5V −1.0 1.0 µA
Low-Level Input Current VIL=0,VCC= 5.5V −1.0 1.0 µA
Oscillator Input Current VIH=VCC= 5.5V 100 µA

VIL=0,VCC= 5.5V −100 µA

MICROWIRE TIMING

t

CS

t

CH

t

CWH

t

CWL

t

ES

t

EW

Note 3: Except fINand OSC
Note 4: See related equations in charge pump current specification definitions

Data to Clock Set Up Time See Data Input Timing 50 ns
Data to Clock Hold Time See Data Input Timing 10 ns
Clock Pulse Width High See Data Input Timing 50 ns
Clock Pulse Width Low See Data Input Timing 50 ns
Clock to Enable Set Up Time See Data Input Timing 50 ns
Enable Pulse Width See Data Input Timing 50 ns

in

LMX2324

dBm

PP

%

%

%

V
V

www.national.com3

Charge Pump Current Specification Definitions

LMX2324

I1=CP sink current at VCP
I2=CP sink current at VCP
I3=CP sink current at VCP
I4=CP source current at VCP
I5=CP source current at VCP
I6=CP source current at VCP
∆V=Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V

vs. VCP

1. ICP

o

1

[

⁄

2. ICP
[|I2| − |I5|]/[

3. ICP
[|I2

o

*

2

{|I1| − |I3|}]/[1⁄

vs. ICP

o-sink

1

*

⁄

2

vs. T=Charge Pump Output Current magnitude variation vs. Temperature

o

@

temp| − |I2@25˚C|]/|I2@25˚C|*100%and [|I5@temp| − |I5@25˚C|]/|I5@25˚C|*100

=

− ∆V

V

o

P

=

/2

V

o

P

=

∆V

o

=

− ∆V

V

o

P

=

/2

V

o

P

=

∆V

o

=

Charge Pump Output Current magnitude variation vs. Voltage

*

2

{|I1| + |I3|}]*100%and [1⁄

=

Charge Pump Output Current Sink vs. Source Mismatch

o-source

{|I2| + |I5|}]*100

%

*

2

{|I4| − |I6|}]/[1⁄

*

2

{|I4| + |I6|}]*100

=

%

=

=

DS101030-4

and ground. Typical values are between 0.5V and 1.0V.

P

%

www.national.com 4

1.0 Functional Description

The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe­sizer such as the National Semiconductor LMX2324, a volt­age controlled oscillator (VCO), and a passive loop filter.The
frequency synthesizer includes a phase detector, current
mode charge pump, as well as programmable reference [R]
and feedback [N] frequency dividers. The VCO frequency is
established by dividing the crystal reference signal down via
the R counter to obtain a frequency that sets the comparison
frequency. This reference signal, f
input of a phase/frequency detector and compared with an­other signal, f
dividing the VCO frequency down by way of the N counter.

, the feedback signal, which was obtained by

p

The phase/frequency detector’s current source outputs
pump charge into the loop filter, which then converts the
charge into the VCO’s control voltage. The phase/frequency
comparator’s function is to adjust the voltage presented to
the VCO until the feedback signal’s frequency (and phase)
match that of the reference signal. When this “phase-locked”
condition exists, the RF VCO’s frequency will be N times that
of the comparison frequency, where N is the divider ratio.

1.1 OSCILLATOR

The reference oscillator frequency for the PLL is provided by
an external reference TCXO through the OSC
block can operate to 40 MHz with a minimum input sensitivity
of 0.4V

. The inputs have a VCC/2 input threshold and can

PP

be driven from an external CMOS or TTL logic gate.

1.2 REFERENCE DIVIDERS (R COUNTER)

The R Counter is clocked through the oscillator block. The
maximum frequency is 40 MHz. The R Counter is a 10 bit
CMOS binary counters with a divide range from 2 to 1,023.
See programming description 2.2.1.

1.3 PROGRAMMABLE DIVIDERS (N COUNTER)

The N counter is clocked by the small signal f
pins. The LMX2324 RF N counter is 15 bit integer divider.
The N counter is configured as a 5 bit A Counter and a 10 bit
B Counter, offering a continuous integer divide range from
992 to 32,767. The LMX2324 is capable of operating from
100 MHz to 2.0 GHz with a 32/33 prescaler.

1.3.1 Prescaler

The RF inputs to the prescaler consist of the f
which are the complimentary inputs of a differential pair am­plifier.The differential f
with an input sensitivity of −15 dBm. The input buffer drives

IN

the N counter’s ECL D-type flip flops in a dual modulus con­figuration. A 32/33 prescale ratio is provided for the
LMX2324. The prescaler clocks the subsequent CMOS flip­flop chain comprising the fully programmable A and B
counters.

1.4 PHASE/FREQUENCY DETECTOR

The phase(/frequency) detector is driven from the N and R
counter outputs. The maximum frequency at the phase de­tector inputs is 10 MHz. The phase detector outputs control
the charge pumps. The polarity of the pump-up or pump­down control is programmed using PD_POL, depending on
whether RF VCO characteristics are positive or negative
(see programming description 2.2.2). The phase detector
also receives a feedback signal from the charge pump, in or­der to eliminate dead zone.

, is then presented to the

r

pin. OSC

in

and f

and f

input

INB

pins

INB

IN

IN

configuration can operate to 2 GHz

1.5 CHARGE PUMP

The phase detector’s current source output pumps charge
into an external loop filter, which then converts the charge
into the VCO’s control voltage. The charge pumps steer the
charge pump output, CP
(pump-down). When locked, CP
mode with small corrections. The RF charge pump output

,toVP(pump-up) or Ground

o

is primarily in a TRI-STATE

o

current magnitude is set to 4.0 mA. The charge pump output
can also be used to output divider signals as detailed in sec­tion 2.2.3.

1.6 MICROWIRE SERIAL INTERFACE

The programmable functions are accessed through the
MICROWIRE serial interface. The interface is made of three
functions: clock, data and latch enable (LE). Serial data for
the various counters is clocked in from data on the rising
edge of clock, into the 18-bit shift register. Data is entered
MSB first. The last bit decodes the internal register address.
On the rising edge of LE, data stored in the shift register is
loaded into one of the two appropriate latches (selected by
address bits). A complete programming description is in­cluded in the following sections.

1.7 POWER CONTROL

The PLL can be power controlled in two ways. The first
method is by setting the CE pin LOW. This asynchronously

in

powers down the PLL and TRI-STATE the charge pump out­put, regardless of the PWDN bit status. The second method
is by programming through MICROWIRE, while keeping the
CE HIGH. Programming the PWDN bit in the N register
HIGH (CE=HIGH) will disable the N counter and de-bias the
f

input (to a high impedance state). The R counter function-

IN

ality also becomes disabled. The reference oscillator block
powers down when the power down bit is asserted. The
OSC

pin reverts to a high impedance state when this con-

in

dition exists. Power down forces the charge pump and
phase comparator logic to a TRI-STATE condition.A power
down counter reset function resets both N and R counters.
Upon powering up the N counter resumes counting in “close”
alignment with the R counter (The maximum error is one
prescaler cycle). The MICROWIRE control register remains
active and capable of loading and latching in data during all
of the power down modes.

LMX2324

www.national.com5

2.0 Programming Description

2.1 MICROWIRE INTERFACE

LMX2324

The LMX2324 register set can be accessed through the MICROWIRE interface. A 18-bit shift register is used as a temporary reg­ister to indirectly program the on-chip registers. The shift register consists of a 17-bit DATA[16:0] field and a 1-bit address (ADDR)
field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift register in
the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Load Enable (LE) signal, data stored
in the shift register is loaded into the addressed latch.

MSB LSB

DATA[16:0] ADDR

17 1 0

2.1.1 Registers’ Address Map

When Load Enable (LE) is transitioned high, data is transferred from the 18-bit shift register into the appropriate latch depending
on the state of the ADDRESS bit. A multiplexing circuit decodes the address bit and writes the data field to the corresponding in­ternal register.

REGISTER

ADDRESSED

R Register 1
N Register 0

ADDRESS BIT

ADDR

www.national.com 6

2.0 Programming Description (Continued)

2.1.2 Register Content Truth Table

MSB SHIFT REGISTER BIT LOCATION LSB

Register

17161514 131211109876543 2 1 0

N

N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0

X X X TEST RS PD_

R

R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

NB_CNTR[9:0] NA_CNTR[4:0] CTL_WORD[1:0]

POL

2.2 R REGISTER

If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into the 14-bit R reg­ister. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide ratio is programmed using the
bits R_CNTR as shown in table 2.2.1. The ratio must be ≥ 2. The PD_POL, CP_TRI and TEST bits control the phase detector po­larity, charge pump TRI-STATE, and test mode respectively, as shown in 2.2.2. The RS bit is reserved and should always be set
to zero. X denotes a don’t care condition. Data is clocked into the shift register MSB first.

MSB SHIFT REGISTER BIT LOCATION LSB

Register

171615 14 1312 1110987654321 0

X X X TEST RS PD_

R

R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

POL

2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter)

Divide Ratio R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

2 0000000010
3 0000000011

• ••••••••••

1,023 1111111111

Notes: Divide ratio: 2 to 1,023 (Divide ratios less than 2 are prohibited)
R_CNTR— These bits select the divide ratio of the programmable reference dividers.

Data Field ADDR Field

CP_

TRI

Data Field ADDR Field

CP_

TRI

R_CNTR[9:0]

R_CNTR[9:0]

R_CNTR[9:0]

LMX2324

0

1

1

2.2.2 R Register Truth Table

Bit Location Function 0 1

CP_TRI R[10] Charge Pump TRI-STATE Normal Operation TRI-STATE
PD_POL R[11] Phase Detector Polarity Negative Positive
TEST R[13] Test Mode Bit Normal Operation Test Mode

If the test mode is NOT activated (R[13]=0), the charge pump is active when CP_TRI is set LOW. When CP_TRI is set HIGH, the
charge pump output and phase comparator are forced to a TRI-STATE condition. This bit must be set HIGH if the test mode is
ACTIVATED (R[13]=1).

If the test mode is NOT activated (R[13]=0), PD_POL sets the VCO characteristics to positive when set HIGH. When PD_POL
is set LOW, the VCO exhibits a negative characteristic where the VCO frequency decreases with increasing control voltage.

If the test mode is ACTIVATED (R[13]=1), the outputs of the N and R counters are directed to the CP
The PD_POL bit selects which counter output according to Table 2.2.3.

output to allow for testing.

o

2.2.3 Test Mode Truth Table (R[13]=1)

CPoOutput CP_TRI R[10] PD_POL R[11]

R Divider Output 1 0
N Divider Output 1 1

www.national.com7

2.0 Programming Description (Continued)

2.3 N REGISTER

LMX2324

If the address bit is LOW (ADDR=0) when LE is transitioned high, data is transferred from the 18-bit shift register into the 17-bit
N register. The N register consists of the 5-bit swallow counter (A counter), the 10-bit programmable counter (B counter) and the
control word. Serial data format is shown below in tables 2.3.1 and 2.3.2. The pulse swallow function which determines the divide
ratio is described in section 2.3.3. Data is clocked into the shift register MSB first.

MSB SHIFT REGISTER BIT LOCATION LSB

Register

17161514131211109876543 2 1 0

N

N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0

NB_CNTR[9:0] NA_CNTR[4:0] CTL_WORD[1:0]

2.3.1 5-Bit Swallow Counter Divide Ratio (A Counter)

Swallow Count NA_CNTR[4:0]

(A) N6 N5 N4 N3 N2

0 00000
1 00001

• •••••

31 11111

Notes: Swallow Counter Value: 0 to 31
NB_CNTR ≥ NA_CNTR

2.3.2 10-Bit Programmable Counter Divide Ratio (B Counter)

Divide Ratio N16 N15 N14 N13 N12 N11 N10 N9 N8 N7

3 0000000011
4 0000000100

• ••••••••••

1023 1111111111

Notes: Divide ratio: 3 to 1,023 (Divide ratios less than 3 are prohibited)
NB_CNTR ≥ NA_CNTR

Data Field ADDR Field

NB_CNTR[10:0]

0

2.3.3 Pulse Swallow Function

The N divider counts such that it divides the VCO RF frequency by (P+1) Atimes, and then divides by P (B - A) times. The B value
(NB_CNTR) must be ≥ 3. The continuous divider ratio is from 992 to 32,767. Divider ratios less than 992 are achievable as long
as the binary counter value is greater than the swallow counter value (NB_CNTR ≥ NA_CNTR).

f

VCO

=Nx(f

OSC

/R)

N=(PxB)+A

: Output frequency of external voltage controlled oscillator (VCO)

f

VCO

: Output frequency of the external reference frequency oscillator

f

OSC

R: Preset divide ratio of binary 10-bit programmable reference counter (2 to 1023)
N: Preset divide ratio of main 15-bit programmable integer N counter (992 to 32,767)
B: Preset divide ratio of binary 10-bit programmable B counter (3 to 1023)
A: Preset value of binary 5-bit swallow A counter (0 ≤ A ≤ 31, A ≤ B)
P: Preset modulus of dual modulus prescaler (P=32)

2.3.4 CTL_WORD

MSB LSB

N1 N0

CNT_RST PWDN

www.national.com 8

2.0 Programming Description (Continued)

2.3.4.1 Control Word Truth Table

CE CNT_RST PWDN Function

1 0 0 Normal Operation
1 0 1 Synchronous Powerdown
1 1 0 Counter Reset
1 1 1 Asynchronous Powerdown
0 X X Asynchronous Powerdown

Notes: X denotes don’t care.

The Counter Reset enable bit when activated allows the reset of both N and R counters. Upon powering up the N counter re­sumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle).

Both synchronous and asynchronous power down modes are available with the LMX2324 to be able to adapt to different types
of applications. The MICROWIRE control register remains active and capable of loading and latching in data during all of the pow­erdown modes.

Synchronous Power down Mode

The PLL loops can be synchronously powered down by setting the counter reset mode bit to LOW (N[1] = 0) and its power down
mode bit to HIGH (N[0] = 1). The power down function is gated by the charge pump. Once the power down mode and counter
reset mode bits are loaded, the part will go into power down mode upon the completion of a charge pump pulse event.

Asynchronous Power down Mode

The PLL loops can be asynchronously powered down by setting the counter reset mode bit to HIGH (N[1] = 1) and its power down
mode bit to HIGH (N[0] = 1), or by setting CE pin LOW. The power down function is NOT gated by the charge pump. Once the
power down and counter reset mode bits are loaded, the part will go into power down mode immediately.

The R and N counters are disabled and held at load point during the synchronous and asynchronous power down modes. This
will allow a smooth acquisition of the RF signal when the PLL is programmed to power up. Upon powering up, both R and N
counters will start at the ‘zero’ state, and the relationship between R and N will not be random.

LMX2324

Serial Data Input Timing

Notes: Parenthesis data indicates programmable reference divider data.

Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V

amplitudes of 1.6V@VCC= 2.7V and 3.3V@VCC= 5.5V.

DS101030-5

/2. The test waveform has an edge rate of 0.6 V/ns with

CC

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Phase Comparator and Internal Charge Pump Characteristics

LMX2324

Notes: Phase difference detection range: −2π to +2π

The minimum width pump up and pump down current pulses occur at the CP

: Phase comparator input from the R Divider

f

R

: Phase comparator input from the N divider

f

N

: Charge pump output

CP

o

pin when the loop is locked. PD_POL = 1

o

DS101030-6

www.national.com 10

Physical Dimensions inches (millimeters) unless otherwise noted

LMX2324

16-Pin Thin Shrink Small Outline Package
Order Number LMX2324TM, LMX2324TMX

NS Package Number MTC16

www.national.com11

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Pin Chip Scale Package
Order Number LMX2324SLBX
NS Package Number SLB16A

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

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whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a

LMX2324 PLLatinum 2.0 GHz Frequency Synthesizer for RF Personal Communications

significant injury to the user.

National Semiconductor
Corporation

Americas
Tel: [phone]
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