National Semiconductor LMX2323 Technical data

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LMX2323

LMX2323 PLLatinum 2.0 GHz Frequency Synthesizer for RF Personal Communications

October 2000

PLLatinum

™

2.0 GHz Frequency Synthesizer for RF

Personal Communications

General Description

The LMX2323 is a high performance frequency synthesizer with integrated 32/33 dual modulus prescaler designed for RF operation up to 2.0 GHz. Using a proprietary digital phase locked loop technique, the LMX2323’s linear phase detector characteristics can generate very stable, low noise control signals for UHF and VHF voltage controlled oscillators.

Serial data is transferred into the LMX2323 via a three-line MICROWIRE range is from 2.7V to 5.5V. The LMX2323 features very low curent consumption, typically 3.5mAat3V.Thecharge pump provides 4 mA output current.

The LMX2323 is manufactured using National’s ABiC V BiCMOS process and is packaged in a 16-pin TSSOP.

Functional Block Diagram

™

interface (Data, LE, Clock). Supply voltage

Features

n RF operation up to 2.0 GHz n 2.7V to 5.5V operation n Low current consumption: Icc = 3.5mA (typ) at

Vcc=3.0V

n Digital Lock Detect n Dual modulus prescaler: 32/33 n Internal balanced, low leakage charge pump

Applications

n Cellular telephone systems (GSM, NADC, CDMA, PDC,

PHS)

n Personal wireless communications (DCS-1800, DECT,

CT-1+)

n Wireless local area networks (WLANs) n DCS/PCS infrastructure equipment n Other wireless communication systems

DS101362-1

TRI-STATE®is a registered trademark of National Semiconductor Corporation. MICROWIRE

™

and PLLatinum™are trademarks of National Semiconductor Corporation.

Connection Diagram

LMX2323

Pin Descriptions

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Top View

Order Number LMX2323TM, LMX2323TMX

See NS Package Number MTC16

Pin No.

1 OSC

Name

I/O Description

I Oscillator input. A CMOS inverting gate input. The input has a VCC/2 input threshold

and can be driven from an external CMOS or TTL logic gate. 3V 4V

— Power supply for charge pump. Must be ≥ VCC. — Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors

should be placed as close as possible to this pin and be connected directly to the

ground plane. 5CP

O Internal charge pump output. For connection to a loop filter for driving the voltage

control input of an external oscillator. 6 GND — Ground. 7f

INB

I RF prescaler complimentary input. In single-ended mode, a bypass capacitor should

be placed as close as possible to this pin and be connected directly to the ground

plane. The LMX2323 can be driven differentially when a bypass capacitor is omitted. 8f

I RF prescaler input. Small signal input from the voltage controlled oscillator.

9 Clock I High impedance CMOS Clock input. Data is clocked in on the rising edge, into the

various counters and registers.

10 Data I Binary serial data input. Data entered MSB first. LSB is control bit. High impedance

CMOS input.

11 LE I Load Enable input. When Load Enable transitions HIGH, data is loaded into either the

N or R register (control bit dependent). See timing diagram.

12 CE I PLL Enable. A LOW on CE powers down the device asynchronously and

TRI-STATE

s the charge pump output.

14 LD O Lock detect output. This pin can be programmed to provide R counter output, N

counter output, digital lock detect (CMOS logic) or analog lock detect (open drain).

2, 13,

NC No Connect.

15, 16

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LMX2323

Absolute Maximum Ratings (Note 1)

Power Supply Voltage (V Power Supply for Charge Pump (V Voltage on Any Pin with

GND=0V(V

) −0.3V to VCC+ 0.5V

Storage Temperature Range (T Lead Temperature (solder, 4 sec.) (T ESD - Whole Body Model (Note 2) 2 kV

) −0.3V to 6.5V

) −65˚C to +150˚C

) +260˚C

to 6.5V

Recommended Operating Conditions

Power Supply Voltage (V Power Supply for Charge pump (V Operating Temperature (T

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Conditions indicate conditions for which the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should be done on ESD protected workstations.

(Note 1)

) 2.7V to 5.5V

) −40˚C to +85˚C

to 5.5V

Electrical Characteristics

VCC= 3.0V, VP= 3.0V; −40˚C<T

Symbol Parameter Conditions Min Typ Max Units

GENERAL I

-PWDN VCC= 5.5V (Note 3) 10 20 µA

OSC

Power Supply Current VCC= 3.0V 3.5 mA

RF Operating Frequency 0.1 2.0 GHz

Oscillator Frequency 5 40 MHz fφ Phase Detector Frequency 10 MHz Pf

OSC

RF Input Sensitivity 2.7V≤Vcc≤ 3.0V -15 0 dBm

Oscillator Sensitivity 0.4 0.8 VCC-0.3 V

Phase Noise (Note 4) fIN= 900 MHz, V

CHARGE PUMP I

CPo-source

CPo-sink

CPo-Tri

Charge Pump Output Current V

Charge Pump TRI-STATE

Current I

CPo

CPo-sink

CPo-source

vs T Charge Pump Output Current

CPo

Charge Pump Output Current

Magnitude Variation vs Voltage

Charge Pump Output Current

Sink vs Source Mismatch

Magnitude Variation vs

Temperature DIGITAL INTERFACE (DATA, CLK,LE, CE) V

High-Level Output Voltage IOH= −500 µA VCC−0.4 V

Low-Level Output Voltage IOL= −500 µA 0.4 V

High-Level Input Voltage

(Note 5) V

Low-Level Input Voltage (Note 5) 0.2Vcc V

High-Level Input Current (Clock,

Data, Load Enable) I

Low-Level Input Current (Clock,

Data, Load Enable) I

Oscillator Input Current VIH=VCC= 5.5V 100 µA

Oscillator Input Current VIL=0,VCC= 5.5V −100 µA

85˚C except as specified.

VCC= 2.7V to 5.5V 7.0 mA

3.0

= 900 MHz, V

= 1800 MHz, V

CPo=VP

0.5 ≤ V

0.5 ≤ V = 25˚C

CPo=VP

= 25˚C

CPo=VP

VIH=VCC= 5.5V

VIL=0,VCC= 5.5V

Vcc≤5.0V -10 0 dBm

PP OSC OSC

OSC OSC

≥ 0.8 V ≥ 0.4 V

PP PP

−86

−82

−80

(Note 6) dBc/Hz

/2 −4.3 mA /2 4.3 mA

≤ VP- 0.5

CPo

≤ VP- 0.5

−2.5 2.5 nA

10 %

0.8Vcc V

−1.0 1.0 µA

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Electrical Characteristics (Continued)

VCC= 3.0V, VP= 3.0V; −40˚C<T

LMX2323

Symbol Parameter Conditions Min Typ Max Units

MICROWIRE TIMING t

CWH

CWL

Note 3: This ICC-PWDN represents CLK, DATA, LE and CE being tied to either higher than 0.8 VCCor lower than 0.2 VCC. Note 4: Phase noise is measured 1 kHz off from the carrier frequency. Comparison frequency is 200 kHz. OSC Note 5: Except f Note 6: Typical values are determined from measurements on the reference evaluation boards. A 3 dB (3 sigma) degradation is estimated from statistical distribution

in manufacturing. Units will NOT be tested in production.

Data to Clock Set Up Time See Data Input Timing 50 ns Data to Clock Hold Time See Data Input Timing 10 ns Clock Pulse Width High See Data Input Timing 50 ns Clock Pulse Width Low See Data Input Timing 50 ns Clock to Enable Set Up Time See Data Input Timing 50 ns Enable Pulse Width See Data Input Timing 50 ns

and OSCIN.

85˚C except as specified.

frequency is 13 MHz.

Charge Pump Current Specification Definitions

I1 = CP sink current at VCPo=VP−∆V I2 = CP sink current at VCP I3 = CP sink current at VCP I4 = CP source current at VCP I5 = CP source current at VCP I6 = CP source current at VCP ∆V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V

vs VCPo= Charge Pump Output Current magnitude variation vs Voltage =

1. ICP

⁄

{|I1| − |I3|}] / [1⁄

[

2. ICP

3. ICP

vs ICP

o-sink

[|I2| − |I5|] / [

vs TA= Charge Pump Output Current magnitude variation vs Temperature =

temp| − |I2@25˚C|] / |I2@25˚C|*100% and [|I5@temp| − |I5@25˚C|] / |I5@25˚C|*100%

[|I2

o-source

⁄

{|I2| + |I5|}]*100%

o=VP

= ∆V

−∆V

o=VP

= ∆V

{|I1| + |I3|}]*100% and [1⁄

= Charge Pump Output Current Sink vs Source Mismatch =

{|I4| − |I6|}] / [1⁄

{|I4| + |I6|}]*100%

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DS101362-4

and ground. Typical values are between 0.5V and 1.0V.

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