National Semiconductor LMX1600, LMX1601, LMX1602 Technical data

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LMX1600/LMX1601/LMX1602 PLLatinum Low Cost Dual Frequency Synthesizer

LMX1600/LMX1601/LMX1602
PLLatinum

LMX1600 2.0 GHz/500 MHz
LMX1601 1.1 GHz/500 MHz
LMX1602 1.1 GHz/1.1 GHz

General Description

The LMX1600/01/02 is part of a family of monolithic inte­grated dual frequency synthesizers designed to be used in a
local oscillator subsystem for a radio transceiver. It is fabri­cated using National’s 0.5uABiCVsilicon BiCMOS process.

The LMX1600/01/02 contains two dual modulus prescalers,
four programmable counters, two phase detectors and two
selectable gain charge pumps necessary to provide the con­trol voltage for two external loop filters and VCO loops. Digi­tal filtered lock detects for both PLLs are included. Data is
transferred into the LMX1600/01/02 via a MICROWIRE
serial interface (Data, Clock, LE).

supply voltage can range from 2.7V to 3.6V. The

V

CC

LMX1600/01/02 features very low current consumption ­typically 4.0 mA at 3V for LMX1601, 5.0 mA at 3V for
LMX1600 or LMX1602. Powerdown for the PLL is hardware
controlled.

The LMX1600/01/02 is available in a 16 pin TSSOP surface
mount plastic package.

™

Low Cost Dual Frequency Synthesizer

™

PRELIMINARY

March 1998

Features

n VCC= 2.7V to 3.6V operation
n Low current consumption:

@

4mA

3V (typ) for LMX1601

@

5mA

n PLL Powerdown mode: I
n Dual modulus prescaler:

n Digital Filtered Lock Detects

3V (typ) for LMX1600 or LMX1602

— 2 GHz/500 MHz option: (Main) 32/33 (Aux) 8/9
— 1.1 GHz/500 MHz option: (Main) 16/17 (Aux) 8/9
— 1.1 GHz/1.1 GHz option: (Main) 16/17 (Aux) 16/17

= 1 µA typical

CC

Applications

n Cordless / Cellular / PCS phones
n Other digital mobile phones

Functional Block Diagram

DS100129-1

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

™

MICROWIRE

© 1998 National Semiconductor Corporation DS100129 www.national.com

and PLLatinum™are trademarks of National Semiconductor Corporation.

Connection Diagram

DS100129-2

Order Number LMX1600TM, LMX1601TM, or LMX1602TM

NS Package Number MTC16

Pin Description

Pin

Pin Name I/O Description

No.

1 FoLD O Multiplexed output of the Main/Aux programmable or reference dividers and Main/Aux lock

2 OSC

3 OSC

IN

OUT

O Oscillator output. Used with an external resonator.
4 GND — Aux PLL ground.
5 fin

AUX

6V

CC

AUX

7 CPo

8EN

9EN

10 CPo

11 V

12 fin

CC

AUX

AUX

MAIN

MAIN

MAIN

MAIN

— Aux PLL power supply voltage input. Must be equal to V

O Aux PLL Charge Pump output. Connected to a loop filter for driving the control input of an

O Main PLL Charge Pump output. Connected to a loop filter for driving the control input of an

— Main PLL power supply voltage input. Must be equal to V

13 GND — Main PLL ground.
14 LE I Load enable high impedance CMOS input. Data stored in the shift registers is loaded into

15 Data I High impedance CMOS input. Binary serial data input. Data entered MSB first. The last two

16 Clock I High impedance CMOS Clock input. Data for the various counters is clocked in on the

detect. CMOS output. (See Programming Description 2.5)

I PLL reference input which drives both the Main and Aux R counter inputs. Has about 1.2V

input threshold and can be driven from an external CMOS or TTL logic gate. Typically
connected to a TCXO output. Can be used with an external resonator (See Programming
Description 2.5.4).

I Aux prescaler input. Small signal input from the VCO.

. May range from 2.7V to

CC

3.6V. Bypass capacitors should be placed as close as possible to this pin and be

MAIN

connected directly to the ground plane.

external VCO.

I Powers down the Aux PLL when LOW (N and R counters, prescaler, and tristates charge

pump output). Bringing EN

HIGH powers up the Aux PLL.

AUX

I Powers down the Main PLL when LOW (N and R counters, prescaler, and tristates charge

pump output). Bringing EN

HIGH powers up the Main PLL.

MAIN

external VCO.

. May range from 2.7V to

CC

3.6V. Bypass capacitors should be placed as close as possible to this pin and be

AUX

connected directly to the ground plane.

I Main prescaler input. Small signal input from the VCO.

one of the 4 internal latches when LE goes HIGH (control bit dependent).

bits are the control bits.

rising edge, into the 18-bit shift register.

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Value

Parameter Symbol Min Typical Max Unit

V

CC

Power Supply Voltage V
Voltage on any pin with GND=0V V
Storage Temperature Range T
Lead Temp. (solder 4 sec) T

MAIN

CC

AUX

I
S
L

−0.3 6.5 V

−0.3 6.5 V

−0.3 VCC+ 0.3 V

−65 +150 ˚C
+260 ˚C

ESD-Human Body Model (Note 2) 2000 eV

Recommended Operating Conditions

Value

Parameter Symbol Min Typical Max Unit

V

CC

Power Supply Voltage V
Operating Temperature T

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. Electrical Characteristics document specific minimum and/or maxi­mum performance values at specified test conditions and are guaranteed. Typical values are for informational purposes only - based on design parameters or device
characterization and are not guaranteed.

Note 2: This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should only be done on ESD-free work­stations.

MAIN

CC

AUX

A

2.7 3.6 V

V

CC

MAIN

V

CC

MAIN

−40 +85 ˚C

V

Electrical Characteristics

(V

=V

CC

MAIN

Symbol Parameter Conditions Min Typ Max Units

GENERAL

I

CC

I

CC-PWDN

fin fin Operating Frequency fin Main 2 GHz Option 200 2000 MHz

OSC

IN

V

OSC

fφ Maximum Phase Detector Frequency 10 MHz
Pfin Main and Aux RF Input Sensitivity −15 0 dBm

CHARGE PUMP

ICP

o-source

ICP

o-sink

ICP

o-source

ICP

o-sink

ICP

o-Tri

DIGITAL INTERFACE (DATA, CLK, LE, EN, FoLD)
V

IH

V

IL

= 3.0V; TA= 25˚C except as specified)

CC

AUX

Power
Supply
Current

2 GHz + 500 MHz Crystal Mode (Note 3) 5.0 mA

1.1 GHz + 500 MHz Crystal Mode (Note 3) 4.0 mA

1.1 GHz + 1.1 GHz Crystal Mode (Note 3) 5.0 mA
2 GHz Only Crystal Mode (Note 3) 3.5 mA

1.1 GHz Only Crystal Mode (Note 3) 2.5 mA
500 MHz Only Crystal Mode (Note 3) 1.5 mA

Power Down Current EN

MAIN

= LOW, EN

= LOW 1 µA

AUX

fin Main and Aux 1.1 GHz Option 100 1100 MHz
fin Aux 500 MHz Option 40 500 MHz

Oscillator Operating Frequency Logic Mode (Note 3) 1 40 MHz

Crystal Mode (Note 3) 1 20 MHz

Oscillator Input Sensitivity 0.5 V

RF Charge Pump Output Current
(See Programming Description 2.4)

VCPo = VCC/2, High Gain Mode −1600 µA
VCPo = VCC/2, High Gain Mode 1600 µA

CC

VCPo = VCC/2, Low Gain Mode −160 µA
VCPo = VCC/2, Low Gain Mode 160 µA

Charge Pump TRI-STATE®Current 0.5 ≤ VCPo≤ VCC−0.5 1 nA

High-Level Input Voltage 0.8V
Low-Level Input Voltage 0.2V

CC

CC

V

PP

V
V

3 www.national.com

Electrical Characteristics (Continued)

(V

=V

CC

MAIN

Symbol Parameter Conditions Min Typ Max Units

DIGITAL INTERFACE (DATA, CLK, LE, EN, FoLD)

I

IH

I

IL

I

IH

I

IL

I

O

V

OH

V

OL

MICROWIRE TIMING

t

CS

t

CH

t

CWH

t

CWL

t

ES

t

EW

CLOSED LOOP SYNTHESIZER PERFORMANCE (NSC evaluation board only)
RFφ

n

Note 3: Refer to Programming Description 2.5.3.
Note 4: Except fin.
Note 5: The OSCout Output Current Magnitude is lass than or equal to 200µA when the Logic Mode is selected. The OSCout Output Current Magnitude is greater

than or equal to 300µA when the Crystal Mode is selected.
Note 6: Offset frequency = 1 kHz, fin = 900 MHz, fφ = 25 kHz, N = 3600, f

of phase noise floor measurement.

= 3.0V; TA= 25˚C except as specified)

CC

AUX

High-Level Input Current VIH=VCC= 3.6V, (Note 4) −1.0 1.0 µA
Low-Level Input Current VIL= 0V; VCC= 3.6V, (Note 4) −1.0 1.0 µA
OSCINInput Current VIH=VCC= 3.6V 100 µA
OSCINInput Current VIL= 0V; VCC= 3.6V −100 µA
OSC

Output Current Magnitude

OUT

(sink/source) (Note 5)

V

OUT=VCC

Logic Mode

= 3.6V

V

CC

(Note 3)

/2 Crystal Mode

= 2.7V

V

CC

(Note 3)

|200| µA

|300| µA

High-Level Output Voltage IOH= −500 µA VCC−0.4 V
Low-Level Output Voltage IOL= 500 µA 0.4 V

Data to Clock Set Up Time See Data Input Timing 50 ns
Data to Clock Hold Time See Data Input Timing 10 ns
Clock Pulse Width High See Data Input Timing 50 ns
Clock Pulse Width Low See Data Input Timing 50 ns
Clock to Load Enable Set Up Time See Data Input Timing 50 ns
Load Enable Pulse Width See Data Input Timing 50 ns

Main PLL Phase Noise Floor (Note 6) −160 dBc/Hz

OSC

= 10 MHz, V

>

1.2 VPP. Refer to the Application Note, AN-1052, for description

OSC

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1.0 Functional Description

The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe­sizer such as the National Semiconductor LMX1600/01/02, a
voltage controlled oscillator (VCO), and a passive loop filter.
The frequency synthesizer includes a phase detector, cur­rent mode charge pump, as well as programmable reference
[R], and feedback [N] frequency dividers. The VCO fre­quency is established by dividing the crystal reference signal
down via the R counter to obtain the comparison frequency.
This reference signal, fr, is then presented to the input of a
phase/frequency detector and compared with another signal,
fp, the feedback signal, which was obtained by dividing the
VCO frequency down using the N counter. The phase/
frequency detector’s current source outputs pump charge
into the loop filter, which then converts the charge into the
VCO’s control voltage. The phase/frequency comparator’s
function is to adjust the voltage presented to the VCO until
the feedback signal’s frequency (and phase) match that of
the reference signal. When this “phase-locked” condition ex­ists, the VCO’s frequency will be N times that of the compari­son frequency, where N is the divider ratio.

1.1 REFERENCE OSCILLATOR INPUTS

The reference oscillator frequency for the Main and Aux
PLL’s is provided by either an external reference through the
OSC

pin with the OSC

IN

to a 30 pF capacitor to ground in Logic Mode, or an external
crystal resonator across the OSC
Crystal Mode (See Programming Description 2.5.3). The
OSC

input can operate to 40 MHz in Logic Mode or to 20

IN

MHz in Crystal Mode with an input sensitivity of 0.5 V
OSC

pin drives the Main and Aux R counters. The inputs

IN

z

have a

1.2V input threshold and can be driven from an ex­ternal CMOS or TTL logic gate. The OSC
connected to the output of a Temperature Compensated

pin not connected or connected

OUT

and OSC

IN

OUT

pin is typically

IN

pins in

. The

PP

Crystal Oscillator (TCXO).

1.2 REFERENCE DIVIDERS (R COUNTERS)

The Main and Aux R Counters are clocked through the oscil­lator block in common. The maximum frequency is 40 MHz
in Logic Mode or 20 MHz in crystal Mode. Both R Counters
are 12-bit CMOS counters with a divide range from 2 to
4,095. (See Programming Description 2.2)

1.3 FEEDBACK DIVIDERS (N COUNTERS)

The Main and Aux N Counters are clocked by the small sig­nal fin Main and fin Aux input pins respectively. These inputs
should be AC coupled through external capacitors. The Main
N counter has an 16-bit equivalent integer divisor configured
as a 5-bit A Counter and an 11-bit B Counter offering a con­tinuous divide range from 992 to 65,535 (2 GHz option) or a
4-bit A Counter and a 12-bit B Counter offering a continuous
divide range from 240 to 65,535 (1.1 GHz option). The Main
N divider incorporates a 32/33 dual modulus prescaler ca­pable of operation from 200 MHz to 2.0 GHz or a 16/17 dual
modulus prescaler capable of operation from 100 MHz to

1.1 GHz.
The Aux N divider operates from 100 MHz to 1.1 GHz with a

16/17 prescaler or from 40 MHz to 500 MHz with a 8/9 pres­caler. The Aux N counter is a 16-bit integer divider fully pro­grammable from 240 to 65,535 over the frequency range of
100 MHz to 1.1 GHz or from 56 to 32,767 over the frequency
range of 40 MHz to 550 MHz. The Aux N counter is config-

ured as a 4-bit A Counter and a 12-bit B Counter. These in­puts should be AC coupled through external capacitors. (See
Programming Description 2.3)

1.3.1 Prescalers

The RF input to the prescalers consists of the fin pins which
are one of two complimentary inputs to a differential pair am­plifier. The complimentary inputs are internally coupled to
ground with a 10 pF capacitor and not brought out to a pin.
The input buffer drives the A counter’s ECL D-type flip flops
in a dual modulus configuration. A 32/33 for 2.0 GHz option,
16/17 for 1.1 GHz option, or 8/9 for 500 MHz option prescale
ratio is provided for the LMX1600/01/02. The prescaler
clocks the subsequent CMOS flip-flop chain comprising the
fully programmable A and B counters.

1.4 PHASE/FREQUENCY DETECTOR

The Main and Aux phase(/frequency) detectors are driven
from their respective N and R counter outputs. The maxi­mum frequency at the phase detector inputs is 10 MHz (un­less limited by the minimum continuous divide ratio of the
multi modulus prescalers). The phase detector outputs con­trol the charge pumps. The polarity of the pump-up or pump­down control is programmed using Main_PD_Pol or
Aux_PD_Pol depending on whether Main orAux VCO char­acteristics are positive or negative. (See Programming De­scription 2.4) The phase detector also receives a feedback
signal from the charge pump in order to eliminate dead zone.

1.5 CHARGE PUMP

The phase detector’s current source outputs pump charge
into an external loop filter, which then converts the charge
into the VCO’s control voltage. The charge pumps steer the
charge pump output, CPo, to V
(pump-down). When locked, CPo is primarily in a

(pump-up) or ground

CC

TRI-STATE mode with small corrections. The charge pump
output current magnitude can be selected as 160 µA or 1600
µA using bits AUX_CP_GAIN and MAIN_CP_GAIN as
shown in Programming Description 2.4.

1.7 MICROWIRE SERIAL INTERFACE

The programmable functions are accessed through the MI­CROWIRE serial interface. The interface is made of 3 func­tions: clock, data, and latch enable (LE). Serial data for the
various counters is clocked in from data on the rising edge of
clock, into the 18-bit shift register. Data is entered MSB first.
The last two bits decode the internal register address. On the
rising edge of LE, data stored in the shift register is loaded
into one of the 4 appropriate latches (selected by address
bits). Data is loaded from the latch to the counter when
counter reaches to zero. A complete programming descrip­tion is included in the following sections.

1.8 FoLD MULTIFUNCTION OUTPUT

The LMX1600/01/02 programmable output pin (FoLD) can
deliver the internal counter outputs, digital lock detects, or
CMOS high/low levels.

1.8.1 Lock Detect

A digital filtered lock detect function is included with each
phase detector through an internal digital filter to produce a
logic level output available on the Fo/LD output pin, if se­lected. The lock detect output is high when the error between

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