查询LMV115供应商
LMV115
GSM Baseband 30MHz 2.8V Oscillator Buffer
LMV115 GSM Baseband 30MHz 2.8V Oscillator Buffer
December 2003
General Description
The LMV115 is a 30MHz buffer specially designed to minimize the effects of spurious signals from the base band chip
to the oscillator. The buffer also minimizes the influence of
varying load resistance and capacitance to the oscillator and
increases the drive capability.
The input of the LMV115 is internally biased with two equal
resistors to the power supply rails. This allows AC coupling
on the input.
The LMV115 offers a shutdown function to optimize current
consumption. This shutdown function can also be used to
control the supply voltage of an external oscillator. The device is in shutdown mode when the shutdown pin is connected to V
The LMV115 comes in SC70-6 package. This space saving
product reduces components, improves clock signal and
allows ease of placement for the best form factor.
.
DD
Schematic Diagram
Features
(Typical 2.8V supply; values unless otherwise specified)
n Low supply current: 0.3mA
n 2.5V to 3.3V supply
n AC coupling possible without external bias resistors.
n Includes shutdown function external oscillator
n SC70-6 pin package 2.1 x 2mm
n Operating Temperature Range −40˚C to 85˚C
Applications
n Cellular phones
n GSM Modules
n Oscillator Modules
20075129
© 2003 National Semiconductor Corporation DS200751 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
LMV115
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance
Human Body Model 2000V (Note 2)
Machine Model 150V (Note 3)
Supply Voltage (V
Output Short Circuit to V
Output Short Circuit to V
+–V−
) 3.6V
+
−
(Note 4), (Note 5)
(Note 4), (Note 5)
Junction Temperature (Note 6) +150˚C
Mounting Temperature
Infrared or Convection (20 sec.) 235˚C
Operating Ratings (Note 1)
Supply Voltage (V
Temperature Range (Note 6), (Note 7) −40˚C to +85˚C
Package Thermal Resistance (Note 6), (Note 7)
SC70-6 414˚C/W
+–V−
) 2.5V to 3.3V
Storage Temperature Range −65˚C to +150˚C
2.8V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25˚C, V+= 2.8V, V−= 0V, VCM=V+/2, shutdown = 0.0V, and RL=
50kΩ to V
Symbol Parameter Conditions
SSBW Small Signal Bandwidth V
GFN Gain Flatness
FPBW Full Power Bandwidth (−3dB) V
Time Domain Response
t
r
t
f
t
s
OS Overshoot 0.1V
SR Slew Rate (Note 11) 18 V/µs
Distortion and Noise Performance
HD2 2
HD3 3
THD Total Harmonic Distortion V
e
n
Isolation Output to Input See also Typical Performance
Static DC Performance
A
CL
V
OS
TC V
R
OUT
PSRR Power Supply Rejection Ratio V
I
S
Miscellaneous Performance
R
IN
C
IN
+
/2, CL= 5pF to V+/2 and C
<
0.1dB f>50kHz 2.8 MHz
COUPLING
Rise Time 0.1V
= 1nF.Boldface limits apply at the temperature extremes.
Min
(Note 9)
<
0.5VPP; −3dB 31 MHz
OUT
= 1.0VPP(+4.5dBm) 9 MHz
OUT
(10-90%) 11
STEP
Typ
(Note 8)
Fall Time 11
Settling Time to 0.1% 0.1V
nd
Harmonic Distortion V
rd
Harmonic Distortion V
OUT
OUT
OUT
STEP
STEP
= 500mVPP; f = 100kHz −41 dBc
= 500mVPP; f = 100kHz −43 dBc
= 500mVPP; f = 100kHz −38 dBc
95 ns
24 %
Input-Referred Voltage Noise f = 1MHz 27 nV/
>
40 dB
Characteristics
Small Signal Voltage Gain V
Output Offset Voltage
Temperature Coefficient Output
OS
OUT
= 100mV
PP
0.90
0.85
0.998
3.5
(Note 12) 102 µV/˚C
Offset Voltage
Output Resistance f = 10kHz 61
f = 25MHz 330
+
= 2.8V to V+= 3.3V 41
38
42 dB
Supply Current No Load; Shutdown = 2.8V 0.0 2.00
No Load; Shutdown = 0V
314
Input Resistance Shutdown = 2.8V 65
Shutdown = 0V 64
Input Capacitance Shutdown = 2.8V 1.82
Shutdown = 0V 1.50
Max
(Note 9) Units
1.10
1.11
35
55
450
520
ns
V/V
mV
Ω
µA
kΩ
pF
www.national.com 2
2.8V Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ= 25˚C, V+= 2.8V, V−= 0V, VCM=V+/2, shutdown = 0.0V, and RL=
50kΩ to V
Symbol Parameter Conditions
Z
IN
V
O
I
O
I
SC
R
ON
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human Body Model (HBM) is 1.5kΩ in series with 100pF.
Note 3: Machine Model, 0Ω in series with 200pF.
Note 4: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150˚C
Note 5: Infinite Duration; Short circuit test is a momentary test. See next note.
Note 6: The maximum power dissipation is a function of T
P
D
Note 7: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of
the device such that T
T
J
Note 8: Typical Values represent the most likely parametric norm.
Note 9: All limits are guaranteed by testing or statistical analysis.
Note 10: Positive current corresponds to current flowing into the device.
Note 11: Slew rate is the average of the positive and negative slew rate.
Note 12: Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature change.
+
/2, CL= 5pF to V+/2 and C
COUPLING
= 1nF.Boldface limits apply at the temperature extremes.
(Note 9)
Input Impedance f = 25MHz; Shutdown = 2.8V 2.38
f = 25MHz; Shutdown = 0V 2.47
Output Swing Positive RL= 50kΩ to V+/2 1.90
Output Swing Negative RL= 50kΩ to V+/2
Linear Output Current No Load; V
=V+− 1.1V
OUT
(Sourcing)
No Load; V
=V−+ 1.1V
OUT
(Sinking)
Output Short-Circuit Current
No Load; Sourcing to V+/2 −90
(Note 5)
+
No Load; Sinking from V
/2 100
Switch in ON Position
, θJA, and TA. The maximum allowable power dissipation at any ambient temperature is
=(T
J(MAX)-TA
>
TA. See Applications section for information on temperature de-rating of this device.
)/θJA. All numbers apply for packages soldered directly onto a PC board.
. There is no guarantee of parametric performance as indicated in the electrical tables under conditions of internal self-heating where
J=TA
J(MAX)
Min
1.65
−90
−35
100
50
−35
50
Typ
(Note 8)
2.16
1.05
−206
205
−186
191
21
Max
(Note 9) Units
1.35
1.30
40
45
LMV115
kΩ
V
µA
µA
Ω
www.national.com3
Connection Diagram
LMV115
Ordering Information
Package Part Number Package Marking Transport Media NSC Drawing
SC70-6
SC70-6
Top View
LMV115MG
LMV115MGX 3k Units Tape and Reel
B04
20075130
250 Units Tape and Reel
MAA06A
www.national.com 4
LMV115
Typical Performance Characteristics T
connected to V
+
/2; Unless otherwise specified.
Frequency and Phase Response Frequency Response Over Temperature
20075103
Phase Response Over Temperature Gain Flatness 0.1dB
= 25˚C, V+= 2.8V, V−= 0V, VCM=V+/2, and RL,CLis
J
20075104
20075114 20075106
Full Power Bandwidth Transient Response Positive
20075105
20075119
www.national.com5
Typical Performance Characteristics T
+
connected to V
LMV115
/2; Unless otherwise specified. (Continued)
Transient Response Negative Harmonic Distortion vs. V
= 25˚C, V+= 2.8V, V−= 0V, VCM=V+/2, and RL,CLis
J
@
100kHz
OUT
Harmonic Distortion vs. V
THD vs. V
for Various Frequencies Voltage Noise
OUT
20075118
@
500kHz Harmonic Distortion vs. V
OUT
20075109
OUT
@
20075107
1MHz
20075108
20075117
www.national.com 6
20075102
LMV115
Typical Performance Characteristics T
+
connected to V
/2; Unless otherwise specified. (Continued)
R
vs. Frequency Input Impedance vs. Frequency
OUT
20075101
Isolation Output to Input V
= 25˚C, V+= 2.8V, V−= 0V, VCM=V+/2, and RL,CLis
J
20075111
OUT
vs. I
OUT
(Sinking)
20075112
V
OUT
vs. I
(Sourcing) ISCSourcing vs. V
OUT
20075121
SUPPLY
20075120
20075122
www.national.com7
Typical Performance Characteristics T
+
connected to V
LMV115
/2; Unless otherwise specified. (Continued)
I
Sinking vs. V
SC
SUPPLY
= 25˚C, V+= 2.8V, V−= 0V, VCM=V+/2, and RL,CLis
J
VOSvs. V
SUPPLY
for 3 Units
VOSvs. V
VOSvs. V
20075123
for Unit 1 VOSvs. V
SUPPLY
20075125 20075126
for Unit 3 I
SUPPLY
SUPPLY
SUPPLY
vs. V
20075124
for Unit 2
SUPPLY
20075127
www.national.com 8
20075128
LMV115
Typical Performance Characteristics T
+
connected to V
/2; Unless otherwise specified. (Continued)
PSRR vs. Frequency Small Signal Pulse Response
20075115 20075116
Large Signal Pulse Response
= 25˚C, V+= 2.8V, V−= 0V, VCM=V+/2, and RL,CLis
J
20075113
www.national.com9
Application Section
LMV115
GENERAL
The LMV115 is specially designed to minimize the effects of
spurious signals from the base band chip to the oscillator.
Beside this the influence of varying load resistance and
capacitance to the oscillator is minimized, while increasing
the drive capability. The input of the LMV115 is internally
biased with two equal resistors to the power supply rails, and
makes AC coupling possible without external bias resistors
at the input. The LMV115 has excellent gain phase margin.
The LMV115 offers a shutdown pin that can be used to
disable the device in order to optimize current consumption
and also has a feature to control the supply voltage to an
external oscillator. When the shutdown pin is connected to
the device is in shutdown mode.
V
DD
SWITCHED POWER SUPPLY CONNECTION
The LMV115 features an enable/disable function for an external oscillator by controlling its supply voltage (pin 4). See
also the schematic diagram on the front page. During normal
operating mode, pin 4 is connected to the positive supply rail
via an internal switch. The resistance between the positive
supply rail and pin 4, R
characterization table. Oscillators with a supply current up to
several milliamps can easily be powered from pin 4. During
shutdown, pin 4 is switched to the negative supply rail. The
simplified schematic for this part of the device is shown in
Figure 1
, is specified in the electrical
ON
20075132
FIGURE 2. Dual Supply Mode
PSRR
If an AC signal is applied to one of the supply lines, while the
input is floating, the signal at the input pin is half the signal at
the supply line, causing the same signal at the output of the
buffer. This will result in a PSRR of only 6dB (see Figure 2).
In a typical application the input is driven from a low ohmic
source that means the disturbance at the supply lines is
attenuated by the series resistors of 110k and the source
impedance. In case the buffer is connected to a 50Ω source,
the resulting suppression will be 20*log [(R
1+RBIAS
)/R
BIAS
= 67dB for signals at the supply line. The PSRR can also be
measured correctly for this type of input by shorten the input
to mid-supply. Due to the internal structure it is not recommended to measure with the input connected to ground. To
measure correctly the PSRR, two signals are applied to both
and VEEbut with 180˚ phase difference (see Figure 2).
V
DD
In this case, both signals are subtracted and there will be no
signal at the input. The resulting disturbance at the output is
now only caused by the signals at the supply lines.
]
20075131
FIGURE 1. Supply For External Oscillator
INPUT CONFIGURATION
The input of the LMV115 is internally biased at mid-supply by
a divider of two equal resistors. With the LMV115 in shutdown mode, the internal resistor connected to the V
is
DD
shortened to the negative power supply rail via a switch. This
makes the power consumption in ‘off’ mode almost zero, but
causes a small difference for the input impedance between
the on and off modes. Both resistors are 110kΩ so the
resulting input impedance will be approximately 55kΩ. The
input configuration allows AC coupling on the input of the
LMV115. A simplified schematic of the input is shown in
Figure 2.
www.national.com 10
INPUT AND OUTPUT LEVEL
Due to the internal loop gain of 1, the output will follow the
input. The output voltage cannot swing as close to the supply
rail as the input voltage. For linear operation the input voltage swing should not exceed the output voltage swing. The
restrictions for the output voltage can be examined by the
two curves in Figure 3. The curve V
(V) shows the
OUT
response of the output signal versus the input signal and the
curve V
–VIN(V) shows the difference between the
OUT
output and the input signal.
Application Section (Continued)
20075133
FIGURE 3. V
In Figure 3 the input signal is swept between both supply
rails (0V - 2.8V). The linear part of the plot ‘V
covers approximately the voltage range between 1.0V and
2.0V. If a difference of 50mV between output and input is
acceptable, the output range is between 1.05V and 2.15V
(see curve V
–VIN). Alternatively the output voltage
OUT
swing can be determined by using Figure 4. In the plot ‘Gain
’ it can be seen that the gain is flat for input voltages
vs. V
IN
from 1.15V till 2.1V. Outside this range the gain differs from
1. This will introduce distortion of the output signal.
OUT–VIN
OUT
vs. VIN’
LMV115
DRIVING RESISTIVE AND CAPACITIVE LOADS
The maximum output current of the LMV115 is about 200µA
which means the output can drive a maximum load of 1V/
200µA = 5kΩ. Using lower load resistances will exceed the
maximum linear output current. The LMV115 can drive a
small capacitive load, but make sure that every capacitor
directly connected to the output becomes part of the loop of
the buffer and will reduce the gain/phase margin, increasing
the instability at higher capacitive values. This will lead to
peaking in the frequency response and in extreme situations
oscillations can occur. A good practice when driving larger
capacitive loads is to include a series resistor to the load
capacitor. A to D converters present complex and varying
capacitive loads to the buffer. The best value for this isolation
resistance is often found by experimentation.
SHUTDOWN MODE
LMV115 offers a shutdown function that can be used to
disable the device and to optimize current consumption.
Switching between the normal mode and the shutdown
mode requires connecting the shutdown pin either to the
negative or the positive supply rail. If directly connected to
one of the supply rails, the part is guaranteed in the correct
mode. But if the shutdown pin is driven by other output
stages, there is a voltage range in which the installed mode
is not certainly set and it is recommended not to drive the
shutdown pin in this voltage range. As can be seen in Figure
5 this hysteresis varies from 1V to 1.6V. Below 1V the
LMV115 is securely ‘ON’ and above 1.6V securely ‘OFF’
while using a supply voltage of 2.8V.
20075134
FIGURE 4. Gain
Another point is the DC bias voltage necessary to get the
optimum output voltage swing. As discussed above, the
output voltage swing can be 1V
, but if the two internal bias
PP
resistors are used, the DC bias will be 1.4V, which is half of
the supply voltage of 2.8V. In this situation the output swing
will exceed the lower limit of 1.15V, so it is necessary to
introduce a small DC offset of 200mV to make use of the full
output swing range of the output stage.
20075135
FIGURE 5. Hysteresis
PRINTED CIRCUIT BOARD LAYOUT AND COMPONENT
VALUES SELECTION
For a good high frequency design both the active parts and
the passive ones should be suitable for the purpose they are
used for. Amplifying high frequencies is possible with standard through-hole components, but for frequencies above
several hundreds of MHz the best choice is using surface
mount devices. Nowadays designs are often assembled with
surface mount devices for the aspect of minimizing space,
but this also greatly improves the performance of designs,
handling high frequencies. Another important issue is the
PCB, which is no longer a simple carrier for all the parts and
a medium to interconnect them. The board becomes a real
www.national.com11
Application Section (Continued)
part itself, adding its own high frequency properties to the
LMV115
overall performance of the circuit. It is good practice to have
at least one ground plane on a PCB giving a low impedance
path for all decoupling and other ground connections. In
order to achieve high immunity for unwanted signals from
outside, it is important to place the components as flat as
possible on the PCB. Be aware that a long lead can act as
an inductor, a capacitor or an antenna. A pair of leads can
even form a transformer. Careful design of the PCB avoids
oscillations or other unwanted behavior. Another important
issue is the value of components, which also determines the
sensitivity to pick-up unwanted signals. Choose the value of
resistors as low as possible, but avoid using values that
causes a significant increase in power consumption, while
loading inputs or outputs to heavily.
NSC suggests the following evaluation board as a guide for
high frequency layout and as an aid in device testing and
characterization.
Device Package Evaluation Board
PN
LMV115 SC70-6 LMV115/117 Eval
Board
This free evaluation board is shipped when a device sample
request is placed with National Semiconductor.
www.national.com 12
Physical Dimensions inches (millimeters) unless otherwise noted
LMV115 GSM Baseband 30MHz 2.8V Oscillator Buffer
NS Package Number MAA06A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National Semiconductor
Americas Customer
Support Center
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
National Semiconductor
Asia Pacific Customer
Support Center
Email: ap.support@nsc.com
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
Loading...