National Semiconductor LMK02000 Technical data

LMK02000 Precision Clock Conditioner with Integrated PLL

September 2007

General Description

The LMK02000 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), three LVDS, and five LVPECL clock output distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.

Functional Block Diagram

Features

20 fs additive jitter

■

Integrated Integer-N PLL with outstanding normalized

■

phase noise contribution of -224 dBc/Hz Clock output frequency range of 1 to 800 MHz

■

3 LVDS and 5 LVPECL clock outputs

■

Dedicated divider and delay blocks on each clock output

■

Pin compatible family of clocking devices

■

3.15 to 3.45 V operation

■

Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

■

Target Applications

Data Converter Clocking

■

Networking, SONET/SDH, DSLAM

■

Wireless Infrastructure

■

Medical

■

Test and Measurement

■

Military / Aerospace

■

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

20216501

Connection Diagram

LMK02000

48-Pin LLP Package

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20216502

Pin Descriptions

Pin # Pin Name I/O Description

1, 25 GND - Ground

2, 7 NC - No Connection to these pins

3, 8, 13, 16, 19, 22, 26,

30, 31, 33, 37, 40, 43, 46

4 CLKuWire I MICROWIRE Clock Input

5 DATAuWire I MICROWIRE Data Input

6 LEuWire I MICROWIRE Latch Enable Input

9, 10 LDObyp1, LDObyp2 - LDO Bypass

11 GOE I Global Output Enable

12 LD O Lock Detect and Test Output

14, 15 CLKout0, CLKout0* O LVDS Clock Output 0

17, 18 CLKout1, CLKout1* O LVDS Clock Output 1

20, 21 CLKout2, CLKout2* O LVDS Clock Output 2

23, 24 CLKout3, CLKout3* O LVPECL Clock Output 3

27 SYNC* I Global Clock Output Synchronization

28, 29 OSCin, OSCin* I Oscillator Clock Input; Must be AC coupled

32 CPout O Charge Pump Output

34, 35 Fin, Fin* I Frequency Input; Must be AC coupled

36 Bias I Bias Bypass

38, 39 CLKout4, CLKout4* O LVPECL Clock Output 4

41, 42 CLKout5, CLKout5* O LVPECL Clock Output 5

44, 45 CLKout6, CLKout6* O LVPECL Clock Output 6

47, 48 CLKout7, CLKout7* O LVPECL Clock Output 7

DAP DAP - Die Attach Pad is Ground

Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7,

Vcc8, Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14

LMK02000

- Power Supply

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

LMK02000

Parameter Symbol Ratings Units

Power Supply Voltage

Input Voltage

Storage Temperature Range

Lead Temperature (solder 4 s)

Junction Temperature

STG

-0.3 to 3.6 V

-0.3 to (VCC + 0.3)

-65 to 150 °C

+260 °C

125 °C

Recommended Operating Conditions

Parameter Symbol Min Typ Max Units

Ambient Temperature

Power Supply Voltage

Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.

-40 25 85 °C

3.15 3.3 3.45 V

Package Thermal Resistance

Package

J-PAD (Thermal Pad)

48-Lead LLP (Note 3) 27.4° C/W 5.8° C/W

Note 3: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.

Electrical Characteristics (Note 4)

(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed).

Symbol Parameter Conditions Min Typ Max Units

Current Consumption

ICCPD

OSCin

Fin

SLEW

DUTY

Fin

square

Fin

Entire device; CLKout0 & CLKout4 Power Supply Current (Note 5)

enabled in Bypass Mode

Entire device; All Outputs Off (no

emitter resistors placed)

Power Down Current POWERDOWN = 1 1 mA

Reference Oscillator

Reference Oscillator Input Frequency Range for Square Wave

Square Wave Input Voltage for OSCin and

AC coupled; Differential (VOD)

OSCin*

Frequency Input

Frequency Input Frequency Range 1 800 MHz

Frequency Input Slew Rate (Notes 6, 10) 0.5 V/ns

Frequency Input Duty Cycle 40 60 %

Input Power Range for Fin or Fin* AC coupled -13 8 dBm

145.8

1 200 MHz

0.2 1.6 Vpp

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Symbol Parameter Conditions Min Typ Max Units

PLL

COMP

CPout

SRCE

CPout

SINK

TRI Charge Pump TRI-STATE® Current 0.5 V < V

CPout

%MIS

CPout

VTUNE

CPout

TEMP

CPout

PN10kHz

PN1Hz

Phase Detector Frequency 40 MHz

Charge Pump Source Current

Charge Pump Sink Current

Magnitude of Charge Pump Sink vs. Source Current Mismatch

Magnitude of Charge Pump Current vs. Charge Pump Voltage Variation

Magnitude of Charge Pump Current vs. Temperature Variation

PLL 1/f Noise at 10 kHz Offset (Note 7) Normalized to 1 GHz Output Frequency

Normalized Phase Noise Contribution (Note 8)

= Vcc/2, PLL_CP_GAIN = 1x

CPout

= Vcc/2, PLL_CP_GAIN = 4x

CPout

= Vcc/2, PLL_CP_GAIN = 16x

CPout

= Vcc/2, PLL_CP_GAIN = 32x

CPout

= Vcc/2, PLL_CP_GAIN = 1x

CPout

= Vcc/2, PLL_CP_GAIN = 4x

CPout

= Vcc/2, PLL_CP_GAIN = 16x

CPout

= Vcc/2, PLL_CP_GAIN = 32x

CPout

< Vcc - 0.5 V

CPout

= Vcc / 2

CPout

TA = 25°C

0.5 V < V

< Vcc - 0.5 V

CPout

TA = 25°C

4 %

PLL_CP_GAIN = 1x -117

PLL_CP_GAIN = 32x -122

PLL_CP_GAIN = 1x -219

PLL_CP_GAIN = 32x -224

100

400

1600

3200

-100

-400

-1600

-3200

2 10 nA

3 %

4 %

Clock Distribution Section (Note 9) - LVDS Clock Outputs (CLKout0 to CLKout2)

Jitter

ADD

Additive RMS Jitter (Note 9)

RL = 100 Ω Distribution Path = 800 MHz Bandwidth = 12 kHz to 20 MHz

CLKoutX_MUX = Bypass

CLKoutX_MUX = Divided CLKoutX_DIV = 4

Equal loading and identical clock

SKEW

CLKoutX to CLKoutY (Note 10)

configuration

-30 ±4 30 ps

RL = 100 Ω

ΔV

SAB

Differential Output Voltage

Change in magnitude of VOD for complementary output states

Output Offset Voltage

Change in magnitude of VOS for complementary output states

Clock Output Short Circuit Current single ended

Clock Output Short Circuit Current differential

RL = 100 Ω

250 350 450 mV

-50 50 mV

1.070 1.25 1.370 V

-35 35 mV

Single ended outputs shorted to GND -24 24 mA

Complementary outputs tied together -12 12 mA

LMK02000

µA

μA

dBc/Hz

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Symbol Parameter Conditions Min Typ Max Units

Clock Distribution Section (Note 9) - LVPECL Clock Outputs (CLKout3 to CLKout7)

LMK02000

Jitter

ADD

Additive RMS Jitter (Note 9)

RL = 100 Ω

Distribution Path =

800 MHz

Bandwidth =

12 kHz to 20 MHz

CLKoutX_MUX = Bypass

CLKoutX_MUX = Divided CLKoutX_DIV = 4

Equal loading and identical clock

SKEW

CLKoutX to CLKoutY (Note 10)

configuration

-30 ±3 30 ps

Termination = 50 Ω to Vcc - 2 V

Output High Voltage

Output Low Voltage

Termination = 50 Ω to Vcc - 2 V

Differential Output Voltage 660 810 965 mV

Vcc -

0.98

Vcc -

1.8

Digital LVTTL Interfaces (Note 11)

High-Level Input Voltage 2.0 Vcc V

Low-Level Input Voltage 0.8 V

High-Level Input Current

Low-Level Input Current

High-Level Output Voltage

Low-Level Output Voltage

VIH = Vcc

VIL = 0

IOH = +500 µA

IOL = -500 µA

-5.0 5.0 µA

-40.0 5.0 µA

Vcc -

0.4

0.4 V

Digital MICROWIRE Interfaces (Note 12)

High-Level Input Voltage 1.6 Vcc V

Low-Level Input Voltage 0.4 V

High-Level Input Current

Low-Level Input Current

VIH = Vcc

VIL = 0

-5.0 5.0 µA

MICROWIRE Timing

CWH

CWL

CES

EWH

Note 4: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 5: See 3.4 for more current consumption / power dissipation calculation information.

Note 6: For all frequencies the slew rate, SLEW

Note 7: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L

dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L (f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L slope close to the carrier. A high phase detector frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L (f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of L

PLL_flicker

Note 8: A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, L L

PLL_flat

detector frequency of the synthesizer. L smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. L masked by the reference oscillator performance if a low power or noisy source is used.

Note 9: The Clock Distribution Section includes all parts of the device except the PLL section. Typical Additive Jitter specifications apply to the clock distribution section only.

Note 10: Specification is guaranteed by characterization and is not tested in production.

Note 11: Applies to GOE, LD, and SYNC*.

Data to Clock Set Up Time See Data Input Timing 25 ns

Data to Clock Hold Time See Data Input Timing 8 ns

Clock Pulse Width High See Data Input Timing 25 ns

Clock Pulse Width Low See Data Input Timing 25 ns

Clock to Enable Set Up Time See Data Input Timing 25 ns

Enable to Clock Set Up Time See Data Input Timing 25 ns

Enable Pulse Width High See Data Input Timing 25 ns

, is measured between 20% and 80%.

(f) and L

(f) – 20log(N) – 10log(f

PLL_flat

(f).

COMP

Fin

). L

(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and f

PLL_flat

(f) contributes to the total noise, L(f). To measure L

PLL_flat

(f), which is dominant close to the carrier. Flicker noise has a 10

PLL_flicker

PLL_flat

(10 kHz) - 20log(Fout / 1 GHz), where L

PLL_flicker

(f) the offset frequency, f, must be chosen sufficiently

(f) it is important to be on the 10 dB/decade

PLL_flicker

(f), of the PLL and is defined as PN1Hz =

PLL_flat

COMP

PLL_flicker

is the phase

(f) can be

PLL_flat

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