National Semiconductor LMH6514 Technical data

January 24, 2008

LMH6514 600 MHz, Digital Controlled, Variable Gain Amplifier

General Description

The LMH6514 is a high performance, digitally controlled variable gain amplifier (DVGA). It combines precision gain control with a low noise, ultra-linear, differential amplifier. Typically, the LMH6514 drives a high performance ADC in a broad range of mixed signal and digital communication applications such as mobile radio and cellular base stations where automatic gain control (AGC) is required to increase system dynamic range. When used in conjunction with a high speed ADC, system dynamic range can be extended by up to 42 dB.

The LMH6514 has a differential input and output allowing large signal swings on a single 5V supply. It is designed to accept signals from RF elements and maintain a terminated impedance environment. The input impedance is 200Ω resistive. The output impedance is either 200Ω or 400Ω and is user selectable. A unique internal architecture allows use with both single ended and differential input signals.

Input signals to the LMH6514 are scaled by a highly linear, digitally controlled attenuator with seven accurate 6 dB steps. The attenuator output provides the input signal for a high gain, ultra linear differential transconductor. The transconductor differential output current can be converted into a voltage by using the on-chip 200Ω or 400Ω loads. The transconductance gain is 0.1 Amp/Volt resulting in a maximum voltage gain of +32 dB when driving a 200Ω load, or 38 dB when driving the 400Ω load. On chip digital latches are provided for local storage of the gain setting. The gain step settling time is 5 ns and care has been taken to reduce the sensitivity of bandwidth and phase to gain setting.

The LMH6514 operates over the industrial temperature range of −40°C to +85°C. The LMH6514 is available in a 16-Pin, thermally enhanced, LLP package.

Features

Adjustable gain with a 42 dB range

■

Precise 6.02 dB gain steps

■

Parallel 3 bit gain control

■

On chip register gain setting

■

Fully differential signal path

■

Single ended to differential capable

■

200Ω input impedance

■

Small footprint (4 mm x 4 mm) LLP package

■

Key Specifications

600 MHz bandwidth at 100Ω load

■

39 dBm OIP3 at 75 MHz, 200Ω load

■

26 dB to 38 dB maximum gain

■

Selectable output impedance of 200Ω or 400Ω.

■

8.3 dB noise figure

■

5 ns gain step switching time

■

100 mA supply current

■

Applications

Cellular base stations

■

IF sampling receivers

■

Instrumentation

■

Modems

■

Imaging

■

Differential line receiver

■

Typical Application

30042901

LMH™ is a trademark of National Semiconductor Corporation.

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/

LMH6514

Distributors for availability and specifications.

Storage Temperature Range −65°C to +150°C Soldering Information

Infrared or Convection (20 sec) 235°C Wave Soldering (10 sec) 260°C

ESD Tolerance (Note 2) Human Body Model 2 kV Machine Model 150V Positive Supply Voltage (Pin 3) −0.6V to 5.5V Output Voltage (Pin 14,15) −0.6V to 6.8V Differential Voltage between Any

Two Grounds <200 mV Analog Input Voltage Range −0.6V to V

Digital Input Voltage Range −0.6V to 3.6V Output Short Circuit Duration

(one pin to ground) Infinite

Operating Ratings (Note 1)

Supply Voltage (Pin 3) 4V to 5.25V Output Voltage Range (Pin 14, 15) 1.4V to 6.4V Differential Voltage Between Any

Two Grounds <10 mV Analog Input Voltage Range,

AC Coupled ±1.4V Temperature Range (Note 3) −40°C to +85°C

Package Thermal Resistance (θJA)

16-Pin LLP 47°C/W

Junction Temperature +150°C

5V Electrical Characteristics (Note 4)

The following specifications apply for single supply with VCC = 5V, Maximum Gain , RL = 100Ω (200Ω external || 200Ω internal), V

= 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes.

OUT

Symbol Parameter Conditions Min

(Note 6)

Dynamic Performance

SSBW −3 dB Bandwidth Average of all Gain Settings 600 MHz

Noise and Distortion

Third Order Intermodulation

Products

OIP3 Output Third Order Intercept Point f = 75 MHz, V

f = 75 MHz, V

f = 150 MHz, V

f = 250 MHz, V

f = 450 MHz, V

OUT

= 2 V

= 2 VPP,

−70

−66

−60

−52

Tone Spacing = 0.5 MHz

f = 150 MHz, V

OUT

= 2 VPP,

Tone Spacing = 2 MHz

f = 250 MHz, V

OUT

= 2 VPP,

Tone Spacing = 2 MHz

f = 75 MHz, RL= 200Ω, V

OUT

= 2 V

Tone Spacing = 0.5 MHz

f = 150 MHz, RL = 200Ω, V

OUT

= 2 VPP,

Tone Spacing = 2 MHz

f = 250 MHz, RL = 200Ω, V

OUT

= 2 VPP,

Tone Spacing = 2 MHz

P1 dB Output Level for 1 dB Gain

Compression

f = 75 MHz, R L = 200Ω

f = 250 MHz, R L = 200Ω

16.7

14.7

f = 75 MHz 14.5

f = 450 MHz 13.2

VNI Input Noise Voltage Maximum Gain, f = 40 MHz 1.8

VNO Output Noise Voltage Maximum Gain, f = 40 MHz 36

NF Noise Figure Maximum Gain 8.3 dB

Analog I/O

Differential Input Resistance 165

158

Input Common Mode Resistance 825

785

Typ

(Note 5)

(Note 6)

188 220

955 1120

Max

230

1160

Units

dBc

dBm

nV/

Ω

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LMH6514

Symbol Parameter Conditions Min

(Note 6)

Typ

(Note 5)

Max

(Note 6)

Units

Differential Output Resistance Low Gain Option 186

High Gain Option 330

325

Internal Load Resistors Between Pins 13, 14 and Pins 15, 16 165

158

Input Signal Level (AC Coupled)

Max Gain, VO = 2 VPP, RL = 1 kΩ

370 420

425

187 215

225

63 mV

Ω

Maximum Differential Input Signal AC Coupled 5.6 V

Input Common Mode Voltage Self Biased 1.3

1.1

Input Common Mode Voltage

Driven Externally 0.9 to 2.0 V

1.4 1.5

1.7

Range

Minimum Input Voltage DC 0 V

Maximum Input Voltage DC 3.3 V

Maximum Differential Output

VCC = 5V, Output Common Mode = 5V 5.5 V

Voltage Swing

Output Offset Voltage All Gain Settings −21 mV

CMRR Common Mode Rejection Ratio Maximum Gain 81 dB

PSRR Power Supply Rejection Ratio Maximum Gain 63

Gain Parameters

Maximum Gain

Minimum Gain

DC, Internal RL = 186Ω,

External RL = 1280Ω

DC, Internal RL = 186Ω,

External RL = 1280Ω

29.3

28.7

−12.75

−13.15

30 30.3

30.9

−12 −11.85

−11.45

Gain Step Size DC 6.02 dB

Gain Step Error DC 0.02

f = 150 MHz 0.07

Cumulative Gain Step Error DC, Gain Step 7 to Gain Step 0 −0.35

−0.50

0.02 0.30

0.45

Gain Step Switching Time 5 ns

Digital Inputs/Timing

Logic Compatibility CMOS Logic 3.3 V

VIL Logic Input Low Voltage 0.8 V

VIH Logic Input High Voltage 2.0 V

IIH Logic Input High Input Current Digital Input Voltage = 3.3V 33 40

μA

TSU Setup Time 3 ns

THOLD Hold Time 3 ns

TPW Minimum Latch Pulse Width 10 ns

Power Requirements

ICC Total Supply Current V

Amplifier Supply Current Pin 3 Only 56 66

Output Stage Bias Currents Pins 13, 14 and Pins 15, 16;

= 0V Differential, V

OUT

Mode = 5V

Common Mode = 5 V

OUT

Common

OUT

107 124

134

51 58

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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.

Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)

Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

LMH6514

Note 3: The maximum power dissipation is a function of T

PD = (T

Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the electrical tables under conditions different than those tested

Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.

Note 6: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods.

Note 7: Negative input current implies current flowing out of the device.

Note 8: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.

– TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.

J(MAX)

, θJA. The maximum allowable power dissipation at any ambient temperature is

J(MAX)

Connection Diagram

16-Pin LLP

Top View

30042904

Gain Control Pins

Pin Number Pin Name Gain Step Size

11 GAIN_0 6.02 dB

10 GAIN_1 12.04 dB

9 GAIN_2 24.08 dB

Ordering Information

Package Part Number Package Marking Transport Media NSC Drawing

16-Pin LLP

LMH6514SQ

LMH6514SQX 4.5k Units Tape and Reel

L6514SQ

1k Units Tape and Reel

SQA16A

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Pin Descriptions

Pin Number Symbol Description

Analog I/O

6 IN+ Non-inverting analog input. Internally biased to 1.4V. Input voltage should not exceed

VCC or go below GND by more than 0.5V.

7 IN− Inverting analog input. Internally biased to 1.4V. Input voltage should not exceed VCC or

go below GND by more than 0.5V. If using amplifier single ended this input should be capacitively coupled to ground.

15 OUT− Open collector inverting output. This pin is an output that also requires a power source.

This pin should be connected to 5V through either an RF choke or an appropriately sized inductor that can form part of a filter. See application section for details.

14 OUT+ Open collector non-inverting output. This pin is an output that also requires a power

source. This pin should be connected to 5V through either an RF choke or an appropriately sized inductor that can form part of a filter. See application section for details.

16 LOAD−

13 LOAD+

Power

3 V

5,8 GND Ground pins. Connect to low impedance ground plane. All pin voltages are specified with

Digital Inputs

11,10,9 GAIN_0 to

2 LATCH This pin controls the function of the gain setting pins mentioned above. With LATCH in

1,4,12 NC These pins are not connected. They can be grounded or left floating.

GAIN_2

Internal 200Ω resistor connection to pin 15. This pin can be left floating for higher gain or shorted to pin 13 for lower gain and lower effective output impedance. See application section for details.

Internal 200Ω resistor connection to pin 14. This pin can be left floating for higher gain or shorted to pin 16 for lower gain and lower effective output impedance. See application section for details.

5V power supply pin. Use ceramic, low ESR bypass capacitors. This pin powers everything except the output stage.

respect to the voltage on these pins. The exposed thermal pad is also a ground connection.

Gain setting pins. See above table for gain step sizes for each pin. These pins are 3.3V CMOS logic compatible. 5V inputs may cause damage.

the logic HIGH state the gain is fixed and will not change. With the LATCH in the logic LOW state the gain is set by the state of the gain control pins. Any changes in gain made with the LATCH pin in the LOW state will take effect immediately. This pin is 3.3V CMOS logic compatible. 5V inputs may cause damage.

LMH6514

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Typical Performance Characteristics V

= 5V

LMH6514

Frequency Response All Gain Settings

Frequency Response over Temperature, Minimum Gain

30042922

Frequency Response over Temperature, Maximum Gain

30042949

OIP3 High Gain Mode

30042950

OIP3 Low Gain Mode

30042942

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30042943

OIP3 Over Temperature

30042926

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