National Semiconductor LMH6502 Technical data

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LMH6502
Wideband, Low Power, Linear-in-dB Variable Gain
Amplifier

LMH6502 Wideband, Low Power, Linear-in-dB Variable Gain Amplifier

June 2004

General Description

The LMH™6502 is a wideband DC coupled differential input
voltage controlled gain stage followed by a high-speed cur­rent feedback Op Amp which can directly drive a low imped­ance load. Gain adjustment range is more than 70dB for up
to 10MHz.

Maximum gain is set by external components and the gain
can be reduced all the way to cut-off. Power consumption is
300mW with a speed of 130MHz. Output referred DC offset
voltage is less than 350mV over the entire gain control
voltage range. Device-to-device Gain matching is within

±

0.6dB at maximum gain. Furthermore, gain at any VGis
tested and the tolerance is guaranteed. The output current
feedback Op Amp allows high frequency large signals (Slew
Rate = 1800V/µs) and can also drive heavy load current
(75mA). Differential inputs allow common mode rejection in
low level amplification or in applications where signals are
carried over relatively long wires. For single ended opera­tion, the unused input can easily be tied to ground (or to a
virtual half-supply in single supply application). Inverting or
non-inverting gains could be obtained by choosing one input
polarity or the other.

To provide ease of use when working with a single supply,

range is set to be from 0V to +2V relative to pin 11

V

G

potential (ground pin). In single supply operation, this ground
pin is tied to a "virtual" half supply.

LMH6502 gain control is linear in dB for a large portion of the
total gain control range. This makes the device suitable for
AGC circuits among other applications. For linear gain con­trol applications, see the LMH6503 datasheet. The
LMH6502 is available in the SOIC-14 and TSSOP-14 pack­age.

Features

VS=±5V, TA= 25˚C, RF=1kΩ,RG= 174Ω,RL= 100Ω,A
=A

n -3dB BW 130MHz
n Gain control BW 100MHz
n Adjustment range (typical over temp) 70dB
n Gain matching (limit)
n Slew rate 1800V/µs
n Supply current (no load) 27mA
n Linear output current
n Output voltage (R
n Input voltage noise 7.7nV/
n Input current noise 2.4pA/
n THD (20MHz, RL= 100Ω,VO=2VPP) −53dBc
n Replacement for CLC520

= 10 Typical values unless specified.

V(MAX)

= 100Ω)

L

±

0.6dB

±

75mA

±

3.2V

Applications

n Variable attenuator
n AGC
n Voltage controller filter
n Video imaging processing

V

Gain vs. VGfor Various Temperature

20067706

LMH™is a trademark of National Semiconductor Corporation.

© 2004 National Semiconductor Corporation DS200677 www.national.com

Typical Application

A

= 10V/V

VMAX

20067737

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/

LMH6502

Distributors for availability and specifications.

Junction Temperature +150˚C

Soldering Information:

Infrared or Convection (20 sec) 235˚C

Wave Soldering (10 sec) 260˚C

ESD Tolerance (Note 4):

Human Body 2KV

Machine Model 200V

±

Input Current

V

Differential

IN

10mA

±

(V+-V−)

Output Current 120mA (Note 3)

Supply Voltages (V

Voltage at Input/ Output pins V

+-V−

) 12.6V

+

+0.8V,V−- 0.8V

Operating Ratings (Note 1)

Supply Voltages (V

Temperature Range −40˚C to +85˚C

Thermal Resistance: (θ

14-Pin SOIC 45˚C/W 138˚C/W

14-Pin TSSOP 51˚C/W 160˚C/W

+-V−

) 5Vto12V

)(θJA)

JC

Storage Temperature Range −65˚C to +150˚C

Electrical Characteristics(Note 2)

Unless otherwise specified, all limits guaranteed for TJ= 25˚C, VS=±5V, A
V

=±0.1V, RL= 100Ω,VG= +2V. Boldface limits apply at the temperature extremes.

IN_DIFF

Symbol Parameter Conditions

Frequency Domain Response

BW -3dB Bandwidth V

GF Gain Flatness V

<

0.5

OUT

V

OUT

OUT

<

0.5PP,A

<

0.5V

PP

= 100 50

V(MAX)

PP

0.6V ≤ VG≤ 2V,±0.3dB

Att Range Flat Band (Relative to Max Gain)

Attenuation Range (Note 14)

BW

Gain control Bandwidth V

±

0.2dB, f<30MHz 16

±

0.1dB, f<30MHz 7.5

= 1V (Note 13) 100 MHz

G

Control

PL Linear Phase Deviation DC to 60MHz 1.5 deg

G Delay Group Delay DC to 130MHz 2.5 ns

CT (dB) Feed-through V

= 0V, 30MHz (Output

G

Referred)

GR Gain Adjustment Range f<10MHz 72

<

f

30MHz 67

Time Domain Response

t

r,tf

Rise and Fall Time 0.5V Step 2.2 ns

OS % Overshoot 0.5V Step 10 %

SR Slew Rate 4V Step 1800 V/µs

∆ G Rate Gain Change Rate V

= 0.3V, 10%-90% of Final

IN

Output

Distortion & Noise Performance

HD2 2

HD3 3

THD Total Harmonic Distortion 2V

nd

Harmonic Distortion 2VPP, 20MHz −55 dBc

rd

Harmonic Distortion 2VPP, 20MHz −57 dBc

, 20MHz −53 dBc

PP

En tot Total Equivalent Input Noise 1MHz to 150MHz 7.7 nV/

I

N

Input Noise Current 1MHz to 150MHz 2.4 pA/

DG Differential Gain f = 4.43MHz, RL= 150Ω,

Neg. Sync

DP Differential Phase f = 4.43MHz, R

= 150Ω,

L

Neg. Sync

= 10, VCM= 0V, RF=1kΩ,RG= 174Ω,

V(MAX)

Min

(Note 6)

Typ

(Note 6)

(Note 6) Units

130

30 MHz

−47 dB

4.8 dB/ns

0.34 %

0.10 deg

Max

MHz

dB

dB

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Electrical Characteristics(Note 2) (Continued)

Unless otherwise specified, all limits guaranteed for TJ= 25˚C, VS=±5V, A
V

Symbol Parameter Conditions

DC & Miscellaneous Performance

GACCU Gain Accuracy (See Application

G Match Gain Matching (See Application

K Gain Multiplier

V

CM

V

IN_DIFF

I

RG_MAX

I

BIAS

TC I

I

OFF

TC I

R

IN

C

IN

I

VG

TC I

R

VG

C

VG

V

OUT

R

OUT

I

OUT

V

O

OFFSET

+PSRR +Power Supply Rejection Ratio

−PSRR −Power Supply Rejection Ratio

CMRR Common Mode Rejection Ratio

I

S

=±0.1V, RL= 100Ω,VG= +2V. Boldface limits apply at the temperature extremes.

IN_DIFF

V

= 2.0V 0.0 +0.6

G

Note)

Note)

<

1V

V

1

G

<

V

2V +0.6/−0.3 +3.1/−3.6

G

= 2.0V –

<

<

V

2V – +2.8/−3.9

G

(See Application Notes)

Input Voltage Range Pin3&6Common Mode,

>

|CMRR|

55dB (Note 9)

Differential Input Voltage Between pins3&6

RGCurrent Pins4&5

Bias Current Pins 3 & 6(Note 7) 9 18

Pins3&6(Note 7),

=±2.5V

V

S

Bias Current Drift Pin 3 & 6(Note 8) 100 nA/˚C

BIAS

Offset Current Pin3&6 0.01 2.0

Offset Current Drift (Note 8) 5 nA/˚C

OFF

Input Resistance Pin3&6 750 kΩ

Input Capacitance Pin3&6 5 pF

VGBias Current Pin 2, VG= 0V(Note 7) −300 µA

VGBias Drift Pin 2(Note 8) 20 nA/˚C

VG

VGInput Resistance Pin 2 10 kΩ

VGInput Capacitance Pin 2 1.3 pF

Output Voltage Range RL= 100Ω

= Open

R

L

Output Impedance DC 0.1 Ω

Output Current V

Output Offset Voltage 0V<V

=±4V from Rails

OUT

<

2V

G

Input Referred, 1V change,

(Note 10)

V

= 2.2V

G

Input Referred, 1V change,

(Note 10)

(Note 9)

= 2.2V

V

G

Input Referred,V

<

<

−1.8V

V

CM

=2V

G

1.8V

Supply Current No Load 27 38

=±2.5V, RL= Open 9.3 16

V

S

= 10, VCM= 0V, RF=1kΩ,RG= 174Ω,

V(MAX)

Min

(Note 6)

1.61

Typ

(Note 6)

(Note 6) Units

1.72 1.84

1.58

±

±

±

±

±

1.70

±

0.12

1.70

1.56

2.0

0.3

±

2.2 V

±

0.39

±

2.22 mA

2.5 5

±

±

±

±

3.00

2.95

3.95

3.82

±

80

±

75

±

3.20

±

4.00

±

90 mA

±

80

−69 −47

−58 −41

−72 dB

Max

±

0.6

1.91

20

6

3.6

±

300

±

380

−45

−40

41

19

LMH6502

dB

dB

V/V

V

µA

µA

V

mV

dB

dB

mA

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Electrical Characteristics(Note 2) (Continued)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.

LMH6502

Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of

the device such that T

Note 3: The maximum output current (I

Note 4: Human body model: 1.5kΩ in series with 100pF. Machine model: 0Ω in series with 200pF.

Note 5: Slew Rate is the average of the rising and falling rates.

Note 6: Typical values represent the most likely parametric norm. Bold numbers refer to over temperature limits.

Note 7: Positive current corresponds to current flowing in the device.

Note 8: Drift determined by dividing the change in parameter distribution average at temperature extremes by the total temperature change.

Note 9: CMRR definition: [|∆V

Note 10: +PSRR definition: [|∆V

Note 11: Gain/Phase normalized to low frequency value at 25˚C.

Note 12: Gain/Phase normalized to low frequency value at each A

Note 13: Gain Control Frequency Response Schematic:

. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where T

J=TA

OUT

OUT

) is determined by device power dissipation limitations or value specified, whichever is lower.

OUT

/∆VCM|/AV] with 0.1V differential input voltage.

/∆V+|/AV], −PSRR definition: [|∆V

/∆V−|/AV] with 0.1V differential input voltage.

OUT

.

V

>

TA.

J

20067738

Note 14: Flat Band Attenuation (Relative to Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain flatness specified

±

(either

0.2dB or±0.1dB) relative to A

±

0.2dB 20dB down to 4dB = 16dB range

±

0.1dB 20dB down to 12.5 dB = 7.5dB range

gain. For example, for f<30MHz, here are the Flat Band Attenuation ranges:

VMAX

Connection Diagram

14-Pin SOIC/TSSOP

Top View

20067736

Ordering Information

Package Part Number Package Marking Transport Media NSC Drawing

14-pin SOIC LMH6502MA LMH6502MA 55 Units/Rail M14A

LMH6502MAX 2.5k Units Tape and Reel

14-Pin TSSOP

LMH6502MT

LMH6502MTX 2.5k Units Tape and Reel

LMH6502MT

94 Units/Rail

MTC14

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LMH6502

Typical Performance Characteristics Unless otherwise specified: V

= 0V, RF=1kΩ,RG= 174Ω, both inputs terminated in 50Ω,RL= 100Ω, Typical values, results referred to device output.

V

CM

Small Signal Frequency for Various V

G

20067731

Frequency Response Over Temperature (AV= 10) Frequency Response for Various VG(A

Large Signal Frequency for Various V

=±5V, 25˚C, VG=V

S

VMAX

GMAX

G

20067732

= 10)

,

Frequency Response for Various VG(A

±

2.5V) Small Signal Frequency Response for Various A

(

20067707 20067708

= 10)

VMAX

20067714

VMAX

20067723

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Typical Performance Characteristics Unless otherwise specified: V

=±5V, 25˚C, VG=V

S

= 0V, RF=1kΩ,RG= 174Ω, both inputs terminated in 50Ω,RL= 100Ω, Typical values, results referred to device
output. (Continued)

LMH6502

GMAX,VCM

Large Signal Frequency Response for Various A

20067724

Frequency Response for Various VG(A

VMAX

= 100)

(Large Signal) I

VMAX

Frequency Response for Various VG(A

(Small Signal)

vs. V

S

S

VMAX

= 100)

20067729

20067730

ISvs. V

S

20067751

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Input Bias Current vs. V

20067750

S

20067752

LMH6502

Typical Performance Characteristics Unless otherwise specified: V

=±5V, 25˚C, VG=V

S

= 0V, RF=1kΩ,RG= 174Ω, both inputs terminated in 50Ω,RL= 100Ω, Typical values, results referred to device
output. (Continued)

A

VMAX

vs. V

CM

20067767

A

VMAX

vs. V

CM

PSRR±5V PSRR±2.5V

GMAX,VCM

20067766

20067703

CMRR±5V CMRR±2.5V

20067701 20067702

20067704

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Typical Performance Characteristics Unless otherwise specified: V

=±5V, 25˚C, VG=V

S

= 0V, RF=1kΩ,RG= 174Ω, both inputs terminated in 50Ω,RL= 100Ω, Typical values, results referred to device
output. (Continued)

LMH6502

A

vs. Supply Voltage Supply Current vs. V

VMAX

GMAX,VCM

CM

Supply Current vs. V

CM

20067768

Output Offset Voltage vs. VCM(Typical Unit#1)

20067757

20067756

20067758

Output Offset Voltage vs. VCM(Typical Unit#2) Output Offset Voltage vs. VCM(Typical Unit#3)

20067759 20067760

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LMH6502

Typical Performance Characteristics Unless otherwise specified: V

=±5V, 25˚C, VG=V

S

= 0V, RF=1kΩ,RG= 174Ω, both inputs terminated in 50Ω,RL= 100Ω, Typical values, results referred to device
output. (Continued)

Feed through Isolation Gain Flatness and Linear Phase Deviation vs. V

20067721

Gain Flatness Frequency vs. Gain (Note 14) Group Delay vs. Frequency

GMAX,VCM

G

20067709

K Factor vs. R

20067711

G

20067739

Gain vs. VGIncluding Limits

20067712

20067705

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Typical Performance Characteristics Unless otherwise specified: V

=±5V, 25˚C, VG=V

S

= 0V, RF=1kΩ,RG= 174Ω, both inputs terminated in 50Ω,RL= 100Ω, Typical values, results referred to device
output. (Continued)

LMH6502

GMAX,VCM

BW vs. R

F

20067740

Gain vs. VG(±5V)

20067706

Gain vs. VG(±2.5V) Output Offset Voltage vs. VG(Typical Unit#1)

20067713

Output Offset Voltage vs. VG(Typical Unit#2) Output Offset Voltage vs. VG(Typical Unit#3)

20067754

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20067753

20067755

LMH6502

Typical Performance Characteristics Unless otherwise specified: V

=±5V, 25˚C, VG=V

S

= 0V, RF=1kΩ,RG= 174Ω, both inputs terminated in 50Ω,RL= 100Ω, Typical values, results referred to device
output. (Continued)

Output Offset Voltage vs.

±

VSfor various V

(Typical Unit#1)

20067761

Output Offset Voltage vs.±VSfor various V

(Typical Unit#3) Noise vs. Frequency (A

G

Output Offset Voltage vs.

(Typical Unit#2)

G

±

VSfor various V

=2)

VMAX

GMAX,VCM

G

20067762

Noise vs. Frequency (A

20067763

= 10) Noise vs. Frequency (A

VMAX

20067710

VMAX

20067725

= 100)

20067717

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Typical Performance Characteristics Unless otherwise specified: V

=±5V, 25˚C, VG=V

S

= 0V, RF=1kΩ,RG= 174Ω, both inputs terminated in 50Ω,RL= 100Ω, Typical values, results referred to device
output. (Continued)

LMH6502

−1dB Compression Output Voltage vs. Output Current

GMAX,VCM

HD2 & HD3 vs. P

THD vs. P

OUT

OUT

20067722

20067733

THD vs. P

OUT

HD2 & HD3 vs. V

20067726

20067718

G

20067719

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20067728

LMH6502

Typical Performance Characteristics Unless otherwise specified: V

=±5V, 25˚C, VG=V

S

= 0V, RF=1kΩ,RG= 174Ω, both inputs terminated in 50Ω,RL= 100Ω, Typical values, results referred to device
output. (Continued)

THD vs. V

G

VGBias Current vs. V

20067720

G

THD vs. V

G

Step Response Plot

GMAX,VCM

20067715

20067727

Step Response Plot Gain vs. VGStep

20067735

20067734

20067764

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Typical Performance Characteristics Unless otherwise specified: V

=±5V, 25˚C, VG=V

S

= 0V, RF=1kΩ,RG= 174Ω, both inputs terminated in 50Ω,RL= 100Ω, Typical values, results referred to device
output. (Continued)

LMH6502

GMAX,VCM

Feedthrough from V

Application Information

THEORY OF OPERATION

A simplified schematic is shown in Figure 1.+V
are buffered with closed loop voltage followers inducing a
signal current in Rg proportional to (+V

) - (−VIN), the dif-

IN

ferential input voltage. This current controls a current source
which supplies two well-matched transistor, Q1 and Q2.

The current flowing through Q2 is converted to the final
output voltage using R

and the output amplifier, U1. By

F

changing the fraction of the signal current "I" which flows
through Q2, the gain is changed. This is done by changing
the voltage applied differentially to the bases of Q1 and Q2.
For example, with V
off. With none of "I" flowing through R

= 0V, Q1 conducts heavily and Q2 is

G

, the LMH6502’s input

F

to output gain is strongly attenuated. With V
and the entire signal current flows through Q2 to R
ing maximum gain. With V

set to 1V, the bases of Q1 and

G

Q2 are set to approximately the same voltage, Q1 and Q2
have the same collector currents - equal to one half of the
signal current "I", thus the gain is approximately one half the
maximum gain.

FIGURE 1. LMH6502 Block Diagram

and −V

IN

=+2V,Q1isoff

G

produc-

F

20067741

G

20067765

CHOOSING R

F&RG

Maximum input amplitude and maximum gain are the two
key specifications that determine component values in a

IN

LMH6502 application.
The output stage op amp is a current-feedback type amplifier

optimized for R

=1kΩ.RGcan then be computed as:

F

(1)

To determine whether the maximum input amplitude will
overdrive the LMH6502, compute:

=(RG+ 3.0Ω) x 1.70mA (2)

V

DMAX

the maximum differential input voltage for linear operation. If
the maximum input amplitude exceeds the above V

DMAX

limit, then LMH6502 should either be moved to a location in
the signal chain where input amplitudes are reduced, or the
LMH6502 gain A

and RFshould be increased. The overall system perfor-

R

G

should be reduced or the values for

VMAX

mance impact is different based on the choice made. If the
input amplitude is reduced, re-compute the impact on signal­to-noise ratio. If A

is reduced, post LMH6502 amplifier

VMAX

gain, should be increased, or another gain stage added to
make up for reduced system gain. To increase R
compute the lowest acceptable value for R

>

590xV

R

Operating with R

G

larger than this value insures linear op-

G

DMAX

G

-3Ω (3)

and RF,

G

:

eration of the input buffers.

may be computed from selected RGand A

R

F

should be>=1kΩ for overall best performance, however R

<

1kΩ can be implemented if necessary using a loop gain

VMAX:RF

F

reducing resistor to ground on the inverting summing node of
the output amplifier (see application note QA-13 for details).

ADJUSTING OFFSET

Offset can be broken into two parts; an input-referred term
and an output-referred term. The input-referred offset shows
up as a variation in output voltage as V

is changed. This

G

can be trimmed using the circuit in Figure 2 by placing a low
frequency square wave (V

LOW

=0V,V

= 2V into VGwith

HIGH

www.national.com 14

Application Information (Continued)

V

= 0V, the input referred VOSterm shows up as a small

IN

square wave riding a DC value. Adjust R
square wave term to zero. After adjusting the input-referred
offset, adjust R
Finally, for inverting applications V

(with VIN=0,VG= 0) until V

14

may be applied to pin 6

IN

and the offset adjustment to pin 3. These steps will minimize
the output offset voltage. However, since the offset term itself
varies with the gain setting, the correction is not perfect and
some residual output offset will remain at in-between V
Also, this offset trim does not improve output offset tempera­ture coefficient.

to null the V

10

OUT

OS

is zero.

’s.

G

NOISE

Figure 3 describes the LMH6502’s output-referred spot
noise density as a function of frequency with A

VMAX

= 10V/V.
The plot includes all the noise contributing terms. However,
with both inputs terminated in 50Ω, the input noise contribu­tion is minimal. At A
input-referred spot noise density (e

= 10V/V, the LMH6502 has a typical

VMAX

) of 7.7nV/ flat-

in

band. For applications extending well into the flat-band re­gion, the input RMS voltage noise can be determined from
the following single-pole model:

(5)

LMH6502

20067743

FIGURE 2. Nulling the output offset voltage

GAIN ACCURACY

Defined as the actual gain compared against the theoretical
gain at a certain V

(results expressed in dB).

G

Theoretical gain is given by:

(4)

Where K = 1.72 (nominal) & V

= 90mV@room tempera-

C

ture.
ForaV

range, the value specified in the tables represents

G

the worst case accuracy over the entire range. The "Typical"
value would be the worst case difference between the "Typi­cal Gain" and the "Theoretical gain". The "Max" value would
be the worst case difference between the max/min gain limit
and the "Theoretical gain".

GAIN MATCHING

Defined as the limit on gain variation at a certain V

(ex-

G

pressed in dB). Specified as "Max" only (no "Typical"). For a

range, the value specified represents the worst case

V

G

matching over the entire range. The "Max" value would be
the worst case difference between the max/min gain limit
and the typical gain.

20067710

FIGURE 3. Output Referred Voltage Noise vs.

Frequency

CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION
BOARD

A good high frequency PCB layout including ground plane
construction and power supply bypassing close to the pack­age are critical to achieving full performance. The amplifier is
sensitive to stray capacitance to ground at the I

−

input (pin

12); keep node trace area small. Shunt capacitance across
the feedback resistor should not be used to compensate for
this effect. For best performance at low maximum gains

<

(A

10) +RGand -RGconnections should be treated in

VMAX

a similar fashion. Capacitance to ground should be mini­mized by removing the ground plane from under the body of

. Parasitic or load capacitance directly on the output (pin

R

G.

10) degrades phase margin leading to frequency response
peaking.

The LMH6502 is fully stable when driving a 100Ω load. With
reduced load (e.g. 1kΩ) there is a possibility of instability at
very high frequencies beyond 400MHz especially with a
capacitive load. When the LMH6502 is connected to a light
load as such, it is recommended to add a snubber network to
the output (e.g. 100Ω and 39pF in series tied between the
LMH6502 output and ground). C

can also be isolated from

L

the output by placing a small resistor in series with the output
(pin 10).

Component parasitics also influence high frequency results.
Therefore it is recommended to use metal film resistors such
as RN55D or leadless components such as surface mount
devices. High profile sockets are not recommended.

www.national.com15

Application Information (Continued)

National Semiconductor suggests the following evaluation

LMH6502

boards as a guide for high frequency layout and as an aid in
device testing and characterization:

Device Package Evaluation Board

Part Number

LMH6502MA SOIC-14 CLC730033

LMH6502MT TSSOP-14 CLC730146

The evaluation board is shipped when a device sample
request is placed with National Semiconductor

SINGLE SUPPLY OPERATION

It is possible to operate the LMH6502 with a single supply. To
do so, tie pin 11 (GND) to a potential about mid point
between V
Figure 5.

+

and V−. Two examples are shown in Figure 4 &

FIGURE 4. AC Coupled Single Supply VGA

20067746

OPERATING AT LOWER SUPPLY VOLTAGES

The LMH6502 is rated for operation down to 5V supplies (V

-V−). There are some specifications shown for operation at

±

2.5V within the data sheet (i.e. Frequency Response,

CMRR, PSRR, Gain vs. V

, etc.). Compared to±5V opera-

G

tion, at lower supplies:
a) V

range shifts lower.

G

Here are the approximate expressions for various V
voltages as a function of V+:

+

+

0.2xV++1

V

G

V

G_MIN

V

G_MID

V

G_MAX

b) V

G_LIMIT

TABLE 1. V

Definition Based on V

G

Definition Expression (V)

Gain Cut-off 0.2 x V+−1

A

/2 0.2 x V

VMAX

A

VMAX

(maximum permissible voltage on VG)isre­duced. This is due to limitations within the device arising
from transistor headroom. Beyond this limit, device per­formance will be affected (non-destructive). This could
reveal itself as premature high frequency response roll-

±

off. With
V

G

2.5V supplies, V

= 1.5V is needed to get maximum gain. This means

is below 1.1V whereas

G_LIMIT

that operating under these conditions has reduced the
maximum permissible voltage on V
what is needed to get Max gain. If supply voltages are
asymmetrical with V

range could result; for example, with V+= 2V, and V

V

G

= −3V, V

G_LIMIT

+

being lower, further "pinching" of

= 0.40V which results in maximum gain

to a level below

G

being 2.5dB less than what would be expected when V
is higher.

c) "Max_gain" reduces. There is an intrinsic reduction in

max gain when the total supply voltage is reduced (see
Typical Performance Characteristics plots for Gain vs. V
(VS=±2.5V). In addition, there is the more drastic
mechanism described in "b" above. Beyond V

G_LIMIT

high frequency response is also effected.

Application Circuits

+

G

−

S

G

,

20067747

FIGURE 5. Transformer Coupled Single Supply VGA

www.national.com 16

AGC LOOP

Figure 6 shows a typical AGC circuit. The LMH6502 is
followed up with a LMH6714 for higher overall gain. The
output of the LMH6714 is rectified and fed to an inverting
integrator using a LMH6657 (wideband voltage feedback op
amp). When the output voltage, V

, is too large the inte-

OUT

grator output voltage ramps down reducing the net gain of
the LMH6502 and V

. If the output voltage is too small,

OUT

the integrator ramps up increasing the net gain and the
output voltage. Actual output level is set with R

. To prevent

1

shifts in DC output voltage with DC changes in input signal
level, trim pot R

is provided. AGC circuits are always limited

2

in the range of input signals over which constant output level
can be maintained. In this circuit, we would expect that
reasonable AGC action could be maintained for at least
40dB. In practice, rectifier dynamic range limits reduce this
slightly.

Application Circuits (Continued)

LMH6502

20067748

FIGURE 6. Automatic Gain Control (AGC) Loop

FREQUENCY SHAPING

Frequency Shaping Frequency shaping and bandwidth extension of the LMH6502 can be accomplished using parallel networks
connected across the R

ports. The network shown in the Figure 7 schematic will effectively extend the LMH6502’s bandwidth.

G

20067749

FIGURE 7. Frequency Shaping

www.national.com17

Physical Dimensions inches (millimeters) unless otherwise noted

LMH6502

14-Pin SOIC

NS Package Number M14A

14-Pin TSSOP

NS Package Number MTC14

www.national.com 18

Notes

LMH6502 Wideband, Low Power, Linear-in-dB Variable Gain Amplifier

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can be reasonably expected to cause the failure of
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