National Semiconductor LMH1981 Technical data

LMH1981 Multi-Format Video Sync Separator

December 2006

General Description

The LMH1981 is a high performance multi-format sync separator ideal for use in a wide range of video applications, such as broadcast and professional video equipment and HDTV/ DTV systems.

The input accepts standard analog SD/ED/HD video signals with either bi-level or tri-level sync, and the outputs provide all of the critical timing signals in CMOS logic, which swing from rail-to-rail (VCC and GND) including Composite, Horizontal, and Vertical Syncs, Burst/Back Porch Timing, Odd/ Even Field, and Video Format Outputs. HSync features very low jitter on its leading (falling) edge, minimizing external circuitry needed to clean and reduce jitter in subsequent clock generation stages.

The LMH1981 automatically detects the input video format, eliminating the need for programming using a microcontroller, and applies precise 50% sync slicing to ensure accurate sync extraction at OH, even for inputs with irregular amplitude from improper termination or transmission loss. Its unique Video Format Output conveys the total horizontal line count per field as an 11-bit binary serial data stream, which can be decoded by the video system to determine the input video format and enable dynamic adjustment of system parameters, i.e.: color space or scaler conversions. The LMH1981 is available in a 14-pin TSSOP package and operates over a temperature range of −40°C to +85°C.

Connection Diagram

14-Pin TSSOP

Top View

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Features

Standard analog video sync separation for NTSC, PAL,

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480I/P, 576I/P, 720P, and 1080I/P/PsF from Composite Video (CVBS), S-Video (Y/C), and Component Video (YPBPR/GBR) interfaces

Bi-level & tri-level sync compatible

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Composite, Horizontal, and Vertical Sync Outputs

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Burst/Back Porch Timing, Odd/Even Field, and Video

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Format Outputs Superior jitter performance on leading edge of HSync

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Automatic video format detection

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50% sync slicing for video inputs from 0.5 VPP to 2 V

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3.3V to 5V supply operation

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Applications

Broadcast and Professional Video Equipment

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HDTV/DTV Systems

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Genlock Circuits

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Video Capture Devices

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Set-Top Boxes (STB) & Digital Video Recorders (DVR)

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Video Displays

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Pin Descriptions

Pin No. Pin Name Pin Description

1 R

2, 5, 10 GND Ground

3, 6, 11 V

4 V

7 HSOUT Horizontal Sync Output

8 VSOUT Vertical Sync Output

9 VFOUT Video Format Output

12 CSOUT Composite Sync Output

13 BPOUT Burst/Back Porch Timing Output

14 OEOUT Odd/Even Field Output

EXT

Bias Current External Resistor

Supply Voltage

Video Input

FIGURE 1. Pinout

Ordering Information

Package Part Number Package Marking Transport Media NSC Drawing

14-Pin TSSOP

LMH1981MT

LMH1981MTX 2.5k Units Tape and Reel

LMH1981MT

94 Units/Rail

MTC14

Absolute Maximum Ratings (Notes 1, 7)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/

LMH1981

Distributors for availability and specifications.

Storage Temperature Range −65°C to +150°C Lead Temperature (soldering 10 sec.) 300°C Junction Temperature (T

Thermal Resistance (θJA)

ESD Tolerance (Note 2) Human Body Model 3.5 kV Machine Model 350V Charge-Device Model 1.0 kV Supply Voltage, V

Video Input, V

−0.3V to VCC + 0.3V

0V to 5.5V

Operating Ratings (Note 1)

Temperature Range (Note 3) −40°C to +85°C V

Input Amplitude, V

IN-AMPL

Electrical Characteristics (Note 4)

Unless otherwise specified, all limits are guaranteed for TA = 25°C, VCC = V RL = 10 kΩ, CL < 10 pF. Boldface limits apply at the temperature extremes. See Figure 2 for Test Circuit.

Symbol Parameter Conditions Min

Supply Current No input signal VCC = 3.3V 9.5 11.5

Video Input Specifications

IN-SYNC

Input Sync Amplitude Amplitude from negative sync tip to video

blanking level for SD/EDTV bi-level sync (Notes 8, 9, 11)

Amplitude from negative to positive sync tips for HDTV tri-level sync (Notes 8, 10, 11)

IN-CLAMP

IN-SLICE

Input Sync Tip Clamp Level 0.7 V

Input Sync Slice Level Level between video blanking & sync tip for

SD/EDTV and between negative & positive sync tips for HDTV

Logic Output Specifications (Note 12)

Output Logic 0 See output load conditions

above

Output Logic 1 See output load conditions

above

SYNC-LOCK

Sync Lock Time Time for the output signals to be correct after

the video signal settles at VIN following a significant input change. See Start-Up Time section for more information

VSOUT

Vertical Sync Output Pulse Width

See Figures 3, 4, 5, 6, 7, 8 for SDTV, EDTV & HDTV Vertical Interval Timing

= V

CC2

= V

CC3

CC1

(Note 6)

VCC = 5V 11 13.5

0.14 0.30 0.60

0.30 0.60 1.20

VCC = 3.3V 0.3

VCC = 5V 0.5

VCC = 3.3V 3.0

VCC = 5V 4.5

JMAX

) (Note 3)

+150°C

52°C/W

3.3V −5% to 5V +5%

= 3.3V, R

(Note 5)

140 mV to VCC–V

= 10 kΩ 1%,

EXT

Typ

Max

(Note 6)

IN-CLAMP

Units

50 %

2 V

periods

3 H periods

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Tables.

Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)

Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

Note 3: The maximum power dissipation is a function of T PD = (T

Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA.

Note 5: Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.

Note 6: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using the Statistical Quality Control (SQC) method.

Note 7: All voltages are measured with respect to GND, unless otherwise specified.

Note 8: V

Note 9: Tested with 480I signal.

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- TA)/θJA . All numbers apply for packages soldered directly onto a PC board.

J(MAX)

IN-AMPL

plus V

should not exceed VCC.

IN-CLAMP

, θJA. The maximum allowable power dissipation at any ambient temperature is

J(MAX)

Note 10: Tested with 720P signal.

Note 11: Maximum voltage offset between 2 consecutive input horizontal sync tips must be less than 25 mVPP.

Note 12: Outputs are negative-polarity logic signal, except for odd/even field and video format outputs.

LMH1981 Test Circuit

LMH1981

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FIGURE 2. Test Circuit

The LMH1981 test circuit is shown in Figure 2. The video generator should provide a low-noise, broadcast-quality signal over 75Ω coaxial cable which should be impedance-matched with a 75Ω load termination resistor to prevent unwanted signal distortion. The output waveforms should be monitored using a low-capacitance probe on an oscilloscope with at least 500 MHz bandwidth. See the PCB LAYOUT CONSIDERATIONS section for more information about signal and supply trace routing and component placement.

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SDTV Vertical Interval Timing (NTSC, PAL, 480I, 576I)

LMH1981

FIGURE 3. NTSC Odd Field Vertical Interval

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FIGURE 4. NTSC Even Field Vertical Interval

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EDTV Vertical Interval Timing (480P, 576P)

LMH1981

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FIGURE 5. 480P Vertical Interval

HDTV Vertical Interval Timing (720P, 1080P)

FIGURE 6. 720P (1080P) Vertical Interval

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