National Semiconductor LMH0340 Technical data

PRELIMINARY

April 10, 2008

LMH0340, LMH0040, LMH0070, LMH0050 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver with LVDS Interface

LMH0340, LMH0040, LMH0070, LMH0050 3Gbps, HD, SD, DVB-ASI SDI Serializer and Cable

Driver with LVDS Interface

General Description

The LMH0340 3 Gbps SDI Serializer is part of National’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. An FPGA Host will format data with supplied IP such that the output of the LMH0340 is compliant with the requirements of DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards.

The interface between the SER (Serializer) and the FPGA consists of a 5 bit wide LVDS data bus, an LVDS clock and an SMBus interface. The LMH0340 / LMH0040 / LMH0070 SER devices include an integrated cable driver which is fully compliant with all of the SMPTE specifications listed above. Refer to Table 1 for a complete listing of single channel serializers currently offered in this family. The LMH0050 has a CML output driver that can drive a differential transmission line or interface to a cable driver.

The FPGA-Attach SER/DES family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The SER is packaged in a physically small 48 pin LLP package.

General Block Diagram

Key Specifications

Output compliant with SMPTE 424M, SMPTE 292M,

■

SMPTE 259M-C and DVB-ASI Typical power dissipation: 440 mW

■

30 ps typical output jitter (HD, 3G)

■

Features

LVDS Interface to Host FPGA

■

No external VCO or clock ref required

■

Integrated Variable Output Cable Driver

■

3.3V SMBus configuration interface

■

Integrated TXCLK PLL cleans clock noise

■

Small 48pin LLP package

■

Applications

SDI interfaces for:

■

Video Cameras

—

DVRs

—

Video Switchers

—

Video Editing Systems

—

30017001

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

Pin Descriptions

Pin Name Type Description

LVDS Input Interface

TX[4:0]+ TX[4:0]-

TXCLK+ TXCLK-

Serial Output Interface

TXOUT+ Output, CML Serial Digital Interface Output Pin

TXOUT- Output, CML Serial Digital Interface Output Pin

SMBus Interface

SDA I/O, LVCMOS SMBus Data I/O Pin

SCK Input, LVCMOS SMBus Clock Input Pin

LMH0340, LMH0040, LMH0070, LMH0050

SMB_CS Input, LVCMOS SMBus Chip Select Input Pin

Control and Configuration Pins

RESET Input, LVCMOS Reset Input Pin

LOCK Output, LVCMOS PLL LOCK Status Output

DVB_ASI Input, LVCMOS DVB_ASI Select Input

GPIO[2:0] I/O, LVCMOS General Purpose Input / Output

RSVD_H Input, LVCMOS Configuration Input – Must tie High

Analog Inputs

SET

LF_CP Input, analog Loop Filter Connection

LF_REF Input, analog Loop Filter Reference

DNC Do Not Connect – Leave Open

Power Supply and Ground

DD3V3

DDPLL

DD2V5

GND Ground Ground connection – The DAP (large center pad) is the primary GND connection

Input, LVDS LVDS Data Input Pins

Five channel wide DDR interface. Internal 100Ω termination.

Input, LVDS LVDS Clock Input Pins

DDR Interface. Internal 100Ω termination.

Non-Inverting Output

Inverting Output

Device is selected when High.

H = normal mode L = device in RESET

H = unlock condition L = Device is Locked

H = DVB_ASI Mode enabled L = Normal Mode enabled

Software configurable I/O pins.

Pull High via 5 kΩ resistor to V

DD3V3

Input, analog Serial Output Amplitude Control

Resistor connected from this pin to ground to set the signal amplitude. Nominally

8.06kΩ for 800mV output (SMPTE).

Power 3.3V Power Supply connection

Power 3.3V PLL Power Supply connection

Power 2.5V Power Supply connection

for the device and must be connected to Ground along with the GND pins.

TABLE 1. Feature Table

Device

SMPTE 424M Support (3G)

SMPTE 292M Support (HD)

SMPTE 259M Support (SD)

DVB-ASI

Support

LMH0340 X X X X X

LMH0040 X X X X

LMH0070 X X X

LMH0050 X X X

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SMPTE compliant

Cable Driver

LMH0340, LMH0040, LMH0070, LMH0050

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (V

LVCMOS input voltage −0.3V to (V

LVCMOS output voltage −0.3V to (V

) −0.3V to +4.0V

DD3V3

) −0.3V to +3.0V

DD2V5

DD3V3

+0.3V)

SMBus I/O voltage -0.3V to +3.6V LVDS Input Voltage -0.3V to +3.6V Junction Temperature +150°C Storage Temperature −65° to 150°C Thermal Resistance—

Junction to Ambient—θ

ESD Rating—Human Body Model,

25°C/W

≥±8kV

1.5 KΩ, 100 pF

Recommended Operating Conditions

Parameter Min Typ Max Units

Supply Voltage (V

Supply noise amplitude (10 Hz to 50 MHz) 100 mV

Ambient Temperature −40 +25 +85 °C

Case Temperature 100 °C

TXCLK input frequency – LMH0340 27 297 MHz

TXCLK input frequency – LMH0040 27 149 MHz

TXCLK input frequency – LMH0070 26.5 27 28 MHz

TXCLK input frequency – LMH0050 27 149 MHz

LVDS PCB board trace length (mismatch <2%) 25 cm

Output Driver Pullup Resistor Termination Voltage (Note 10) 2.5 2.625 V

-GND) 3.135 3.3 3.465 V

DD3V3

-GND) 2.375 2.5 2.625 V

DD2V5

P-P

Electrical Characteristics

Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)

Symbol Parameter Condition Min Typ Max Units

DD2.5

2.5V supply current for LMH0340, LMH0040, or LMH0070

2.97 Gbps 93 102 mA

1.485 Gbps 80 87 mA

270 Mbps 63 69 mA

2.5V supply current for LMH0050 1.485 Gbps 87 95 mA

270 Mbps 70 75 mA

DD3.3

3.3V supply current for LMH0340, LMH0040, or LMH0070

2.97 Gbps 73 85 mA

1.485 Gbps 73 85 mA

270 Mbps 73 85 mA

3.3V supply current for LMH0050 1.485 Gbps 73 85 mA

270 Mbps 73 85 mA

PD Power Consumption LMH0340 - 2.97 Gbps 475 545 mW

LMH0040 - 1.485 Gbps 440 510 mW

LMH0050 - 1.485 Gbps 460 525 mW

LMH0050 - 270 Mbps 415 485 mW

LMH0070 - 270 Mbps 400 470 mW

Control Pin Electrical Characteristics

Over supply and Operating Temperature ranges unless otherwise specified. Applies to DVB_ASI, RESET (Note 2)

Symbol Parameter Condition Min Typ Max Units

High Level Input Voltage 2.0 V

Low Level Input Voltage 0 0.8 V

High Level Output Voltage IOH=−2 mA 2.7 3.3 V

Low Level Output Voltage IOL=2 mA 0.3 V

Input Clamp Voltage ICL=−18 mA -0.79 -1.5 V

, GPIO[2:0] and LOCK.

DD3V3

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Symbol Parameter Condition Min Typ Max Units

Input Current VIN=0.4V, 2.5V or V

Output Short Circuit Current V

=0V -40 mA

OUT

-35 35

LVDS Input Electrical Characteristics

Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)

Symbol Parameter Condition Min Typ Max Units

LVIN

Differential Input High threshold 0.05V<VCM<2.4V +100 mV

Differential Input Low threshold −100 mV

Input Impedance Measured between LVDS pairs 85 100 115

LVDS Switching Characteristics

Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)

Symbol Parameter Condition Min Typ Max Units

LMH0340, LMH0040, LMH0070, LMH0050

CIP

CIT

CIH

CIL

XIT

STC

HTC

TxCLKIN Period See Figure 1 3.2 2T 37 ns

TxCLKIN Transition Time See Figure 2 0.5 1.0 3.0 ns

TxCLKIN IN High Time See Figure 1 0.7T T 1.3T ns

TxCLKIN IN Low Time See Figure 1 0.7T T 1.3T ns

TxIN Transition Time 0.15 3 ns

TxIN Setup to TxCLKIN See Figure 1, (Note 11) -550 ps

TxIN Hold to TxCLKIN 900 ps

μA

Ω

FIGURE 1. LVDS Input Timing Diagram

FIGURE 2. Transmit Clock Transition Times

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30017002

30017003

SMBus Input Electrical Characteristics

Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)

Symbol Parameter Condition Min Typ Max Units

SIL

SIH

SPULLUP

Data, Clock Input Low Voltage 0.8 V

Data, Clock Input High Voltage 2 V

Current through pull-up resistor or

(Note 3) 4 mA

SDD

current source

SDD

SLEAKB

SLEAKP

Nominal Bus Voltage 2.375 3.6 V

Input Leakage per bus segment (Note 3) −200 200

Input Leakage per pin −10 10

Capacitance for SMBdata and

(Notes 3, 4) 10 pF

μA

SMBclk

STERM

Termination Resistance V

(Notes 5, 4, 3) 1000

SDD3V3

Ω

SMBus Switching Characteristics

Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)

Symbol Parameter Condition Min Typ Max Units

SMB

BUF

HD:STA

SU:STA

SU:STO

HD:DAT

SU:DAT

LOW

HIGH

SU:CS

POR

Bus Operating Frequency 10 100 kHz

Bus free time between stop and start

4.7

μs

condition

Hold time after (repeated) start

At I

= MAX 4.0

SPULLUP

μs

condition. After this period, the first clock is generated

Repeated Start condition setup time 4.7

Stop Condition setup time 4.0

μs

Data hold time 300 ns

Data setup time 250 ns

Clock Low Time 4.7

Clock High Time 4.0 50

μs

Clock/data fall time 20% to 80% 300 ns

Clock/data rise time 1000 ns

SMB_CS setup time 30 ns

Time in which a device must be

500 ms

operational after power on

LMH0340, LMH0040, LMH0070, LMH0050

(levels are V

SIL

and V

SIH

30017004

)

FIGURE 3. SMBus Timing Parameters

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SDI Output Characteristics — LMH0340 / LMH0040 / LMH0070

Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)

Symbol Parameter Condition Min Typ Max Units

DR SDI Output Datarate LMH0340 270 2,970 Mbps

Δt

LMH0340, LMH0040, LMH0070, LMH0050

RL Output Return Loss — EVK

SDI Output Voltage

into 75Ω load

720 800 880 mV

LMH0040 270 1,485 Mbps

LMH0070 270 Mbps

SDI Output Rise Time 2.97 Gbps 90 135 ps

1.485 Gbps 90 220 ps

<1.485 Gbps 400 700 1000 ps

SDI Output Fall Time 2.97 Gbps 90 135 ps

1.485 Gbps 90 220 ps

<1.485 Gbps 400 700 1000 ps

Mismatch between rise and fall time

≥1.485 Gbps

30 ps

(Note 9)

Propagation Delay Latency See Figure 4 9.5 TXCLK

Peak to Peak Alignment Jitter

≥1.485 Gbps(Note 6)

30 50 ps

270 Mbps(Note 6) 100 200 ps

Measured 5 MHz to 1485 MHz 15 20 dB Specification (Note 12)

Output Overshoot (Note 9)

Measured 1485 MHz to 2970

10 15 dB

MHz

2.97 Gbps 8 %

1.485 Gbps 5 %

270 Mbps 2 %

cycle

CML Output Characteristics — LMH0050

Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)

Symbol Parameter Condition Min Typ Max Units

DR Data Rate 270 1485 Mbps

OUT

Output Voltage

into 100 Ω differential load

1175 1450 mV

Output Rise Time 100 ps

Output Fall Time 100 ps

Peak-to-Peak Alignment Jitter 1.485 Gbps 25 50 ps

Output Termination Resistance Output Pin to V

Pin 40 50 60

DD2V5

Ω

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Device Switching Characteristics

Over supply and Operating Temperature ranges unless otherwise specified. (Note 2)

Symbol Parameter Condition Min Typ Max Units

TPLD

Note 1: “Absolute Maximum Ratings” are limits beyond which the safety of the device cannot be guaranteed. It is not implied that the device will operate up to these limits.

Note 2: Typical Parameters measured at V

Note 3: Recommended value—Parameter is not tested.

Note 4: Recommended maximum capacitance load per bus segment is 400 pF.

Note 5: Maximum termination voltage should be identical to the device supply voltage.

Note 6: Measured in accordance with SMPTE RP184. 100% production tested.

Note 7: Register 0x30'h bits [7:5] is at default value of 011'b

Note 8: Measured with R

Note 9: Specification guaranteed by characterization.

Note 10: Applies to LMH0340, LMH0040, and LMH0070.

Note 11: Parameter uses default settings in registers: 0x24'h and 0x30'h.

Note 12: Output Return Loss specification applies to measurement on the EVK PCB (LMH0340 ALP Daughter Card) per SMPTE requirements.

Device Lock Time 2.97 Gbps 10 ms

1.485 Gbps 11 ms

270 Mbps 15 ms

=3.3V, V

DD3V3

= 8.06 kΩ and register 0x69'h at default value.

SET

=2.5V, TA=25°C. They are for reference purposes and are not production tested.

DD2V5

LMH0340, LMH0040, LMH0070, LMH0050

FIGURE 4. LVDS Interface Propagation Delay

30017005

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