National Semiconductor LM97593 Technical data

LM97593 Dual ADC / Digital Tuner / AGC

March 12, 2008

General Description

The LM97593 Dual ADC / Digital Tuner / AGC IC is a two channel digital downconverter (DDC) with integrated 12-bit analog-to-digital converters (ADCs) and automatic gain control (AGC). The LM97593 further enhances National’s Diversity Receiver Chipset (DRCS) by integrating a wide-bandwidth dual ADC core with the DDC. The complete DRCS includes one LM97593 Dual ADC / Digital Tuner / AGC and two CLC5526 digitally controlled variable gain amplifiers (DVGAs). This system allows direct IF sampling of signals up to 300MHz for enhanced receiver performance and reduced system costs. A block diagram for a DRCS-based narrowband communications system is shown in Figure 1.

The LM97593 offers high dynamic range digital tuning and filtering based on hard-wired digital signal processing (DSP) technology. Each channel has independent tuning, phase offset, filter coefficients, and gain settings. Channel filtering is performed by a series of three filters. The first is a 4-stage Cascaded Integrator Comb (CIC) filter with a programmable decimation ratio from 8 to 2048. Next there are two symmetric FIR filters, a 21-tap and a 63-tap, both with independent programmable coefficients. The first FIR filter decimates the data by 2, the second FIR decimates by either 2 or 4. Channel filter bandwidth at 52MSPS ranges from ±650kHz down to ±1.3kHz. At 65MSPS, the maximum bandwidth increases to ±812kHz.

The LM97593’s AGC controller monitors the ADC output and controls the ADC input signal level by adjusting the DVGA setting. AGC threshold, deadband+hysteresis, and the loop time constant are user defined. Total dynamic range of greater than 123dB full-scale signal to noise in a 200kHz bandwidth can be achieved with the Diversity Receiver Chipset.

Features

100% Software compatible with the CLC5903

■

Pin compatible with the CLC5903 except for the analog

■

input and reference section 123 dB dynamic range with CLC5526 DVGA (200kHz)

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On-chip precision reference

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User Programmable AGC with enhanced Power Detector

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Channel Filters include a Fourth Order CIC followed by 21-

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tap and 63-tap Symmetric FIRs Flexible output formats

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Serial and Parallel output ports

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JTAG Boundary Scan

■

8-bit Microprocessor Interface

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128 pin PQFP

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Key Specifications

Internal ADC Resolution 12 Bits

■

Sample Rate 65 MSPS

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SNR (fIN = 250MHz, 11-bit, Nyquist) 62 dBFS (typ)

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SNR (fIN = 250MHz, 200kHz) 83 dBFS (typ)

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SFDR (fIN = 250MHz, 11-bit, Nyquist) 68 dBFS (typ)

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Full Power Bandwidth 650 MHz (typ)

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Power Consumption (65MSPS) 560 mW (typ)

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Applications

Cellular Basestations

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GSM / GPRS / EDGE / GSM Phase 2 Receivers

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Satellite Receivers

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Wireless Local Loop Receivers

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Digital Communications

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Block Diagram 1

30008701

FIGURE 1. Diversity Receiver Chipset Block Diagram

Connection Diagram

LM97593

Ordering Information

Industrial (−40°C to +85°C) Package

Block Diagram 2

30008702

FIGURE 2. LM97593VH PQFP Pinout

LM97593VH 128 Pin PQFP

LM97593EB Evaluation Board

30008703

FIGURE 3. LM97593 Block Diagram

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Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

13 27

14 26

15 24

16 23

17 22

VINA− VINB−

VINA+ VINB+

REF

COM

VRPA VRPB

VRNA VRNB

Analog Input

Control / Analog Input

A B

Analog Output

8 REFSEL/DCS Control Input

DIGITAL I/O

30 PD Input

45 MR Input

82 78

127:125 40:42

124 43

AOUT BOUT

AGAIN[2:0] BGAIN[2:0]

ASTROBE BSTROBE

Output

80 SCK Output

Negative differential input signal for the 'A' channel Negative differential input signal for the 'B' channel

Positive differential input signal for the 'A' channel Positive differential input signal for the 'B' channel

Reference Select Pin / External Reference Voltage Input Input differential full scale swing = 2 * V V

= VA to VA - 0.3V: Reference Voltage = 1.0 V (Internal)

REF

= 0.8V to 1.5V: Reference Voltage = V

REF

Common Mode reference voltage for the 'A' channel Common Mode reference voltage for the 'B' channel These pins may be loaded to 1 mA for use as temperature stable 1.5V references.

Upper reference voltage for the 'A' channel Upper reference voltage for the 'B' channel

Lower reference voltage for the 'A' channel Lower reference voltage for the 'B' channel

This is a three-state pin. V REFSEL/DCS = AGND: the internal reference is enabled and duty cycle correction is applied to the ADC input clock (CK). REFSEL/DCS = V cycle correction is applied to the ADC input clock (CK). REFSEL/DCS = VA: DCS is on, the internal reference is disabled. Apply A 0.8-1.2V external reference to the V

POWER DOWN, when high both ADCs are powered down, when low, both ADCs are enabled

MASTER RESET, Active low Resets all registers within the chip. ASTROBE and BSTROBE are asserted during MR.

SERIAL OUTPUT DATA, Active high The 2's complement serial output data is transmitted on these pins, MSB first. The output bits change on the rising edge of SCK (falling edge if SCK_POL=1) and should be captured on the falling edge of SCK (rising if SCK_POL=1). These pins are tri-stated at power up and are enabled by the SOUT_EN control register bit. See Figure 13 and Figure 34 timing diagrams. In Debug Mode AOUT=DEBUG[1], BOUT=DEBUG[0].

OUTPUT DATA TO DVGA, Active high 3 bit bus that sets the gain of the DVGA determined by the AGC circuit.

DVGA STROBE, Active low Strobes the data into the DVGA. See Figure 7 and Figure 41 timing diagrams.

SERIAL DATA CLOCK, Active high or low The serial data is clocked out of the chip by this clock. The active edge of the clock is user programmable. This pin is tri-stated at power up and is enabled by the SOUT_EN control register bit. See Figure 13 and Figure 34 timing diagrams. In Debug Mode outputs an appropiate clock for the debug data. If RATE=0 the input CK duty cycle will be reflected to SCK.

REF

(External)

REF

= V

COM

A or V

COM

: the internal reference is enabled and no duty

COM

REF

COM

pin.

LM97593

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Pin No. Symbol Equivalent Circuit Description

SERIAL DATA CLOCK INPUT, Active high or low

LM97593

99 SCK_IN Input

Data bits from a serial daisy-chain slave are clocked into a serial daisychain master on the falling edge of SCK_IN (rising if SCK_POL=1 on the slave). Tie low if not used.

SERIAL FRAME STROBE, Active high or low The serial word strobe. This strobe delineates the words within the serial output streams. This strobe is a pulse at the beginning of each serial

81 SFS Output

word (PACKED=0) or each serial word I/Q pair (PACKED=1). The polarity of this signal is user programmable. This pin is tri-stated at power up and is enabled by the SOUT_EN control register bit. See and timing diagrams. In Debug Mode SFS=DEBUG[2].

84, 86:88, 90, 91, 93:97, 104:106, 108, 109

POUT[15:0] Output

PARALLEL OUTPUT DATA, Active high The output data is transmitted on these pins in parallel format. The

POUT_SEL[2:0] pins select one of eight 16-bit output words. The POUT_EN pin enables these outputs. POUT[15] is the MSB. In Debug

Mode POUT[15:0]=DEBUG[19:4].

PARALLEL OUTPUT DATA SELECT, Active high The 16-bit output word is selected with these 3 pins according to . Not

112:114 POUT_SEL[2:0] Input

used in Debug Mode. For a serial daisy-chain master, POUT_SEL

[2:0] become inputs from the slave: POUT_SEL[2]=SFS POUT_SEL[1]=BOUT

not used.

PARALLEL OUTPUT ENABLE. Active low

111 POUT_EN Input

This pin enables the chip to output the selected output word on the POUT[15:0] pins. Not used in Debug Mode. Tie high if not used.

READY FLAG, Active high or low The chip asserts this signal to identify the beginning of an output sample

77 RDY Output

period (OSP). The polarity of this signal is user programmable. This signal is typically used as an interrupt to a DSP chip, but can also be used as a start pulse to dedicated circuitry. This pin is active regardless of the state of SOUT_EN. In Debug Mode RDY=DEBUG[3].

INPUT CLOCK. Active high

37 CK Input

The clock input to the chip. The The VINA and VINB analog input signals are sampled on the rising edge of this signal. SI on the rising edge of CK.

SYNC IN. Active low The sync input to the chip. The decimation counters, dither, and NCO

46 SI Input

phase can be synchronized by SI. This sync is clocked into the chip on the rising edge of CK. Tie this pin high if external sync is not required. All sample data is flushed by SI. To properly initialize the DVGA ASTROBE and BSTROBE are asserted during SI.

DATA BUS. Active high 62, 63, 69:73, 75

D[7:0] Input/Output

This is the 8 bit control data I/O bus. Control register data is loaded into

the chip or read from the chip through these pins. The chip will only drive

output data on these pins when CE is low, RD is low, and WR is high.

ADDRESS BUS. Active high

These pins are used to address the control registers within the chip.

48, 50, 52:57 A[7:0] Input

Each of the control registers within the chip are assigned a unique

address. A control register can be written to or read from by setting A

[7:0] to the register’s address and setting CE, RD, and WR

appropriately.

READ ENABLE. Active low 59 RD Input

This pin enables the chip to output the contents of the selected register

on the D[7:0] pins when CE is also low.

, and POUT_SEL[0]=AOUT

SLAVE

. Tie low if

SLAVE

is clocked into the chip

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Pin No. Symbol Equivalent Circuit Description

WRITE ENABLE. Active low

58 WR Input

This pin enables the chip to write the value on the D[7:0] pins into the selected register when CE is also low. This pin can also function as RD/ CE if RD is held low. See for details.

CHIP ENABLE. Active low This control strobe enables the read or write operation. The contents of

60 CE Input

the register selected by A[7:0] will be output on D[7:0] when RD is low and CE is low. If WR is low and CE is low, then the selected register will be loaded with the contents of D[7:0].

116 TDO Output TEST DATA OUT. Active high

117 TDI Input TEST DATA IN. Active high with pull-up

118 TMS Input TEST MODE SELECT. Active high with pull-up

119 TCK Input TEST CLOCK. Active high. Tie low if JTAG is not used.

TEST RESET. Active low with pull-up

121 TRST Input

Asynchronous reset for TAP controller. Tie low or to MR if JTAG is not used.

SCAN ENABLE. Active low with pull-up

122 SCAN_EN Input

Enables access to internal scan registers. Tie high. Used for manufacturing test only!

Digital Power Supplies

38, 39, 64, 79, 92, 102,

DDC Output Driver Power I/O Power Supply, 3.3V nominal. Quantity 8.

107, 128

1, 47, 61, 68, 83, 89, 98, 110

49, 74, 85, 115, 123

DRGND

D18

DDC Output Driver Ground

I/O Ground Return. Quantity 8.

DDC Core Power DSP Digital Core Power Supply, 1.8V nominal. Quantity 5.

44, 51, 65, 66, 76, 103,

D18GND DDC Core Ground DSP Digital Core Ground Return. Quantity 7.

120

4, 6, 31, 34

ADC Digital Power ADC Digital Logic Power Supply, 3.3V nominal. Quantity 4.

5, 7, 32, 33 DGND ADC Digital Ground ADC Digital Logic Ground Return. Quantity 4.

Analog Power Supplies

10, 11, 19, 25, 29

2, 9, 12, 18, 20, 28

ADC Analog Power ADC Analog Power Supply, 3.3V nominal. Quantity 5.

AGND ADC Analog Ground ADC Analog Ground Return. Quantity 6.

Unconnected Pins

3, 35, 36, 67, 100, 101

NC NC Not Connected. These pins should be left floating.

LM97593

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Absolute Maximum Ratings

(Notes 1, 2)

LM97593

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

ADC Analog, Digital and IO Supply Voltages (VA, VD and VDR)

Difference between VA, VD, and V

Positive Core Supply Voltage (V

) −0.3V to 2.35V

D18

Voltage on Any Input or Output Pin (Not to exceed 4.2V)

Input Current at Any Pin other than Supply Pins (Note 3)

Package Input Current (Note 3) ±50 mA Max Junction Temp (TJ) +125°C

Thermal Resistance (θJA)

Package Dissipation at TA = 25°C (Note 4)

ESD Susceptibility (Note 5)

Human Body Model (1.5kΩ, 100pF)

Machine Model (0Ω, 200pF)

−0.3V to 4.2V

−0.3V to (VDR +0.3V)

≤ 100 mV

±5 mA

39°C/W

3.2W

2000 V

200 V

Operating Ratings (Notes 1, 2)

Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging.

(Note 6) Operating Temperature

Range ADC Analog, Digital and IO

−40°C ≤ TA ≤ +85°C

+3.0V to +3.6V Supply Voltages (VA, VD and VDR)

Digital Core Supply Voltage (VD18) +1.6V to +2.0V

Difference Between AGND, DGND, DRGND and D18GND ≤ 100 mV

Voltage on Any Input or Output Pin 0V to +3.3V

1.0V to 2.0V

Clock Duty Cycle 30% to 70 %

Reliability Information

Transistor Count 1.3 million

Charge Device Model 750 V Storage Temperature −65°C to +150°C

LM97593 Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V, VA = VD = VDR = +3.3V, V

= +1.8V, Internal V

D18

observed at the mixer output debug tap with NCO = 0Hz. Typical values are for TA = 25°C. Boldface limits apply for T

≤ T

. All other limits apply for TA = 25°C. (Notes 7, 8, 9)

MAX

Symbol Parameter Conditions

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 11 Bits (min)

INL Integral Non Linearity (Note 11) Ramp, End Point ±0.7

DNL Differential Non Linearity Ramp, End Point ±0.3

OFF

Offset Error −40°C to +85°C -4.1 LSB

REFERENCE AND ANALOG INPUT CHARACTERISTICS

V V

COM

REF

A B

Common Mode Input Voltage 1.5

Reference Output Voltage 1.5 V

VIN Input Capacitance (each pin to GND) (VIN= 1.5Vdc ±0.5V) (Note 12)

External Reference Voltage (Note 14)

Reference Input Resistance 1

DYNAMIC CONVERTER CHARACTERISTICS

FPBW Full Power Bandwidth 650 MHz

SNR Signal-to-Noise Ratio

= +1.0V, f

REF

= 65 MHz, VCM = V

CLK

, tR = tF = 1 ns, CL = 5 pF/pin. The ADC’s 11 most significant bits

COM

Typical

(Note 10)

Limits

2 LSB (max)

-2 LSB (min)

0.85 LSB (max)

-0.85 LSB (min)

1.0 V (min)

2.0 V (max)

CK LOW 8 pF

CK HIGH 7 pF

1.0

fIN = 20MHz, VIN = -3dBFS fIN = 249MHz, VIN = -3dBFS fIN = 249MHz, VIN = -9dBFS

66.2

63.7

63.9 62.2

0.8 V (min)

1.2 V (max)

≤ T

MIN

Units

(Limits)

MΩ

dBFS dBFS

dBFS (min)

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LM97593

Symbol Parameter Conditions

fIN = 20MHz, VIN = -3dBFS

SINAD Signal-to-Noise and Distortion