National Semiconductor LM5100A, LM5101A Technical data
March 2005
LM5100A/LM5101A
3.0 Amp High Voltage High Side and Low Side Driver
General Description
The LM5100A/LM5101A High Voltage Gate Drivers are designed to drive both the high side and the low side
N-Channel MOSFETs in a synchronous buck or a half bridge
configuration. The floating high-side driver is capable of
operating with supply voltages up to 100V. The outputs are
independently controlled with CMOS input thresholds
(LM5100A) or TTL input thresholds (LM5101A). An integrated high voltage diode is provided to charge the high side
gate drive bootstrap capacitor. A robust level shifter operates
at high speed while consuming low power and providing
clean level transitions from the control logic to the high side
gate driver. Under-voltage lockout is provided on both the
low side and the high side power rails. This device is available in the standard SOIC-8 pin and the LLP-10 pin packages.
n Bootstrap supply voltage range up to 118V DC
n Fast propagation times (25 ns typical)
n Drives 1000 pF load with 8 ns rise and fall times
n Excellent propagation delay matching (3 ns typical)
n Supply rail under-voltage lockouts
n Low power consumption
n Pin compatible with HIP2100/HIP2101 and
LM5100/LM5101
Typical Applications
n Current Fed push-pull converters
n Half and Full Bridge power converters
n Synchronous buck converters
n Two switch forward power converters
n Forward with Active Clamp converters
LM5100A/LM5101A 3.0 Amp High Voltage High Side and Low Side Driver
Features
n 3.0A Sink/Source current gate drive
n Drives both a high side and low side N-Channel
MOSFET
n Independent high and low driver logic inputs (TTL for
LM5101A or CMOS for LM5100A)
Simplified Block Diagram
Package
n SOIC-8
n LLP-10 (4 mmx4mm)
20124003
FIGURE 1.
© 2005 National Semiconductor Corporation DS201240 www.national.com
Connection Diagrams
LM5100A/LM5101A
20124001
20124002
FIGURE 2.
Ordering Information
Ordering Number Package Type NSC Package Drawing Supplied As
LM5100A/01A M SOIC-8 M08A Shipped in anti static rails
LM5100A/01A MX SOIC-8 M08A 2500 shipped as Tape & Reel
LM5100A/01A SD LLP-10 SDC10A 1000 shipped as Tape & Reel
LM5100A/01A SDX LLP-10 SDC10A 4500 shipped as Tape & Reel
Pin Description
Pin #
SO-8 LLP-10
11V
2 2 HB High side gate driver
3 3 HO High side gate driver output Connect to gate of high side MOSFET with a short low
4 4 HS High side MOSFET source
5 7 HI High side driver control input The LM5100A inputs have CMOS type thresholds. The
6 8 LI Low side driver control input The LM5100A inputs have CMOS type thresholds. The
79V
8 10 LO Low side gate driver output Connect to the gate of the low side MOSFET with a short low
Note: For LLP-10 package, it is recommended that the exposed pad on the bottom of the LM5100A / LM5101A be soldered to ground plane on the PC
board, and the ground plane should extend out from beneath the IC to help dissipate the heat. Pins 5 and 6 have no connection.
Name Description Application Information
DD
Positive gate drive supply Locally decouple to VSSusing low ESR/ESL capacitor located
as close to IC as possible.
Connect the positive terminal of the bootstrap capacitor to HB
bootstrap rail
and the negative terminal to HS. The Bootstrap capacitor
should be place as close to IC as possible.
inductance path.
Connect to bootstrap capacitor negative terminal and the
connection
source of the high side MOSFET.
LM5101A inputs have TTL type thresholds. Unused inputs
should be tied to ground and not left open.
LM5101A inputs have TTL type thresholds. Unused inputs
should be tied to ground and not left open.
SS
Ground return All signals are referenced to this ground.
inductance path.
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LM5100A/LM5101A
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
Storage Temperature Range −55˚C to +150˚C
ESD Rating HBM (Note 2) 2 KV
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
to V
V
DD
SS
V
to V
HB
HS
LI or HI Inputs −0.3V to V
LO Output −0.3V to V
HO Output V
V
to V
HS
SS
V
to V
HB
SS
HS
Junction Temperature +150˚C
−0.3V to +18V
−0.3V to +18V
+0.3V
DD
+0.3V
DD
−0.3V to VHB+0.3V
−1V to +100V
118V
Conditions
V
DD
HS −1V to 100V
HB V
HS Slew Rate
Junction Temperature −40˚C to +125˚C
+9V to +14V
+8V to VHS+14V
HS
<
50 V/ns
Electrical Characteristics
Specifications in standard typeface are for TJ= +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, V
DD=VHB
Symbol Parameter Conditions Min Typ Max Units
SUPPLY CURRENTS
I
DD
I
DDO
I
HB
I
HBO
I
HBS
I
HBSO
VDDQuiescent Current LI = HI = 0V (LM5100A) 0.1 0.2
VDDOperating Current f = 500 kHz 2.0 3 mA
Total HB Quiescent Current LI = HI = 0V 0.06 0.2 mA
Total HB Operating Current f = 500 kHz 1.6 3 mA
HB to VSSCurrent, Quiescent VHS=VHB= 100V 0.1 10 µA
HB to VSSCurrent, Operating f = 500 kHz 0.4 mA
INPUT PINS
V
IL
V
IL
V
IHYS
V
IHYS
R
I
Input Voltage Threshold (LM5100A) Rising Edge 4.5 5.4 6.3 V
Input Voltage Threshold (LM5101A) Rising Edge 1.3 1.8 2.3 V
Input Voltage Hysteresis (LM5101A) 50 mV
Input Voltage Hysteresis (LM5100A) 500 mV
Input Pulldown Resistance 100 200 400 kΩ
UNDER VOLTAGE PROTECTION
V
DDR
V
DDH
V
HBR
V
HBH
VDDRising Threshold 6.0 6.8 7.4 V
VDDThreshold Hysteresis 0.5 V
HB Rising Threshold 5.7 6.6 7.1 V
HB Threshold Hysteresis 0.4 V
BOOT STRAP DIODE
V
DL
V
DH
R
D
Low-Current Forward Voltage I
High-Current Forward Voltage I
Dynamic Resistance I
LO GATE DRIVER
V
V
I
I
OLL
OHL
OHL
OLL
Low-Level Output Voltage ILO= 100 mA 0.12 0.25 V
High-Level Output Voltage ILO= −100 mA,
Peak Pullup Current VLO= 0V 3.0 A
Peak Pulldown Current VLO= 12V 3.0 A
HO GATE DRIVER
V
V
I
I
OLH
OHH
OHH
OLH
Low-Level Output Voltage IHO= 100 mA 0.12 0.25 V
High-Level Output Voltage IHO= −100 mA
Peak Pullup Current VHO= 0V 3.0 A
Peak Pulldown Current VHO= 12V 3.0 A
= 12V, VSS=VHS= 0V, No Load on LO or HO .
LI = HI = 0V (LM5101A) 0.25 0.4
= 100 µA 0.52 0.85 V
VDD-HB
= 100 mA 0.80 1.0 V
VDD-HB
= 100 mA 1.0 1.65 Ω
VDD-HB
V
OHL=VDD–VLO
V
OHH=VHB–VHO
0.24 0.45 V
0.24 0.45 V
mA
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Electrical Characteristics (Continued)
Specifications in standard typeface are for TJ= +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, V
DD=VHB
= 12V, VSS=VHS= 0V, No Load on LO or HO .
Symbol Parameter Conditions Min Typ Max Units
HO GATE DRIVER
THERMAL RESISTANCE
LM5100A/LM5101A
θ
JA
Junction to Ambient SOIC-8 170
LLP-10 (Note 3) 40
Switching Characteristics
Specifications in standard typeface are for TJ= +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, V
DD=VHB
Symbol Parameter Conditions Min Typ Max Units
LM5100A
t
LPHL
Lower Turn-Off Propagation Delay (LI
Falling to LO Falling)
t
HPHL
Upper Turn-Off Propagation Delay (HI
Falling to HO Falling)
t
LPLH
Lower Turn-On Propagation Delay (LI
Rising to LO Rising)
t
HPLH
Upper Turn-On Propagation Delay (HI
Rising to HO Rising)
t
MON
Delay Matching: Lower Turn-On and
Upper Turn-Off
t
MOFF
Delay Matching: Lower Turn-Off and
Upper Turn-On
t
RC,tFC
t
R,tF
Either Output Rise/Fall Time CL= 1000 pF 8 ns
Either Output Fall Time
(3V to 9V)
Either Output Rise Time
(3V to 9V)
t
PW
Minimum Input Pulse Width that
Changes the Output
t
BS
Bootstrap Diode Turn-Off Time IF= 100 mA,
LM5101A
t
LPHL
Lower Turn-Off Propagation Delay (LI
Falling to LO Falling)
t
HPHL
Upper Turn-Off Propagation Delay (HI
Falling to HO Falling)
t
LPLH
Lower Turn-On Propagation Delay (LI
Rising to LO Rising)
t
HPLH
Upper Turn-On Propagation Delay (HI
Rising to HO Rising)
t
MON
Delay Matching: Lower Turn-On and
Upper Turn-Off
t
MOFF
Delay Matching: Lower Turn-Off and
Upper Turn-On
t
RC,tFC
t
R,tF
Either Output Rise/Fall Time CL= 1000 pF 8 ns
Either Output Fall Time
(3V to 9V)
Either Output Rise Time
(3V to 9V)
= 12V, VSS=VHS= 0V, No Load on LO or HO.
CL= 0.1 µF
CL= 0.1 µF
= 100 mA
I
R
CL= 0.1 µF
CL= 0.1 µF
20 45 ns
20 45 ns
20 45 ns
20 45 ns
1 10 ns
1 10 ns
0.26
0.43
50 ns
38 ns
22 56 ns
22 56 ns
26 56 ns
26 56 ns
4 10 ns
4 10 ns
0.26
0.43
˚C/W
µs
µs
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