National Semiconductor LM49350 Technical data

September 23, 2008

LM49350
High Performance Audio Codec Sub-System with a
Ground-Referenced Stereo Headphone Amplifier & an
Ultra Low EMI Class D Loudspeaker Amplifier with Dual
I2S/PCM Digital Audio Interfaces

SNR (Stereo DAC at 48kHz) 96dB (typ)

1.0 General Description

The LM49350 is a high performance audio subsystem that
supports both analog and digital audio functions. The
LM49350 includes a high quality stereo DAC, a high quality
stereo ADC, a stereo headphone amplifier that supports
ground referenced output cap-less operation, a dual mode
earpiece speaker amplifier, and a low EMI Class D loud­speaker amplifier. It is designed for demanding applications
in mobile phones and other portable devices.

The LM49350 features dual bi-directional I2S or PCM audio
interfaces for full range audio and an I2C compatible interface
for control. The stereo DAC path features an SNR of 96dB
with 24-bit 48 kHz input. The headphone amplifier delivers
69mW
than 1% distortion (THD+N) when A_VDD = 3.3V. The ear­piece speaker amplifier delivers 58mW
bridged-tied load with less than 1% distortion (THD+N) when
A_VDD = 3.3V. The loudspeaker amplifier delivers up to
495mW into an 8Ω load with less than 1% distortion when
LS_VDD = 3.3V and up to 1.2W when LS_VDD = 5.0V.

The LM49350 employs advanced techniques to reduce pow­er consumption, to reduce controller overhead, to speed de­velopment time, and to eliminate click and pop. Boomer audio
power amplifiers were designed specifically to provide high
quality output power with a minimal amount of external com­ponents. It is therefore ideally suited for mobile phone and
other low voltage applications where minimal power con­sumption, PCB area and cost are primary requirements.

(typ) to a 32Ω single-ended stereo load with less

RMS

(typ) to a 32Ω

RMS

2.0 Applications

Smart Phones

■

Mobile Phones and VOIP Phones

■

Portable GPS Navigator and Portable Gaming Devices

■

Portable DVD/CD/AAC/MP3/MP4 Players

■

Digital Cameras/Camcorders

■

3.0 Key Specifications

PHP at A_VDD = 3.3V, Stereo 32Ω, 1% THD 69mW/ch (typ)

■

PLS at LS_VDD = 5V, 8Ω, 1% THD 1.2W (typ)

■

PLS at LS_VDD = 4.2V, 8Ω, 1% THD 825mW (typ)

■

PLS at LS_VDD = 3.3V, 8Ω, 1% THD 495mW (typ)

■

PEP at A_VDD = 3.3V, 32Ω BTL, 1% THD 58mW (typ)

■

■ Supply Voltage Range
  D_V
  LS_V
  I/O_V

Boomer® is a registered trademark of National Semiconductor Corporation.

= 1.7V to 2.0V

DD

and A_VDD = 2.7V to 5.5V

DD

= 1.6V to 4.5V

DD

■

SNR (Stereo ADC at 48kHz) 94dB (typ)

■

Shutdown Current 2.3µA (typ)

■

PSRR at 217 Hz, A_VDD = 3.3V, (HP from

■

AUX)

4.0 Features

High performance 96dB SNR stereo DAC

■

High performance 94dB SNR stereo ADC

■

Up to 192kHz stereo audio playback

■

Up to 48kHz stereo recording

■

Dual bidirectional I2S or PCM compatible audio interfaces

■

Read/write I2C compatible control interface

■

Flexible digital mixer with sample rate conversion

■

Dual sigma-delta PLLs for operation from any clock at any

■

sample rate
Digital 3D stereo enhancement

■

Dual 5 band parametric equalizers

■

Cascadable DSP effects that allow 10 band parametric

■

equalization
ALC/Compressor/Limiter on both DAC and ADC paths

■

Ultra low EMI, Class D loudspeaker amplifier with spread

■

spectrum control
Ground referenced output cap-less headphone amplifier

■

operation
Earpiece speaker amplifier with reduced power

■

consumption mode for mono differential line out
applications

Stereo auxiliary inputs or mono differential input

■

Differential stereo microphone inputs with single-ended

■

option
Automatic level control for digital audio inputs, stereo

■

microphone inputs, and stereo auxiliary inputs
Flexible audio routing from input to output

■

16 Step volume control for microphones with 2dB steps

■

32 Step volume control for auxiliary inputs in 1.5dB steps

■

Micro-power shutdown mode

■

Available in the 3.5 x 3.5 mm 36 bump micro SMD package

■

97dB (typ)

LM49350 High Performance Audio Codec Sub-System with a Ground-Referenced Stereo

Headphone Amplifier & an Ultra Low EMI Class D Loudspeaker Amplifier with Dual I

Digital Audio Interfaces

2

S/PCM

© 2008 National Semiconductor Corporation 201941 www.national.com

5.0 LM49350 Overview

LM49350

FIGURE 1. LM49350 Block Diagram

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20194111

6.0 Typical Application

LM49350

20194102

FIGURE 2. Example Application in Multimedia Phone with a Dedicated Earpiece and Mono Loudspeaker

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LM49350

FIGURE 3. Example Application in Multimedia Phone Using Stereo Loudspeaker

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20194103

LM49350

20194104

FIGURE 4. Example Application in a Multimedia Phone Using a Dedicated RF Module for Voice Modern Functions

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LM49350

20194105

FIGURE 5. Example Application in a Portable Media Player with a Differential Stereo Line Input

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Table of Contents

1.0 General Description ......................................................................................................................... 1

2.0 Applications .................................................................................................................................... 1

3.0 Key Specifications ........................................................................................................................... 1

4.0 Features ........................................................................................................................................ 1

5.0 LM49350 Overview .......................................................................................................................... 2

6.0 Typical Application ........................................................................................................................... 3

7.0 Connection Diagrams ..................................................................................................................... 10

7.1 PIN TYPE DEFINITIONS .............................................................................................................. 11

8.0 Absolute Maximum Ratings ............................................................................................................ 12

9.0 Operating Ratings ......................................................................................................................... 12

10.0 Electrical Characteristics: A_VDD = LS_VDD = 3.3V; D_VDD = I/O_VDD = 1.8V (Notes 1, 2) The following

specifications apply for R

11.0 Timing Characteristics: DVDD = I/OVDD = 1.8V (Notes 1, 2) The following specifications apply for R

R

= 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C. ...................................................... 16

L(HP)

12.0 Typical Performance Characteristics .............................................................................................. 17

13.0 System Control ............................................................................................................................ 24

13.1 I2C SIGNALS ............................................................................................................................ 24

13.2 I2C DATA VALIDITY .................................................................................................................. 24

13.3 I2C START AND STOP CONDITIONS .......................................................................................... 24

13.4 TRANSFERRING DATA ............................................................................................................. 24

13.5 I2C TIMING PARAMETERS ....................................................................................................... 26

14.0 Device Register Map .................................................................................................................... 27

15.0 Basic PMC Setup Register ............................................................................................................ 32

16.0 PMC Clocks Register ................................................................................................................... 33

17.0 PMC Clock Divide Register ........................................................................................................... 33

18.0 LM49350 Clock Network .............................................................................................................. 34

19.0 PLL Setup Registers .................................................................................................................... 36

20.0 Analog Mixer Control Registers ..................................................................................................... 41

21.0 ADC Control Registers ................................................................................................................. 47

22.0 DAC Control Registers ................................................................................................................. 49

23.0 Digital Mixer Control Registers ...................................................................................................... 50

24.0 Audio Port Control Registers ......................................................................................................... 54

25.0 Digital Effects Engine ................................................................................................................... 59

26.0 DAC Effects Registers .................................................................................................................. 77

27.0 GPIO Registers ........................................................................................................................... 95

28.0 Schematic Diagram ...................................................................................................................... 97

29.0 Demonstration Board Layout ......................................................................................................... 98

30.0 Revision History ........................................................................................................................ 101

31.0 Physical Dimensions .................................................................................................................. 102

L(LS)

= 8Ω, R

= 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C. ......... 12

L(HP)

L(SP)

= 8Ω,

LM49350

List of Figures

FIGURE 1. LM49350 Block Diagram ............................................................................................................. 2

FIGURE 2. Example Application in Multimedia Phone with a Dedicated Earpiece and Mono Loudspeaker ......................... 3

FIGURE 3. Example Application in Multimedia Phone Using Stereo Loudspeaker ...................................................... 4

FIGURE 4. Example Application in a Multimedia Phone Using a Dedicated RF Module for Voice Modern Functions ............. 5

FIGURE 5. Example Application in a Portable Media Player with a Differential Stereo Line Input .................................... 6

List of Tables

TABLE 1. Device Register Map .................................................................................................................. 27

TABLE 2. PMC_SETUP (0x00h) ................................................................................................................. 32

TABLE 3. PMC_SETUP (0x01h) ................................................................................................................. 33

TABLE 4. PMC_SETUP (0x02h) (Default data value is 0x50h) ............................................................................. 33

TABLE 5. DAC Clock Requirements ............................................................................................................. 34

TABLE 6. ADC Clock Requirements ............................................................................................................. 34

TABLE 7. PLL_CLOCK_SOURCE (0x03h) .................................................................................................... 36

TABLE 8. PLL1_M (0x04h) ........................................................................................................................ 37

TABLE 9. PLL1_N (0x05h) ........................................................................................................................ 37

TABLE 10. PLL1_N_MOD (0x06h) .............................................................................................................. 38

TABLE 11. PLL1_P1 (0x07h) ..................................................................................................................... 38

TABLE 12. PLL1_P2 (0x08h) ..................................................................................................................... 38

TABLE 13. PLL2_M (0x09h) ...................................................................................................................... 39

TABLE 14. PLL2_N (0x0Ah) ...................................................................................................................... 39

TABLE 15. PLL2_N_MOD (0x0Bh) .............................................................................................................. 39

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TABLE 16. PLL2_P (0x0Ch) ...................................................................................................................... 40

TABLE 17. CLASS_D_OUTPUT (0x10h) ....................................................................................................... 41

TABLE 18. LEFT HEADPHONE_OUTPUT (0x11h) .......................................................................................... 41

LM49350

TABLE 19. RIGHT HEADPHONE_OUTPUT (0x12h) ........................................................................................ 42

TABLE 20. AUX_OUTPUT (0x13h) .............................................................................................................. 42

TABLE 21. OUTPUT_OPTIONS (0x14h) ....................................................................................................... 43

TABLE 22. ADC_INPUT (0x15h) ................................................................................................................. 43

TABLE 23. MIC_L_INPUT (0x16h) .............................................................................................................. 43

TABLE 24. MIC_R_INPUT (0x17h) .............................................................................................................. 44

TABLE 25. AUX_L_INPUT (0x18h) .............................................................................................................. 45

TABLE 26. AUX_R_INPUT (0x19h) ............................................................................................................. 46

TABLE 27. ADC Basic (0x20h) ................................................................................................................... 47

TABLE 28. ADC_CLK_DIV (0x21h) ............................................................................................................. 47

TABLE 29. ADC TRIM (0x22h) ................................................................................................................... 48

TABLE 30. DAC Basic (0x30h) ................................................................................................................... 49

TABLE 31. DAC_CLK_DIV (0x31h) ............................................................................................................. 49

TABLE 32. Input Levels 1 (0x40h) ............................................................................................................... 51

TABLE 33. Input Levels 2 (0x41h) ............................................................................................................... 51

TABLE 34. Audio Port 1 Input (0x42h) .......................................................................................................... 52

TABLE 35. Audio Port 2 Input (0x43h) .......................................................................................................... 52

TABLE 36. DAC Input Select (0x44h) ........................................................................................................... 53

TABLE 37. Decimator Input Select (0x45h) .................................................................................................... 53

TABLE 38. BASIC_SETUP (0x50h/0x60h) ..................................................................................................... 55

TABLE 39. CLK_GEN_1 (0x51h/0x61h) ........................................................................................................ 55

TABLE 40. CLK_GEN_1 (0x52h/62h) ........................................................................................................... 56

TABLE 41. CLK_GEN_1 (0x53h/63h) ........................................................................................................... 56

TABLE 42. DATA_WIDTHS (0x54h/64h) ....................................................................................................... 57

TABLE 43. TX_MODE (0x55h/x65h) ............................................................................................................ 58

TABLE 44. ADC EFFECTS (0x70h) ............................................................................................................. 59

TABLE 45. DAC EFFECTS (0x71h) ............................................................................................................. 59

TABLE 46. HPF MODE (0x80h) .................................................................................................................. 60

TABLE 47. ADC_ALC_1 (0x81h) ................................................................................................................. 61

TABLE 48. ADC_ALC_2 (0x82h) ................................................................................................................. 62

TABLE 49. ADC_ALC_3 (0x83h) ................................................................................................................. 63

TABLE 50. ADC_ALC_4 (0x84h) ................................................................................................................. 64

TABLE 51. ADC_ALC_5 (0x85h) ................................................................................................................. 65

TABLE 52. ADC_ALC_6 (0x86h) ................................................................................................................. 66

TABLE 53. ADC_ALC_7 (0x87h) ................................................................................................................. 66

TABLE 54. ADC_ALC_8 (0x88h) ................................................................................................................. 66

TABLE 55. ADC_L_LEVEL (0x89h) ............................................................................................................. 67

TABLE 56. ADC_R_LEVEL (0x8Ah) ............................................................................................................. 68

TABLE 57. EQ_BAND_1 (0x8Bh) ................................................................................................................ 69

TABLE 58. EQ_BAND_2 (0x8Ch) ................................................................................................................ 70

TABLE 59. EQ_BAND_3 (0x8Dh) ................................................................................................................ 71

TABLE 60. EQ_BAND_4 (0x8Eh) ................................................................................................................ 72

TABLE 61. EQ_BAND_5 (0x8Fh) ................................................................................................................ 73

TABLE 62. SOFTCLIP1 (0x90h) ................................................................................................................. 74

TABLE 63. SOFTCLIP2 (0x91h) ................................................................................................................. 75

TABLE 64. SOFTCLIP3 (0x92h) ................................................................................................................. 76

TABLE 65. DAC_ALC_1 (0xA0h) ................................................................................................................ 76

TABLE 66. DAC_ALC_2 (0xA1h) ................................................................................................................ 78

TABLE 67. DAC_ALC_3 (0xA2h) ................................................................................................................ 79

TABLE 68. DAC_ALC_4 (0xA3h) ................................................................................................................ 80

TABLE 69. DAC_ALC_5 (0xA4h) ................................................................................................................ 81

TABLE 70. DAC_ALC_6 (0xA5h) ................................................................................................................ 83

TABLE 71. DAC_ALC_7 (0xA6h) ................................................................................................................ 83

TABLE 72. DAC_ALC_8 (0xA7h) ................................................................................................................ 83

TABLE 73. DAC_L_LEVEL (0xA8h) ............................................................................................................. 84

TABLE 74. DAC_R_LEVEL (0xA9h) ............................................................................................................. 85

TABLE 75. DAC_3D (0xAAh) ..................................................................................................................... 86

TABLE 76. EQ_BAND_1 (0xABh) ............................................................................................................... 87

TABLE 77. EQ_BAND_2 (0xACh) ............................................................................................................... 88

TABLE 78. EQ_BAND_3 (0xADh) ............................................................................................................... 89

TABLE 79. EQ_BAND_4 (0xAEh) ............................................................................................................... 90

TABLE 80. EQ_BAND_5 (0xAFh) ................................................................................................................ 91

TABLE 81. SOFTCLIP1 (0xB0h) ................................................................................................................. 92

TABLE 82. SOFTCLIP2 (0xB1h) ................................................................................................................. 93

TABLE 83. SOFTCLIP3 (0xB2h) ................................................................................................................. 94

TABLE 84. GPIO (0xE0h) ......................................................................................................................... 94

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TABLE 85. Spread Spectrum (0xF1h) ........................................................................................................... 95

TABLE 86. ADC Compensation Filter C0 LSBs (0xF8h) ..................................................................................... 95

TABLE 87. ADC Compensation Filter C0 MSBs (0xF9h) .................................................................................... 95

TABLE 88. ADC Compensation Filter C1 LSBs (0xFAh) ..................................................................................... 96

TABLE 89. ADC Compensation Filter C1 MSBs (0xFBh) .................................................................................... 96

TABLE 90. ADC Compensation Filter C2 LSBs (0xFCh) .................................................................................... 96

TABLE 91. ADC Compensation Filter C2 MSBs (0xFDh) .................................................................................... 96

TABLE 92. AUX_LINEOUT (0xFE) .............................................................................................................. 96

LM49350

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7.0 Connection Diagrams

LM49350

See NS Package Number RLA36TTA

36 Bump micro SMD

Top View (Bump Side Down)

Order Number LM49350RL

20194101

36 Bump micro SMD Marking

Top View

XY — Date Code

TT — Die Traceability

G — Boomer

J8 — LM49350RL

Ordering Information

Order Number Package Package DWG # Transport Media MSL Level Green Status

LM49350RL

LM49350RLX

36 Bump micro

SMDxt

36 Bump micro

SMDxt

RLA36TTA 250 units on tape and reel 1

RLA36TTA 3000 units on tape and reel 1

201941q7

RoHS and

no Sb/Br

RoHS and

no Sb/Br

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Pin Descriptions

Pin Pin Name Type Direction Description

A1 HPR Analog Output Headphone right output

A2 A_V

DD

A3 AGND Supply Input Headphone and mixer ground

A4 VREF_FLT Analog Input/Output Filter point for the microphone power supply and internal references

A5 GPIO Digital Input/Output General purpose input or output

A6 SDA Digital Input/Output I2C interface data line

B1 HPL Analog Output Headphone left output

B2 AUX_R Analog Input Right analog input

B3 AUX_L Analog Input Left analog input

B4 PORT2_SYNC Digital Input/Output Audio Port 2 SYNC Signal (can be master or slave)

B5 PORT2_SDI Digital Input Audio Port 2 serial data input

B6 SCL Digital Input I2C interface clock line

C1 HP_V

SS

C2 AUX_OUT+ Analog Output Auxiliary positive output

C3 AUX_OUT- Analog Output Auxiliary negative output

C4 PORT2_SDO Digital Output Audio port 2 serial data out

C5 PORT2_CLK Digital Input/Output Audio port 2 clock signal (can be master or slave)

C6 MCLK Digital Input Input clock from 0.5MHz to 50 MHz

D1 CP- Analog Input/Output Charge pump flying capacitor negative input

D2 CP+ Analog Input/Output Charge pump flying capacitor positive input

D3 MIC_BIAS Analog Output Microphone ultra clean supply (2.2V)

D4 PORT1_SYNC Digital Input/Output Audio Port 1 sync signal (can be master or slave)

D5 PORT1_SDO Digital Output Audio Port 1 serial data output

D6 DGND Supply Input Digital ground

E1 LSGND Supply Input Loudspeaker ground

E2 LS_V

DD

E3 RIGHT_MIC- Analog Input Right microphone negative input

E4 LEFT_MIC- Analog Output Left microphone negative input

E5 PORT1_SDI Digital Input Audio Port 1 serial data input

E6 D_V

DD

F1 LS + Analog Output Loudspeaker positive output

F2 LS - Analog Output Loudspeaker negative output

F3 RIGHT_MIC + Analog Input Right microphone positive input

F4 LEFT_MIC + Analog Input Left microphone positive input

F5 PORT1_CLK Digital Input/Output Audio Port 1 clock signal (can be master or slave)

F6 I/O_V

DD

7.1 PIN TYPE DEFINITIONS Analog Input —

Analog Output —

Analog Input/Output —

Supply Input Headphone and mixer power supply input

Analog Output Negative power supply pin for the headphone amplifier

Supply Input Loudspeaker power supply input

Supply Input Digital power supply input

Supply Input Digital interface power supply input

vice. Passive components can be

A pin that is used by the analog
and is never driven by the device.
Supplies are part of this classifica­tion.

A pin that is driven by the device
and should not be driven by exter­nal sources.

A pin that is typically used for fil­tering a DC signal within the de-

Digital Input —

Digital Output —

Digital Input/Output —

connected to these pins.
A pin that is used by the digital but

is never driven by the device.
A pin that is driven by the device

and should not be driven by an­other device to avoid contention.

A pin that is either open drain
(SDA) or a bidirectional CMOS in/
out. In the latter case the direction
is selected by a control register
within the LM49350.

LM49350

11 www.national.com

8.0 Absolute Maximum Ratings (Notes

1, 2)

LM49350

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Analog Supply Voltage

(A_VDD and LS_VDD)

Digital Supply Voltage

D_V

DD

I/O Supply Voltage

I/O_V

DD

Storage Temperature −65°C to +150°C
Power Dissipation (Note ) Internally Limited

6.0V

2.2V

5.5V

Junction Temperature 150°C
Thermal Resistance

 θJA – RLA36 (soldered down

to PCB with 2in2 1oz. copper

plane) 60°C/W
Soldering Information
See Applications Note AN-1112.

9.0 Operating Ratings

Temperature Range −40°C to +85°C
Supply Voltage

A_VDD and LS_V

D_V

DD

I/O_V

DD

DD

ESD Ratings

Human Body Model (Note )
Machine Model (Note )

2000V

200V

10.0 Electrical Characteristics: A_VDD = LS_VDD = 3.3V; D_VDD = I/O_VDD = 1.8V

(Notes 1, 2) The following specifications apply for R

for TA = 25°C.

Symbol Parameter Conditions

DC CHARACTERISTICS (Digital current combines D_VDD and I/O_VDD. Analog current combines A_VDD and LS_VDD)

DI

DI

SD

ST

Digital Shutdown Current

Digital Standby Current

Shutdown Mode,
f

f

f

Digital Active Current (MP3 Mode)

Stereo DAC On, OSR
PLL Off, HP On

Digital Active Current (FM Mode) f

Analog Audio modes

DI

DD

Digital Active Current (FM Record
Mode)

f
Stereo ADC On, OSR
PLL Off, Stereo Analog Inputs On

Digital Active Current (CODEC
Mode)-

f
Mono ADC On, Stereo DAC On,
OSR = 128, PLL Off, MIC On

AI

SD

AI

ST

Analog Shutdown Current Shutdown Mode 0.3 5

Analog Standby Quiescent Current Reference Voltages On only 0.85 1.5 mA (max)

f

Analog Supply Current (MP3 Mode)

Stereo DAC On, OSR
PLL Off, HP On

Analog Supply Current (FM Mode) Stereo Analog Inputs On, HP On 5.3 7 mA (max)

AI

DD

PLLI

HPI

LSI

DD

DD

DD

Analog Supply Current (FM Record
Mode)

Analog Supply Current (CODEC
Mode)

PLL Total Active Current

Headphone Quiescent Current Stereo HP On only 3.5 mA

Loudspeaker Quiescent Current LS On only 2.9 mA

f
Stereo ADC On, OSR
PLL Off, Stereo Analog Inputs On

f
Mono ADC On, Stereo DAC On,
OSR = 128, PLL Off, MIC On

f
f

= 8Ω, R

L(LS)

= 13MHz, PLL Off

MCLK

= 12.288MHz, PMC On only

MCLK

= 11.2896MHz, fS = 44.1kHz,

MCLK

= 13MHz

MCLK

= 12.288MHz, fS = 48kHz,

MCLK

= 11.2896MHz, fS = 44.1kHz,

MCLK

= 11.2896MHz, fS = 44.1kHz,

MCLK

= 12.288MHz, fS = 48kHz,

MCLK

= 11.2896MHz, fS = 44.1kHz,

MCLK

= 13MHz,

MCLK

= 12MHz, PLL On only

PLLOUT

= 32Ω, f = 1kHz, unless otherwise specified. Limits apply

L(HP)

DAC

ADC

DAC

ADC

= 128,

= 128,

= 128,

= 128,

LM49350

Typical

(Note 6)

Limit

(Note 7)

2 15 µA (max)

0.25 1 mA (max)

0.9 2 mA (max)

0.2 0.5 mA (max)

1.5 2 mA (max)

2.7 3.8 mA (max)

7.8 10 mA (max)

9.8 12 mA (max)

13 15 mA (max)

2.9 5.5 mA (max)

2.7V to 5.5V

1.7V to 2.0V

1.6V to 4.5V

Units

(Limits)

μA (max)

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LM49350

Symbol Parameter Conditions

MICI

DD

ADCI

DD

DACI

DD

AUXINI

AUXOUTI

Microphone Quiescent Current mono MIC + MIC Bias On 0.5 mA

ADC Total Active Current

DAC Total Active Current

Auxiliary Input Amplifier Quiescent

DD

Current

Auxiliary Output Amplifier Quiescent

DD

Current

fS = 48kHz, Stereo

fS = 48kHz, Stereo

Stereo Auxiliary Inputs enabled 0.7 mA

AUX_LINE_OUT enabled 0.5 mA

Earpiece mode enabled 1.0 mA

LOUDSPEAKER AMPLIFIER

LS

EFF

THD+N Total Harmonic Distortion + Noise

Loudspeaker Efficiency

PO = 400mW, RL = 8Ω

PO = 400mW, f = 1kHz,

RL = 8Ω, Mono Input Signal

RL = 8Ω, f = 1kHz, THD+N = 1%,

P

O

Output Power

Mono Input Signal

RL = 4Ω, f = 1kHz, THD+N = 1%,
Mono Input Signal

V

= 200mV

PSRR Power Supply Rejection Ration

SNR Signal-to-Noise Ratio

RIPPLE

f

= 217Hz

RIPPLE

Mono Input Terminated

V

= 1.0μF

REF

Reference = V
Gain = 0dB, A-weighted

P-P

OUT

Mono Input Terminated

e

OS

V

OS

T

WU

Output Noise

Offset Voltage Gain = 0dB, form Mono Input 10 50 mV (max)

Turn-On Time PMC Clock = 300kHz 28 ms

Gain = 0dB, A-weighted,
Mono Input Terminated

HEADPHONE AMPLIFIERS

PO = 7.5mW, f = 1kHz,

THD+N Total Harmonic Distortion + Noise

RL = 32Ω
Stereo Analog Input Signal

P

O

Headphone Output Power

PSRR Power Supply Rejection Ratio

RL = 32Ω, f = 1kHz, THD+N = 1%,
Stereo Analog Input Signal

V

= 200mV

RIPPLE

P-P

Stereo Analog Inputs Terminated,

V

= 1.0μF, Mono Differential Input

REF

Mode

Reference = V

OUT

Gain = 0dB, A-weighted

SNR Signal-to-Noise Ratio

Stereo Inputs Terminated

Reference = V

OUT

0dB,
A-weighted, I2S Input = Digital Zero

Gain = 0dB, A-weighted,

e

OS

Output Noise

Stereo Inputs Terminated

Gain = 0dB, A-weighted,
I2S Input = Digital Zero

PO = 60mW, f = 1kHz,

X

TALK

Crosstalk

RL = 32Ω
Stereo Analog Input Signal

(1% THD+N )

, f

RIPPLE

= 217Hz

(1% THD+N )

(0dBFS ) Gain =

LM49350

Typical

(Note 6)

Limit

(Note 7)

Units

(Limits)

9 mA

5.5 mA

83 %

0.07 %

495 400 mW (min)

800 mW

73 55 dB (min)

95 85 dB (min)

35 µV

0.025 0.1 % (max)

69 60 mW (min)

97 75 dB (min)

106 98 dB (min)

96 90 dB (min)

8 µV

16 µV

71 dB

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Symbol Parameter Conditions

LM49350

ΔA

CH-CH

V

OS

T

WU

AUXILIARY OUTPUTS

THD+N Total Harmonic Distortion + Noise

P

OUT

PSRR Power Supply Rejection Ratio

SNR Signal-to-Noise Ratio

∈

OUT

V

OS

T

WU

STEREO ADC

THD+N

PB

ADC

R

ADC

SNR

ADC

ADC

LEVEL

STEREO DAC

THD+N

DAC

LEVEL

Channel-to-Channel Gain Matching

AUX Gain = 0dB

Output Offset Voltage

From Differential Mono Input

DAC Gain = 0dB, From DAC Input
f

= 12.288MHz, PLL off

MCLK

Turn-On Time PMC Clock = 300kHz 28 ms

AUX_LINE_OUT

RL = 5kΩ, V

Earpiece mode, f = 1kHz

RL = 32Ω BTL, P

Output Power

Earpiece mode, f = 1kHz

RL = 32Ω BTL, THD+N = 1%

V

= 200mV

RIPPLE

Mono Input terminated, C
AUX_LINE_OUT

V

= 200mV

RIPPLE

Mono Input terminated, C
Earpiece mode

Gain = 0dB, V
A-weighted, Mono Input Terminated

Output Noise

Gain = 0dB, V
A-weighted, Mono Input Terminated

Gain = 0dB, From Mono Input

Output Offset Voltage

AUX_LINE_OUT

Gain = 0dB, From Mono Input
Earpiece mode

Turn-On Time PMC Clock = 300kHz 28 ms

ADC Total Harmonic Distortion +

ADC

Noise

Differential Line Input
VIN = 200mV
Gain = 0dB

HPF On, fS = 48kHz

ADC Passband

Lower -3dB Point

HPF On, Upper -3dB Point

ADC Ripple ADC Compensated 0.1 dB

Reference = V
6dB,
A-weighted From MIC, fS = 8kHz

ADC Signal-to-Noise Ratio

Reference = V
0dB,
A-weighted From Stereo Input, fS =
48kHz

ADC Full Scale Input Level

DAC Total Harmonic Distortion +

DAC

Noise

I2S Input
VIN = 500mFFS
Gain = 0dB

DAC Full Scale Output Level

= 1V

OUT

RMS

= 20mW

OUT

, f

P-P

, f

P-P

= V

REF

= V

REF

, f = 1kHz

RMS

(0dBFS ) Gain =

OUT

(0dBFS ) Gain =

OUT

, f = 1kHz

RMS

= 217Hz

RIPPLE

= 1μF

REF

= 217Hz

RIPPLE

= 1μF

REF

(1%THD+N)

OUT

(1%THD+N)

OUT

LM49350

Typical

(Note 6)

Limit

(Note 7)

Units

(Limits)

0.03 dB

0.5 6 mV (max)

1 6 mV (max)

0.004 %

0.08 %

58 45 mW (min)

100 dB

94 62 dB (min)

100 dB

13

7 mV

3 15 mV (max)

0.03 %

300 Hz

0.41*f

S

kHz

90 dB

94 dB

1

V

0.05 %

1

V

μV

RMS

RMS

www.national.com 14

LM49350

Symbol Parameter Conditions

R

DAC

PB

SNR

DAC

DAC

DAC Ripple

DAC Passband Upper –3dB Point 0.45*f

DAC Signal-to-Noise Ratio fS = 48kHz, A-weighted

LM49350

Typical

(Note 6)

Limit

(Note 7)

0.1 dB

S

kHz

96 dB

Units

(Limits)

MIC BIAS

V

BIAS

Microphone Bias Voltage MIC input selected 2.2 V

VOLUME CONTROL

VCR

AUX

VCR

DAC

VCR

ADC

VCR

MIC

SS

AUX

SS

DAC

SS

ADC

SS

MIC

SV

AUX

SV

MIC

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.

Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation is P

Note 4: Human body model, applicable std. JESD22-A114C.

Note 5: Machine model, applicable std. JESD22-A115-A.

Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product

characterization and are not guaranteed.

Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.

Stereo Input Volume Control Range

DAC Volume Control Range

ADC Volume Control Range

MIC Volume Control Range

AUX Volume Control Stepsize 1.5 dB

DAC Volume Control Stepsize 1.5 dB

DAC Volume Control Stepsize 1.5 dB

MIC Volume Control Stepsize 2 dB

AUX Volume Setting Variation ±1 dB (max)

MIC Volume Setting Variation ±1 dB (max)

= (T

DMAX

- TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower.

JMAX

Minimum Gain –46.5 dB

Maximum Gain 12 dB

Minimum Gain –76.5 dB

Maximum Gain 18 dB

Minimum Gain –76.5 dB

Maximum Gain 18 dB

Minimum Gain 6 dB

Maximum Gain 36 dB

, θJA, and the ambient temperature, TA. The maximum

JMAX

15 www.national.com

11.0 Timing Characteristics: DVDD = I/OVDD = 1.8V (Notes 1, 2) The following specifications

apply for R

LM49350

Symbol Parameter Conditions

PLL

f

IN

DIGITAL AUDIO INTERFACE TIMING

t

BCLKR

t

BCLKCF

t

BCLKDS

t

DL

t

DST

t

DHT

CONTROL INTERFACE TIMING

1

2 Clock Low Time

3 Clock High Time 600 ns (min)

4 Setup Time for a Repeated START

5 Data Hold Time

6 Data Setup Time 100 ns (min)

7 Rise Time of SDA and SCL

8 Fall Time SDA and SCL

9 Setup Time for STOP Condition 600 ns (min)

10

C

B

L(SP)

= 8Ω, R

= 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.

L(HP)

LM49350

PLL Input Frequency Range

BCK rise time

BCK fall time

BCK duty cycle

WS Propagation Delay from BCK
falling edge

DATA Setup Time to BCK Rising Edge

DATA Hold Time from BCK Rising
Edge

Typical

(Note 6)

Minimum MCLK Frequency 0.5 MHz (min)

Maximum MCLK Frequency 50 MHz (max)

3 ns (max)

50 %

10 ns (max)

10 ns (min)

10 ns (min)

Limit

(Note 7)

3 ns (max)

SCL Frequency 400 kHz (max)

Hold Time (repeated START
Condition)

0.6

1.3

Condition

Bus Free Time Between a STOP and
START Condition

Bus Capacitance

600 ns (min)

Output

Input

1.3

300
900

0

900

20+0.1C

300

15+0.1C

300

B

B

10

200

Units

(Limits)

μs (min)

μs (min)

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

ns (max)

μs (min)

pF (min)
pF(max)

www.national.com 16

12.0 Typical Performance Characteristics

LM49350

DAC Frequency Response

fS = 48kHz, OSR = 128

20194139

Stereo Audio ADC Frequency Response

fS = 48kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB

DAC Frequency Response

fS = 8kHz, OSR = 128

20194140

Stereo Audio ADC Frequency Response

fS = 8kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB

20194141

Stereo Audio ADC HPF Frequency Response

fS = 48kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB

(Top-No HPF, Upper-HPF_Mode = '101',

Lower-HPF_Mode = '110)'

Bottom-HPF_Mode = '111'

20194143

20194142

Mono Voice ADC Frequency Response

fS = 48kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB

20194144

17 www.national.com

LM49350

Mono Voice ADC Frequency Response

fS = 8kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB

20194145

Mono Voice ADC HPF Frequency Response

fS = 48kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB

(Top-No HPF)

(From Left to Right:

HPF_Mode = '000', '001', '010', '011', '100')

20194146

Mono Voice ADC HPF Frequency Response

fS = 8kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB

(Top-No HPF)

(From Left to Right:

HPF_Mode = '000', '001', '010', '011', '100')

20194147

ADC Output THD+N vs Frequency

Differential MIC Input, MIC Gain = 6dB

VIN = 100mV

, fS = 48kHz

RMS

ADC Output THD+N vs Frequency

Differential Line Input, Aux Gain = 0dB

VIN = 200mV

ADC Output THD+N vs V

Differential Line Input, Aux Gain = 0dB

, fS = 48kHz

RMS

20194155

IN

VIN = 1kHz, fS = 48kHz

20194156

www.national.com 18

20194148

LM49350

ADC Output THD+N vs V

Differential MIC Input, MIC Gain = 6dB

IN

VIN = 1kHz, fS = 48kHz

20194149

Loudspeaker THD+N vs Frequency

Differential Aux Input, Aux Gain = 0dB

VDD = 5V, P

= 400mW, RL = 8Ω

OUT

Loudspeaker THD+N vs Frequency

Differential Aux Input, Aux Gain = 0dB

VDD = 3.3V, P

= 400mW, RL = 8Ω

OUT

20194159

Loudspeaker THD+N vs Frequency

Differential Aux Input, Aux Gain = 0dB
LS_VDD = 3.3V, P

= 500mW, RL = 4Ω

OUT

20194161

Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB

VDD = 3.3V, VIN = 1kHz, RL = 8Ω

20194165

20194181

Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB

VDD = 4.2V, VIN = 1kHz, RL = 8Ω

20194166

19 www.national.com

LM49350

Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB

VDD = 5V, VIN = 1kHz, RL = 8Ω

Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB

LS_VDD = 3.3V, RL = 4Ω, f = 1kHz

20194167

Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB

LS_VDD = 4.2V, RL = 4Ω, f = 1kHz

20194183

Loudspeaker PSRR vs Frequency

LS_VDD = 3.3V, Aux Gain = 0dB

Differential Aux Input to Ground

V

= 200mV

RIPPLE

PP

20194182

Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB

LS_VDD = 5V, RL = 4Ω, f = 1kHz

20194184

Loudspeaker PSRR vs Frequency

LS_VDD = 4.2V, Aux Gain = 0dB

Differential Aux Input to Ground

V

= 200mV

RIPPLE

PP

20194151

www.national.com 20

20194152

LM49350

Loudspeaker PSRR vs Frequency

LS_VDD = 5V, Aux Gain = 0dB

Differential Aux Input to Ground

V

= 200mV

RIPPLE

PP

Headphone THD+N vs Frequency

Stereo Aux Input, Aux Gain = 0dB
VDD = 5V, P

= 7.5mW, RL = 32Ω

OUT

20194153

Headphone THD+N vs Frequency

Stereo Aux Input, Aux Gain = 0dB

VDD = 3.3V, P

= 7.5mW, RL = 32Ω

OUT

20194157

Headphone THD+N vs Frequency

Differential Aux Input, Aux Gain = 0dB
A_VDD = 3.3V, P

= 7.5mW, RL = 16Ω

OUT

20194158

Headphone THD+N vs Output Power

Stereo Aux Input, Aux Gain = 0dB

VDD = 3.3V, VIN = 1kHz, RL = 32Ω

20194173

20194179

Headphone THD+N vs Output Power

Stereo Aux Input, Aux Gain = 0dB

VDD = 5V, VIN = 1kHz, RL = 32Ω

20194174

21 www.national.com

LM49350

Headphone THD+N vs Output Power

A_VDD = 3.3V, Stereo Aux Input, Aux Gain = 0dB

RL = 16Ω, f = 1kHz

Differential Aux Input to Ground, Aux Gain = 0dB

Headphone PSRR vs Frequency

V

= 200mV

RIPPLE

PP

20194180

Headphone Crosstalk vs Frequency

Stereo Aux Inputs, Aux Gain = 0dB, RL = 32Ω

20194169

Earpiece THD+N vs Output Power

Differential Aux Input, Aux Gain = 0dB

A_VDD45 = 3.3V, RL = 32Ω, f = 1kHz

20194175

Earpiece THD+N vs Frequency

Differential Aux Input, Aux Gain = 0dB

A_VDD = 3.3V, P

= 20mW, RL = 32Ω

OUT

20194176

Earpiece PSRR vs Frequency

Differential Aux Input to Ground, Aux Gain = 0dB

V

= 200mV

RIPPLE

PP

20194177

www.national.com 22

20194178

LM49350

AUXOUT THD+N vs Frequency

Differential Aux Input, Aux Gain = 0dB

VDD = 5V, V

OUT

= 1V

, RL = 5kΩ

RMS

20194162

AUXOUT PSRR vs Frequency

Differential Aux Input to Ground, Aux Gain = 0dB

V

= 200mV

RIPPLE

PP

AUXOUT THD+N vs Output Voltage

Differential Aux Input, Aux Gain = 0dB

V

= 1kHz, RL = 5kΩ

IN

20194168

20194154

23 www.national.com

13.0 System Control

Method 1. I2C Compatible Interface

LM49350

13.1 I2C SIGNALS

In I2C mode the LM49350 pin SCL is used for the I2C clock
SCL and the pin SDA is used for the I2C data signal SDA. Both

these signals need a pull-up resistor according to I2C speci­fication. The I2C slave address for LM49350 is 00110102.

13.2 I2C DATA VALIDITY

The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when SCL is LOW.

FIGURE 6: I2C Signals: Data Validity

13.3 I2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates

FIGURE 7: I2C Start and Stop Conditions

13.4 TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac­knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an ac­knowledge after each byte has been received.

20194123

START and STOP bits. The I2C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I2C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.

20194124

After the START condition, the I2C master sends a chip ad­dress. This address is seven bits long followed by an eight bit
which is a data direction bit (R/W). The LM49350 address is

00110102. For the eighth bit, a “0” indicates a WRITE and a

“1” indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.

FIGURE 8: I2C Chip Address

Register changes take effect at the SCL rising edge during
the last ACK from slave.

www.national.com 24

20194125

LM49350

w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start

20194126

FIGURE 9: Example I2C Write Cycle

25 www.national.com

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle
waveform.

LM49350

FIGURE 10: Example I2C Read Cycle

FIGUREW 11: I2C Timing Diagram

20194128

20194127

13.5 I2C TIMING PARAMETERS

Symbol Parameter Limit Units

Min Max

1 Hold Time (repeated) START Condition 0.6 µs

2 Clock Low Time 1.3 µs

3 Clock High Time 600 ns

4 Setup Time for a Repeated START Condition 600 ns

5 Data Hold Time (Output direction, delay generated by LM49350) 300 900 ns

5 Data Hold Time (Input direction, delay generated by the Master) 0 900 ns

6 Data Setup Time 100 ns

7 Rise Time of SDA and SCL 20+0.1C

8 Fall Time of SDA and SCL 15+0.1C

b

b

300 ns

300 ns

9 Set-up Time for STOP condition 600 ns

10 Bus Free Time between a STOP and a START Condition 1.3 µs

C

NOTE: Data guaranteed by design

Capacitive Load for Each Bus Line 10 200 pF

b

www.national.com 26

14.0 Device Register Map

TABLE 1. Device Register Map

Address Register 7 6 5 4 3 2 1 0

BASIC SETUP

0x00h PMC CHIP PORT2 PORT1 MCLK OSC PLL2 PLL1 CHIP

SETUP ACTIVE CLK OVR CLK OVR OVR ENB ENB ENB ENABLE

0x01h PMC

CLOCKS

0x02h PMC

CLK_DIV

0x03h PLL2_CLK_SEL PLL1_CLK_SEL

0x04h PLL1 M PLL1 M

0x05h PLL1 N PLL1 N

0x06h PLL1

N_MOD

0x07h PLL1 P1 PLL1 P1 [7:0]

0x08h PLL1 P2 PLL1 P2[7:0]

0x09h PLL2 M PLL2 M

0x0Ah PLL2 N PLL2 N

0x0Bh PLL2

N_MOD

0x0Ch PLL2 P PLL2 P[7:0]

0x10h CLASSD AUXR_LS AUXL_LS MICR_LS MICL_LS DACR_LS DACL_LS

0x11h HEAD

PHONESL

0x12h HEAD AUXR_HPRAUXL_HPRMICR_HPRMICL_HPR DACR_HPRDACL_HP

PHONESR

0x13h AUX_OUT AUXR_AX AUXL_AX MICR_AX MICL_AX DACR_AX DACL_AX

0x14h OUTPUT

OPTIONS

0x15h ADC AUXR_ADCRAUXL_ADCLMICR_ADCRMICL_ADCLDACR_ADCRDACL_AD

0x16h MICL_LVL MUTE SE/DIFF MIC_L_LEVEL

0x17h MICR_LVL MUTE SE/DIFF MIC_R_LEVEL

0x18h AUXL_LVL FROM

0x19h AUXR_LVLDIFF_MODEFROM

0x20h ADC

BASIC

0x21h ADC

CLOCK

0x22h ADC_DSP ADC_TRI

0x30h DAC_BASICDSPONLY DAC_CLK_SEL MUTE_R MUTE_L DAC_OSR

PMC_CLK_SEL

PMC_CLK_DIV(R)

PLLs

PLL2 P2[8] PLL1 P1[8] PLL1 N_MOD

PLL2 P[8] PLL2 N_MOD

ANALOG MIXER

AUXR_HPLAUXL_HPLMICR_HPL MICL_HPL DACR_HPLDACL_HP

LSSHORT

IGNORE

DSPONLY ADC_CLK_SEL MUTE_R MUTE_L ADC_OSR MONO

LSTHERM

IGNORE

LINEL

LINER

HPTHERM

IGNORE

CP_FORCEAUX-6dB LS-6dB HP-6dB EPMODE

AUX_L_LEVEL

AUX_R_LEVEL

ADC

ADC_CLK_DIV (T)

DAC

LM49350

L

R

CL

M

27 www.national.com

Address Register 7 6 5 4 3 2 1 0

0x31h DAC_CLO

LM49350

0x32h DAC_DSP DAC_TRI

0x40h IPLVL1 PORT2_RX_R_LVL PORT2_RX_L_LVL PORT1_RX_R_LVL PORT1_RX_L_LVL

0x41h IPLVL2 INTERP_L_LVL INTERP_R_LVL ADC_R_LVL ADC_L_LVL

0x42h OPPORT1 MONO SWAP R_SEL L_SEL

0x43h OPPORT2 MONO SWAP R_SEL L_SEL

0x44h OPDAC SWAP ADCR PORT2R PORT1R ADCL PORT2L PORT1L

0x45h OPDECI MXRCLK_SEL R_SEL L_SEL

0x50h BASIC STEREO_

0x51h CLK_GEN

0x52h CLK_GEN

0x53h SYNC_GE

0x54h DATA_WI

0x55h RX_MODE A/ULAW COMPAN

0x56h TX_MODE A/ULAW COMPAN

0x60h BASIC STEREO_

0x61h CLK_GEN

0x62h CLK_GEN

0x63h SYNC_GE

0x64h DATA_WI

0x65h RX_MODE A/ULAW COMPAN

0x66h TX_MODE A/ULAW COMPAN

0x70h ADC FX ADC ADC ADC ADC ADC

0x71h DAC FX DAC DAC DAC DAC DAC

0x80h HPF HPF MODE

0x81h ADC SOURCE SOURCE STEREO LIMITER SAMPLE_RATE

CK

DIGITAL MIXER

AUDIO PORT 1

STEREO_

SYNC_MO

DE

1

2

N

TX_EXTRA_BITS TX_WIDTH RX_WIDTH

DTH

SYNC_MO

DE

1

2

N

TX_EXTRA_BITS TX_WIDTH RX_WIDTH

DTH

ALC 1 OVR SEL LINK

SYNC_PH

ASE

CLK_SEL HALF_CYCLE_DIVDER

SYNTH_D

SYNC_WIDTH(MONO MODE) SYNC_RATE

D

D

STEREO_
SYNC_PH

ASE

CLK_SEL HALF_CYCLE_DIVDER

SYNTH_D

SYNC_WIDTH(MONO MODE) SYNC_RATE

D

D

CLK_PH SYNC_MS CLK_MS TX_ENB RX_ENB STEREO

AUDIO PORT 2

CLK_PH SYNC_MS CLK_MS TX_ENB RX_ENB STEREO

EFFECTS ENGINE

ADC EFFECTS

DAC_CLK_DIV (S)

SYNTH_NOM

ENOM

MSB_POSITION RX_MODE

MSB_POSITION TX_MODE

SYNTH_NOM

ENOM

MSB_POSITION RX_MODE

MSB_POSITION TX_MODE

SCLP ENB EQ ENB PK ENB ALC ENB HPF_ENB

SCLP ENB 3D ENB EQ ENB PK ENB ALC ENB

M

www.national.com 28

Address Register 7 6 5 4 3 2 1 0

0x82h ADC NG_ENB NOISE_FLOOR

ALC 2

0x83h ADC ALC_TARGET_LEVEL

ALC 3

0x84h ADC ATTACK_RATE

ALC 4

0x85h ADC PK_DECAY_RATE DECAY_RATE/RELEASE_RATE

ALC 5

0x86h ADC HOLDTIME

ALC 6

0x87h ADC MAX_LEVEL

ALC 7

0x88h ADC MIN_LEVEL

ALC 8

0x89h ADC L ADC_L_LEVEL

LEVEL

0x8Ah ADC R ADC_R_LEVEL

LEVEL

0x8Bh EQ BAND

1

0x8Ch EQ BAND

2

0x8Dh EQ BAND

3

0x8Eh EQ BAND

4

0x8Fh EQ BAND

5

0x90h SOFTCLIP

1

0x91h SOFTCLIP

2

0x92h SOFTCLIP

3

0x98h LVLMONL ADC LEFT LEVEL MONITOR

0x99h LVLMONR ADC RIGHT LEVEL MONITOR

0x9Ah FXCLIP SCLP_R SCLP_L EQ_R EQ_L GAIN_R

0x9Bh ALCMONL SCLP_R SCLP_L ADC LEFT ALC MONITOR

0x9Ch ALCMONR SCLP_L SCLP_R ADC RIGHT ALC MONITOR

0xA0h DAC STEREO LIMITER SAMPLE_RATE

ALC 1 LINK

0xA1h DAC NG_ENB NOISE_FLOOR

ALC 2

0xA2h DAC AGC_TARGET_LEVEL

ALC 3

0xA3h DAC ATTACK_RATE

ALC 4

LEVEL FREQ

Q LEVEL FREQ

Q LEVEL FREQ

Q LEVEL FREQ

LEVEL FREQ

SOFT

KNEE

RATIO

LEVEL

ADC EFFECT MONITORS

CLIP CLIP CLIP CLIP CLIP CLIP

DISTORT DISTORT

DISTORT DISTORT

DAC EFFECTS

CLIP

THRESHOLD

GAIN_L

CLIP

ADC_R ADC_L

LM49350

29 www.national.com

Address Register 7 6 5 4 3 2 1 0

0xA4h DAC PK_DECAY_RATE DECAY_RATE/RELEASE_RATE

LM49350

0xA5h DAC HOLDTIME

0xA6h DAC MAX_LEVEL

0xA7h DAC MIN_LEVEL

0xA8h DAC L DAC_L_LEVEL

0xA9h DAC R DAC_R_LEVEL

0xAAh DAC_3D ATTEN FILTER_TYPE EFFECT_LEVEL EFFECT_

0xABh EQ BAND

0xACh EQ BAND

0xADh EQ BAND

0xAEh EQ BAND

0xAFh EQ BAND

0xB0h SOFTCLIP

0xB1h SOFTCLIP

0xB2h SOFTCLIP

0xB8h LVLMONL DAC LEFT LEVEL MONITOR

0xB9h LVLMONR DAC RIGHT LEVEL MONITOR

0xBAh FXCLIP SCLP_R SCLP_L EQ_R EQ_L 3D_R 3D_L GAIN_R

0xBBh ALCMONL SCLP_R SCLP_L DAC LEFT ALC MONITOR

0xBCh ALCMONR SCLP_L SCLP_R DAC RIGHT ALC MONITOR

0xE0h GPIO TEMP SHORT GPIO_RX GPIO_TX GPIO_MODE

0xF1h SS SS_DISABLERSVD RSVD

ALC 5

ALC 6

ALC 7

ALC 8

LEVEL

LEVEL

1

2

3

4

5

1

2

3

LEVEL FREQ

Q LEVEL FREQ

Q LEVEL FREQ

Q LEVEL FREQ

LEVEL FREQ

SOFT

KNEE

RATIO

LEVEL

DAC EFFECT MONITORS

CLIP CLIP CLIP CLIP CLIP CLIP

DISTORT DISTORT

DISTORT DISTORT

GPIO

SPREAD SPECTRUM

THRESHOLD

CLIP

MODE

GAIN_L

CLIP

ADC COMPENSATION FILTER

0xF8h ADC_C0_L

SB

0xF9h ADC_C0_

MSB

0xFAh ADC_C1_L

SB

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ADC_C0_LSB

ADC_C0_MSB

ADC_C1_LSB