National Semiconductor LM4550B Technical data

September 2006

LM4550B AC ’97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound

LM4550B AC ’97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample

Rate Conversion and National 3D Sound

General Description

The LM4550B is an audio codec for PC systems which is fully PC99 compliant and performs the analog intensive functions of the AC ’97 Rev 2.1 architecture. Using 18-bit Sigma-Delta ADCs and DACs, the LM4550B provides 90 dB of Dynamic Range.

The LM4550B was designed specifically to provide a high quality audio path and provide all analog functionality in a PC audio system. It features full duplex stereo ADCs and DACs and analog mixers with access to 4 stereo and 4 mono inputs. Each mixer input has separate gain, attenuation and mute control and the mixers drive 1 mono and 2 stereo outputs, each with attenuation and mute control. The LM4550B provides a stereo headphone amplifier as one of its stereo outputs and also supports National’s 3D Sound stereo enhancement and a comprehensive sample rate conversion capability. The sample rate for the ADCs and DACs can be programmed separately with a resolution of 1 Hz to convert any rate in the range 4 kHz – 48 kHz. Sample timing from the ADCs and sample request timing for the DACs are completely deterministic to ease task scheduling and application software development. These features together with an extended temperature range also make the LM4550B suitable for non-PC codec applications.

The LM4550B features the ability to connect several codecs together in a system to provide up to 6 simultaneous channels of streaming data on Output Frames (Controller to Codec) for surround sound applications. Such systems can also support up to 8 simultaneous channels of streaming data on Input Frames (Codec to Controller). Multiple codec systems can be built either using the standard AC Link configuration (i.e. of one serial data signal to the Controller per codec) or using a unique National Semiconductor feature for chaining codecs together. This chain feature shares only a single data signal to the controller among multiple codecs.

The AC ’97 architecture separates the analog and digital functions of the PC audio system allowing both for system design flexibility and increased performance.

Key Specifications

n Analog Mixer Dynamic Range 97 dB (typ) n DAC Dynamic Range 89 dB (typ) n ADC Dynamic Range 90 dB (typ) n Headphone Amp THD+N at 50 mW 0.02% (typ)

into 32Ω

Features

n AC ’97 Rev 2.1 compliant n High quality Sample Rate Conversion from 4 kHz to 48

kHz in 1 Hz increments

n Supports up to 6 DAC channel systems with multiple

LM4550Bs or with other National LM45xx codecs

n Unique National chaining function shares a single

controller SDATA_IN pin among multiple codecs

n Stereo headphone amp with separate gain control n National’s 3D Sound stereo enhancement circuitry n Advanced power management support n External Amplifier Power Down (EAPD) control n PC Beep passthrough to Line Out during Initialization or

Cold Reset

n Digital 3.3V and 5V supply options n Extended Temperature: −40˚C ≤ T

≤ 85˚C

Applications

n Desktop PC audio systems on PCI cards, AMR cards, or

with motherboard chips sets featuring AC Link

n Portable PC systems as on MDC cards, or with a

chipset or accelerator featuring AC Link

n General Audio Frequency Systems requiring 2, 4 or 6

DAC channels and/or up to 8 ADC channels

n Automotive telematics

LM4550B

20123701

Block Diagram

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LM4550B

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage 6.0V

Soldering Information

LQFP Package

Vapor Phase (60 sec.) 215˚C

Infrared (15 sec.) 220˚C

(typ) – VBH48A 74˚C/W

Storage Temperature −65˚C to +150˚C

Input Voltage −0.3V to V

+0.3V

Operating Ratings

ESD Susceptibility (Note 2) 2000V

pin 3 750

ESD Susceptibility (Note 3) 200V

pin 3 100V

Junction Temperature 150˚C

Electrical Characteristics (Notes 1, 5) The following specifications apply for AV

48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for T

Temperature Range

MIN

≤ TA≤ T

(Note 4) −40˚C ≤ TA≤ 85˚C

MAX

Analog Supply Range 4.2V ≤ AV

Digital Supply Range 3.0V ≤ DV

= 5V, DVDD= 3.3V, Fs =

= 25˚C. The reference for 0 dB

≤ 5.5V

is 1 Vrms unless otherwise specified.

Units

(Limits)

Symbol Parameter Conditions

Analog Supply Range 4.2 V (min)

LM4550B

Typical

(Note 6)

Limit

(Note 7)

5.5 V (max)

Digital Supply Range 3.0 V (min)

5.5 V (max)

= 5 V 34 mA

DSD

ASD

IDD

REF

Digital Quiescent Power Supply Current

Analog Quiescent Power Supply Current

Digital Shutdown Current PR6543210 = 1111111 19 µA

Analog Shutdown Current PR6543210 = 1111111 70 µA

Reference Voltage No pullup resistor 2.16 V

= 3.3 V 19 mA

= 5 V 53 mA

PSRR Power Supply Rejection Ratio 40 dB

Analog Loopthrough Mode (Note 8)

Dynamic Range (Note 9)

THD Total Harmonic Distortion V

CD Input to Line Output, -60 dB Input THD+N

=-3dB,f=1kHz, RL=10kΩ 0.013 0.02 % (max)

97 90 dB (min)

Analog Input Section

Line Input Voltage

Mic Input with 20 dB Gain 0.1 Vrms

Mic Input with 0 dB Gain 1 Vrms

LINE_IN, AUX, CD, VIDEO, PC_BEEP, PHONE

1 Vrms

Xtalk Crosstalk CD Left to Right −95 dB

Input Impedance (Note 9) All Analog Inputs 40 10 kΩ (min)

Input Capacitance(Note 9) 3.7 7 pF

Interchannel Gain Mismatch CD Left to Right 0.10 dB

Record Gain Amplifier - ADC

Step Size 0 dB to 22.5 dB 1.5 dB

Mute Attenuation (Note 9) 86 dB

Mixer Section

Step Size +12 dB to -34.5 dB 1.5 dB

Mute Attenuation(Note 9) 86 dB

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Electrical Characteristics (Notes 1, 5) The following specifications apply for AV

48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for T is 1 Vrms unless otherwise specified. (Continued)

LM4550B

= 5V, DVDD= 3.3V, Fs =

= 25˚C. The reference for 0 dB

Units

(Limits)

Symbol Parameter Conditions

LM4550B

Typical

(Note 6)

Limit

(Note 7)

Analog to Digital Converters

Resolution 18 Bits

Dynamic Range (Note 9) -60 dB Input THD+N, A-Weighted 90 86 dB (min)

Frequency Response -1 dB Bandwidth 20 kHz

Digital to Analog Converters

Resolution 18 Bits

Dynamic Range (Note 9) -60 dB Input THD+N, A-Weighted 89 82 dB (min)

THD Total Harmonic Distortion V

=-3dB,f=1kHz, RL=10kΩ 0.01 %

Frequency Response 20-21 k Hz

Group Delay (Note 9) Sample Freq. = 48 kHz 0.36 1

(max)

Out of Band Energy (Note 10) -40 dB

Stop Band Rejection 70 dB

Discrete Tones -96 dB

Analog Output Section

THD+N

OUT

Step Size 0 dB to -46.5 dB 1.5 dB

Mute Attenuation(Note 9) 86 dB

Headphone Amplifier Total Harmonic Distortion plus Noise

Loopthrough Mode (Note 8), R f = 1 kHz, P

=50mW

out

=32Ω,

0.02 %

Output Impedance (Note 9) HP_OUT_L, HP_OUT_R 0.65 2.75 Ω

Output Impedance (Note 9)

LINE_OUT_L, LINE_OUT_R, MONO_OUT

220 500 Ω

Digital I/O (Note 9)

High level input voltage

Low level input voltage

High level output voltage IO= −2.5 mA.

Low level output voltage IO= 2.5 mA.

Input Leakage Current AC Link inputs

Tri state Leakage Current High impedance AC Link outputs

0.65 x DV

0.35 x DV

0.90 x DV

0.10 x DV

10 µA

V (min)

V (max)

V (min)

V (max)

Cin AC-Link I/O capacitance SDout, BitClk, SDin, Sync, Reset# only 4 7.5 pF (max)

Output drive current AC Link outputs 5 mA

Digital Timing Specifications (Note 9)

BCP

SYNC

DSETUP

BIT_CLK frequency 12.288 MHz

BIT_CLK period 81.4 ns

BIT_CLK high

Variation of BIT_CLK duty cycle from 50%

20 % (max)

SYNC frequency 48 kHz

SYNC period 20.8 µs

SYNC high pulse width 1.3 µs

SYNC low pulse width 19.5 µs

Setup Time for codec data input SDATA_OUT to falling edge of BIT_CLK 3.5 10 ns (min)

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LM4550B

Electrical Characteristics (Notes 1, 5) The following specifications apply for AV

48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for T

= 5V, DVDD= 3.3V, Fs =

= 25˚C. The reference for 0 dB

is 1 Vrms unless otherwise specified. (Continued)

JMAX

Units

(Limits)

ns (max)

= 150˚C.

Symbol Parameter Conditions

DHOLD

SSETUP

SHOLD

RISE

FALL

RST_LOW

RST2CLK

SYNC2CLK

S2_PDOWN

SUPPLY2RST

SU2RST

RST2HZ

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC andAC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance.

Note 2: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

Note 3: Machine Model, 220 pF – 240 pF discharged through all pins.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

allowable power dissipation is P The typical junction-to-ambient thermal resistance is 74˚C/W for package number VBH48A.

Note 5: All voltages are measured with respect to the ground pin, unless otherwise specified.

Note 6: Typicals are measured at 25˚C and represent the parametric norm.

Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 8: Loopthrough Mode describes a path from an analog input through the analog mixers to an analog output.

Note 9: These specifications are guaranteed by design and characterization; they are not production tested.

Note 10: Out of band energy is measured from 28.8 kHz to 100 kHz relative toa1VrmsDACoutput.

Hold Time for codec data input

Setup Time for codec SYNC input

Hold Time for codec SYNC input

Output Valid Delay

Rise Time

Fall Time

Chain Propagation Delay

RESET# active low pulse width For Cold Reset 1.0 µs (min)

RESET# inactive to BIT_CLK start up

SYNC active high pulse width For Warm Reset 1.0 µs (min)

SYNC inactive to BIT_CLK start up For Warm Reset 162.8 ns (min)

AC Link Power Down Delay

Power On Reset

Setup to trailing edge of RESET# For ATE Test Mode 15 ns (min)

Rising edge of RESET# to Hi-Z For ATE Test Mode 25 ns (max)

DMAX

=(T

)/θJAor the number given in Absolute Maximum Ratings, whichever is lower. For the LM4550B, T

JMAX–TA

Hold time of SDATA_OUT from falling edge of BIT_CLK (Note 9)

SYNC to falling edge of BIT_CLK (Note

Hold time of SYNC from falling edge of BIT_CLK

Output Delay of SDATA_IN from rising edge of BIT_CLK (Note 9)

BIT_CLK, SYNC, SDATA_IN or SDATA_OUT

Data Delay from CIN to SDATA_IN when the chain feature is active

For Cold Reset 271 162.8 ns (min)

Delay from end of Slot 2 to BIT_CLK, SDATA_IN low

Time from minimum valid supply levels to end of Reset

, θJA, and the ambient temperature TA. The maximum

JMAX

LM4550B

Typical

(Note 6)

Limit

(Note 7)

5.3 10 ns (min)

3.8 10 ns (min)

10 ns (min)

5.2 15 ns (max)

6 ns (max)

1 µs (max)

1 µs (min)

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Timing Diagrams

LM4550B

Clocks Data Delay, Setup and Hold

20123710

20123711

Digital Rise and Fall Legend

20123730

20123712

Power On Reset

Cold Reset

Warm Reset

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20123729

20123713

20123714

Typical Application

LM4550B

20123703

FIGURE 1. LM4550B Typical Application Circuit, Single Codec, 1 Vrms inputs

APPLICATION HINTS

The LM4550B must be initialized by using RESET# to perform a Power On Reset as shown in the Power On Reset Timing

•

Diagram Don’t leave unused Analog inputs floating. Tie all unused inputs together and connect to Analog Ground through a capacitor

•

(e.g. 0.1 µF) Do not leave CD_GND floating when using the CD stereo input. CD_GND is the AC signal reference for the CD channels and

•

should be connected to the CD source ground (Analog Ground may also be acceptable) througha1µFcapacitor If using a non-standard AC Link controller take care to keep the SYNC and SDATA_OUT signals low during Cold Reset to

•

avoid accidentally activating the ATE or Vendor test modes The PC_Beep input should be explicitly muted if not used since it defaults to 0 dB gain on reset, unlike the mute default of the

•

other analog inputs

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LM4550B

20123725

Typical Application (Continued)

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FIGURE 2. LM4550B Reference Design, Typical Application, Single Codec, 1 Vrms and 2 Vrms inputs, EMC output filters

Connection Diagram

LM4550B

Pin Descriptions

Name Pin I / O

PC_BEEP 12 I

PHONE 13 I

Top View

20123702

Order Number LM4550BVH

See NS Package Number VBH48A

ANALOG I/O

Functional Description

Mono Input This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the PC_Beep Volume control register, 0Ah. The PC_BEEP level can be muted or adjusted from 0 dB to -45 dB in 3 dB steps. The Stereo Mix signal feeds both the Line Out and Headphone Out analog outputs and is also selectable at the Record Select Mux. During Initialization or Cold Reset, (reset pin held active low), PC_BEEP is switched directly to both channels of the Line Out stereo output, bypassing all volume controls. This allows signals such as PC power-on self-test tones to be heard through the PC’s audio system before the codec registers are configured.

Mono Input This line level (1 Vrms nominal) mono input is selectable at the Record Select Mux for conversion by either or both channels of the stereo ADC. It can also be mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the Phone Volume register, 0Ch. The PHONE level can be muted or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. The Stereo Mix signal feeds both the Line Out and Headphone Out analog stereo outputs and is also selectable at the Record Select Mux.

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Pin Descriptions (Continued)

LM4550B

Name Pin I / O

AUX_L 14 I

AUX_R 15 I

VIDEO_L 16 I

VIDEO_R 17 I

CD_L 18 I

CD_GND 19 I

CD_R 20 I

ANALOG I/O (Continued)

Functional Description

Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the Aux Volume register, 16h. The AUX_L level can be muted (along with AUX_R) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.

Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record Select Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the Aux Volume register, 16h. The AUX_R level can be muted (along with AUX_L) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.

Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_L level can be muted (along with VIDEO_R) or adjusted from +12 dB to -34.5 dB in

1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.

Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record Select Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_R level can be muted (along with VIDEO_L) or adjusted from +12 dB to

-34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.

Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Input Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the CD Volume register, 12h. The CD_L level can be muted (along with CD_R) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is mixed into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.

AC Ground Reference This input is the reference for the signals on both CD_L and CD_R. CD_GND is NOT a DC ground and must be AC-coupled to the stereo source ground common to both CD_L and CD_R. The three inputs CD_GND, CD_L and CD_R act together as a quasi-differential stereo input with CD_GND providing AC common-mode feedback to reject ground noise. This can improve the input SNR for a stereo source with a good common ground but precision resistors may be needed in any external attenuators to achieve the necessary balance between the two channels.

Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the CD Volume register, 12h. The CD_R level can be muted (along with CD_L) or adjusted from +12 dB to -34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.

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+ 21 hidden pages

National Semiconductor LM4550B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Key Specifications

Features

Applications

Block Diagram

Absolute Maximum Ratings (Note 1)

Operating Ratings

Electrical Characteristics (Notes 1, 5) The following specifications apply for AV

Timing Diagrams

Typical Application

FIGURE 1. LM4550B Typical Application Circuit, Single Codec, 1 Vrms inputs

APPLICATION HINTS

Connection Diagram

Pin Descriptions

ANALOG I/O