National Semiconductor LM4308 Technical data

September 2007

LM4308 Mobile Pixel Link Two (MPL-2) – 18-bit CPU Display Interface Master/Slave

General Description

The LM4308 device adapts a 18-bit CPU style display interfaces to a MPL-2 SLVS differential serial link for displays. Two chip selects support a main and sub display up to and beyond 640 x 480 pixels. A mode pin configures the device as a Master (MST) or Slave (SLV). Both WRITE and READ operations are supported. CPU interface widths below 18-bits are supported by tieing unused inputs to a static level.

The differential line drivers and receivers conform to the JEDEC SLVS Standard. When noise is picked up as common-mode, it is rejected by the receivers. This is further enhanced with the 50 Ohm output impedance of the drivers. The 100 Ohm termination is integrated into the receivers.

Data integrity is insured with a 5-bit CRC field. CRC checking is done for both WRITE and READ operations. An Error (ERR) pin reports the occurrence of an error. A Write Only mode is also provided.

The interconnect is reduced from 23 signals to only 4 active signals with the LM4308 chipset easing flex interconnect design, size constraints and cost.

A low power sleep state entered when the PD* inputs are driven low.

Features

18-bit i80 CPU Display Interface

■

Supports up to 640 x 480 VGA formats

■

Differential SLVS Interface

■

Dual displays supported

■

WRITE and READ operations supported

■

Robust Differential Physical Layer

■

400mVpp differential signal swing

■

Internal 100 Ω Termination Resistor

■

Low Power Consumption

■

5-bit CRC for data integrity

■

Level translation between host and display

■

Low Power sleep state

■

3.3V Tolerant Master Clock Input regardless of V

■

Fast Start Up Time - 1k CLK cycles

■

1.6V to 2.0V core / analog supply voltage

■

1.6V to 3.0V I/O supply voltage range

■

System Benefits

Small Interface

■

Low Power

■

Low EMI

■

Intrinsic Level Translation

■

DDIO

Typical Application Diagram

20189601

Pin Descriptions

LM4308

Pin Name

SLVS SERIAL BUS PINS

DDP 1 1 IO, slvs Differential Data - Positive, Transceiver

DDN 1 1 IO, slvs Differential Data - Negative, Transceiver

DCP 1 1 O, I, slvs Differential Clock - Positive,

DCN 1 1 O, I, slvs Differential Clock - Negative,

CONFIGURATION/PARALLEL BUS PINS

M/S* 1 1 I,

TM 1 1 I,

PLLCON

[1:0]

RDS[1:0] 2 2 I,

ERR 1 1 O,

WO 1 1 I,

CLOCK / POWER DOWN SIGNALS

CLK 1 1 I,

PD* 1 1 I,

PARALLEL INTERFACE SIGNALS

D[17:0] 18 18 IO,

CS1* CS2*

RD* 1 1 I, O,

WR* 1 1 I, O,

AD 1 1 I, O,

No.

of Pads

uArray

2 2 I,

2 2 I, O,

No.

of Pins

LLP

I/O, Type

LVCMOS

CPU Master

(MST)

Line Driver

High for Master Low for Slave

Test Mode Control Input

Tie Low

L = Normal H = Test Mode (factory test only)

PLL Multiplier Input Pins See PLLCON[1:0] - PLL Multiplier

Settings

NA Receiver Drive Strength Control Input

Error Output Signal Indicates a CRC error on the READ Payload

NA WRITE Only Control Input

CLK Input Input is 3.3V Tolerant regardless of V

DDIO

Power Down Input, L = Powered down, Low Power SLEEP state H = active state

CPU Data Bus Inputs / Outputs CPU Data Bus Outputs / Inputs

Chip Select Input Pins Only one CS is allowed to be Low at a time.

Read Enable Input, active Low

Write Enable Input, active Low

Address / Data selector input Address / Data selector output

Description

CPU Slave

(SLV)

Differential Clock - Positive, Receiver

Differential Clock - Clock, Receiver

NA

Pins, See RDS[1:0] - Receiver Output Drive

Strength

Error Output Signal Reports a CRC error was detected on the WRITE Payload

L = Writes and reads enabled H = Write Only

NA

Chip Select Output Pins

Read Enable Output, active Low

Write Enable Output, active Low

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LM4308

Pin Name

No.

of Pads

uArray

No.

of Pins

LLP

I/O, Type

POWER/GROUND PINS

V

DDA

V

SSA

V

DD

V

SS

V

DDIO

V

SSIO

DAP NA *

1 1 Power Power Supply Pin for the PLL (MST) and SLVS Interface. 1.6V to 2.0V

1 1 Ground Ground Pin for the PLL (MST) and SLVS Interface.

1 1 Power Power Supply Pin for the digital core. 1.6V to 2.0V

1 * Ground Ground Pin for the digital core.

2 2 Power Power Supply Pin for the parallel interface I/Os. 1.6V to 3.0V

9 * Ground Ground Pin for the parallel interface I/Os.

Connect to Ground - LLP Package

1

Note:

I = Input, O = Output, IO = Input/Output. Do not float input pins.

PLLCON[1:0] - PLL Multiplier Settings

PLLCON1 PLLCON0 Multiplier

L L 8X

L H 10X

H L 12X

H H Reserved

Description

CPU Master

(MST)

For the LLP Package, VSSIO and VSS

Ground pin for V

SSIO

and V

SS

RDS[1:0] - Receiver Output Drive Strength

RDS1 RDS0 Result

L L Use with High V

L H Increased drive on DATA, AD, and

H L Increased drive on WR* and RD*

H H All outputs, use for Low V

CPU Slave

(SLV)

operation

DDIO

CS1*/CS2* outputs

Increased drive strength on all

DDIO

outputs

,

Ordering Information

NSID Package Type Package ID

LM4308GR 49L MicroArray, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch GRA49A

LM4308SQ 40L LLP, 5.0 X 5.0 X 0.8 mm, 0.4 mm pitch SQF40A

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

LM4308

please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (V

Supply Voltage (VDD)

Supply Voltage (V

LVCMOS Input/Output Voltage −0.3V to (V

CLK LVCMOS Input Voltage −0.3V to +3.3V SLVS Input/Output Voltage −0.3V to V

Junction Temperature +150°C Storage Temperature −65°C to +150°C ESD Ratings:

HBM, 1.5 kΩ, 100 pF

EIAJ, 0Ω, 200 pF

DDA

DDIO

)

−0.3V to +2.2V

)

−0.3V to +3.6V

DDIO

+0.3V)

DDA

≥±2 kV

≥±200V

GRA Package 2.75 W Derate GRA Package above 25°C 22 mW/°C SQF Package 3.43 W Derate SQF Package above 25°C 27 mW/°C

Recommended Operating Conditions

Min Typ Max Units

Supply Voltage

V

to V

SS

SSA

SSIO

and

V V

DDA

DD

DDIO

to V

Clock Frequency 9.6 30 MHz DC (Serial) Clock Frequency 76.8 240 MHz Ambient Temperature −40 25 85 °C

1.6 1.8 2.0 V

1.6 3.0 V

Maximum Package Power Dissipation Capacity at 25°C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)

Symbol Parameter Conditions Min Typ Max Units

SLVS

V

ΔV

V

ΔV

R

V

R

V

OD

OS

OUT

OH

T

IDH

IDL

CM

Differential Output Voltage

(Note 9)

100 Ω Load

Match

Driver Offset Voltage

Driver Offset Voltage Match (Note 9)

Driver Output Impedance High Output

Low Output

High Level Output Voltage (Diff. Mode)

Receiver Differential Termination Resistor

Differential Input High Threshold

DD (RX) Configuration or DC (SLV) (Note

8)

RX, VCM = 35mV, 200mV and 365mV (Note 9)

Differential Input Low Threshold

Receiver Common Mode

RX with VID = |70mV|

Input Range

140 200 270 mV

-10 0 10 mV

150 200 250 mV

-5 0 5 mV

50

360 mV

80 100 125

10 70 mV

−70 -10 mV

35 365 mV

Ω

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Symbol Parameter Conditions Min Typ Max Units

LVCMOS

V

IH

V

IL

V

HY

I

IH

Input Voltage High Level 0.7 V

Input Voltage Low Level

GND

Input Hysteresis

Input Current High Level LVCMOS Inputs VIN = V

DDIO

V

0.3 V

DDIO

160 mV

−1 0 +1 µA

V

CLK Input VIN = 3.3V

V

DDIO

= 1.8V

0 +8 µA

(Note 10)

CLK Input VIN = 1.8V

V

= 1.8V

DDIO

I

IL

V

OH

Input Current Low Level

Output Voltage High Level IOH = −2 mA

RDS = H VDD = 1.6 V , V

DDIO

= 2.0 V

−1 0 +1 µA

0.75 V

DDIO

V

DDIO

V

IOH = −2 mA RDS = L VDD = 2.0 V , V

V

OL

Output Voltage Low Level IOL = 2 mA

DDIO

= 3.0 V

RDS = H VDD = 1.6V , V

DDIO

= 2.0 V

0.8 V

V

SSIO

DDIO

V

0.2 V

DDIO

V

IOL = 2 mA RDS = L VDD = 2.0 V , V

DDIO

= 3.0 V

V

SSIO

0.2 V

DDIO

V

SUPPLY CURRENT

I

DD

Total Supply Current— Enabled Conditions: CLK = 30MHx (8X mode), DC = 240MHz, DD = 480Mbps Worse Case Data Pattern,

Master (Note 11)

Slave (Note 11)

V

DDIO

VDD/V

V

DDIO

VDD/V

DDA

64 µA

18 mA

7 mA

constant WRITE

I

DDZ

Supply Current—Enabled Bus Idle (WR* = H)

Supply Current—Disable Power Down Modes

Master V

Slave V

Master PD* = L, or CLK stop

Slave PD* = L, or Auto Sleep

DDIO

VDD/V

DDIO

VDD/V

V

DDIO

VDD/V

V

DDIO

VDD/V

DDA

10 µA

8.2 mA

>1 µA

2.9 mA

8 µA

9 µA

8 µA

9 µA

PD Power Dissipation 25% Bus active Master 15 mW

Slave 6 mW

Idle Bus Master 14.8 mW

Slave 5.2 mW

QVGA (Note 5)

Master 195 µW

Slave 8 µW

PD*=L Master >0.1 µW

Slave >0.1 µW

LM4308

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Switching Characteristics

LM4308

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)

Symbol Parameter Conditions Min Typ Max Units

PARALLEL BUS TIMING See alsoTable 2 and Figure 9

t

SET

t

HOLD

t

RISE

t

FALL

SERIAL BUS TIMING

t

DVBC

t

DVAC

t

Sset

t

Shold

t

T

POWER UP TIMING

t

a

t

b

t

c

t

d

t

e

t

f

t

SU

POWER OFF TIMING

t

O

Set Up Time Master Input, WRITE

Hold Time

Rise Time RD* and WR* Slave

Outputs(Note 4) CL = 15 pF,

Figure 2

Fall Time V

V

= 1.6V

DDIO

RDS = H

V

= 3.0V

DDIO

RDS = L

= 1.6V

DDIO

RDS = H

V

= 3.0V

DDIO

RDS = L

Data Valid before DC Clock Master

Data Valid after DC Clock

(Note 9)

Serial Set Time Slave

Serial Hold Time

(Note 8)

26% 74% UI

400 ps

Transition Time Master 20% to 80%

DC ON High Delay Link Start Up Sequence

DC Low Delay

DC Active Delay

DD High Delay

DD Low Delay

DD Differential ON

Start Up Delay

ta +tb + tc + td + te + t

f

Includes PLL Lock Time

Turn Off Delay (Note 7)

5 ns

7 ns

6 ns

200 ps

128

504

128

8

128

1,024

0.1 2 µs

CLK

cycles

CLK

cycles

CLK

cycles

CLK

cycles

CLK

cycles

CLK

cycles

CLK

cycles

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Recommended Input Timing Requirements

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)

Symbol Parameter Conditions Min Typ Max Units

MASTER REFERENCE CLOCK (CLK)

f Clock Frequency 9.6 30 MHz

t

CP

CLK

t

T

t

CLKgap

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for V

Note 3: Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise

specified.

Note 4: Rise and Fall Time tested on the following pins only: WR* and RD*.

Note 5: Typical PD for QVGA application. Conditions: 1.8V, 25C, 19.2MHz CLK and 8X, 10% blanking, 1fps. Link is started up, 1 frame (240 x 320) is sent and

link is powered down.

Note 6: Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality.

Note 7: Guaranteed functionally by the I

Note 8: Specification is guaranteed by design and is not tested in production.

Note 9: Specification is guaranteed by characterization and is not tested in production.

Note 10: When clock input is in overdrive ( Vin = 3.3 V ) and then stop clock is applied, it is recommended to set input clock to a low state.

Note 11: For IDD measurments a checkerboard pattern 2AAAA-15555 was used.

Clock Period

Clock Duty Cycle

DC

Clock/Data Transition Times

CLK Stop Gap

(Rise or Fall, 10%–90%)(Note 6) 2 >2 ns

4 CLKcycles

= 1.8V and VDD = V

DDIO

parameter. See also Figure 7.

DDZ

= 1.8V and TA = 25°C.

DDA

33.3 104.2 ns

30 50 70 %

Timing Diagrams

LM4308

FIGURE 1. Serial Data Valid & Set/Hold Times

20189618

FIGURE 2. Slave Output Rise and Fall Time (WR* and RD*)

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20189616

Functional Description

LM4308

BUS OVERVIEW

The LM4308 is a Master (SER) / Slave (DES) configurable part that supports a 18-bit (or less) i80 CPU Display interface. Both WRITE and READ transactions are supported. The SLVS physical layer is purpose-built for an extremely low power and low EMI data transmission while requiring the fewest number of signal lines. No external line components are required, as termination is provided internal to the SLVS receiver. A maximum raw throughput of 480 Mbps (raw) is possible with this chipset. The SLVS interface is designed for use with 100Ω differential lines.

20189603

FIGURE 4. Serial Link Timing (WRITE)

Data is strobed out on the Rising edge by the Slave for a CPU READ as shown in Figure 5. The Master monitors for the start bit transition (High to Low) and then selects the best strobe to sample the incoming data on. This is done to account for the round trip delay of the interconnect and application data rate. Since READ data is sent on one edge only, the back channel rate (READ) is one quarter that of the WRITE rate.

20189604

20189602

FIGURE 3. SLVS Point-to-Point Bus

SERIAL BUS TIMING

Data valid is relative to both edges for a CPU WRITE as

SERIAL BUS PHASES

There are five bus phases on the serial bus. These are determined by the state of the DC and DD lines. The bus phases are shown in Table 1.

FIGURE 5. Serial Link Timing (READ)

shown in Figure 4. Data valid is specified as: Data Valid before Clock, Data Valid after Clock, and Skew between data lines should be less than 500ps.

TABLE 1. Link Phases

Name DC State DD State Phase Description Pre-Phase Post-Phase

OFF (O) GND GND Link is Off A, I or LU LU

IDLE (I) A H Idle, MD(s) = Logic Low A or LU A or O

ACTIVE (A),

A X Write Payloads LU, A, or I A, I, or O

Write

ACTIVE, Read

Read Command A X

(MST)

Read Command A, or I

TA’ A HUH MD Turn Around RC RD

Read Data A X

Read Payload TA’ TA"

(SLV)

TA" A HUH MD Turn Around RD I

LINK-UP

Master * * Start Up O A, I, or O

(LU)

Notes on DC/DD Line State:

0 = no current (off)

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