National Semiconductor LM3433 Technical data

March 7, 2008

LM3433
Common Anode Capable High Brightness LED Driver with
High Frequency Dimming

LM3433 Common Anode Capable High Brightness LED Driver with High Frequency Dimming

General Description

The LM3433 is an adaptive constant on-time DC/DC buck
(step-down) constant current controller (a true current
source). The LM3433 provides a constant current for illumi­nating high power LEDs. The output configuration allows the
anodes of multiple LEDs to be tied directly to the ground ref­erenced chassis for maximum heat sink efficacy. The high
frequency capable architecture allows the use of small exter­nal passive components and no output capacitor while main­taining low LED ripple current. Two control inputs are used to
modulate LED brightness. An analog current control input is
provided so the LM3433 can be adjusted to compensate for
LED manufacturing variations and/or color temperature cor­rection. The other input is a logic level PWM control of LED
current. The PWM functions by shorting out the LED with a
parallel switch allowing high PWM dimming frequencies. High
frequency PWM dimming allows digital color temperature
control, interference blanking, field sequential illumination,
and brightness control. Additional features include thermal
shutdown, VCC under-voltage lockout, and logic level shut­down mode. The LM3433 is available in a low profile LLP-24
package.

Typical Application Circuit

Features

Operating input voltage range of -9V to -14V w.r.t. LED

■

anode
Control inputs are referenced to the LED anode

■

Output current greater than 6A

■

Greater than 30kHz PWM frequency capable

■

Negative output voltage capability allows LED anode to be

■

tied directly to chassis for maximum heat sink efficacy
No output capacitor required

■

Up to 1MHz switching frequency

■

Low IQ, 1mA typical

■

Soft start

■

Adaptive programmable ON time allows for constant ripple

■

current
LLP-24 package

■

Applications

LCD backlighting

■

Projection systems

■

Solid state lighting

■

Automotive lighting

■

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Connection Diagram

LM3433

Top View

NS Package Number SQA24A

24-Lead LLP

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Ordering Information

Order Number Spec. Package

Type

LM3433SQ NOPB LLP-24 SQA24A 1000 Units, Tape and Reel

LM3433SQX NOPB LLP-24 SQA24A 4500 Units, Tape and Reel

NSC Package

Drawing

Supplied As

Pin Descriptions

Pin Name Function

On-time programming pin. Tie an external resistor (RON) from TON to CSN, and a capacitor

1

2 ADJ

3 EN

4 DIM Logic level input for LED PWM dimming. DIM is internally tied to CGND through a 100k resistor.

5 V

6 CGND Chassis ground connection.

7 V

8 COMP

9 NC No internal connection. Tie to VEE or leave open.

10 SS

11 NC No internal connection. Tie to VEE or leave open.

12 NC No internal connection. Tie to VEE or leave open.

13 LS Low side FET gate drive return pin.

14 LO Low side FET gate drive output. Low in shutdown.

T

ON

IN

EE

(CON) from TON to VEE. This sets the nominal operating frequency when the LED is fully
illuminated.

Analog LED current adjust. Tie to VIN for fixed 60mV average current sense resistor voltage. Tie
to an external reference to adjust the average current sense resistor voltage (programmed output
current). Refer to the "V
Characteristics section and the Design Procedure section of the datasheet.

Enable pin. Connect this pin to logic level HI or VIN for normal operation. Connect this pin to
CGND for low current shutdown. EN is internally tied to VIN through a 100k resistor.

Logic power input: Connect to positive voltage between +3.0V and +5.8V w.r.t. CGND.

Negative voltage power input: Connect to voltage between –14V to –9V w.r.t. CGND.

Compensation pin. Connect a capacitor between this pin and VEE.

Soft Start pin. Tie a capacitor from SS to VEE to reduce input current ramp rate. Leave pin open
if function is not used. The SS pin is pulled to VEE when the device is not enabled.

vs. ADJ Voltage" graphs in the Typical Performance

SENSE

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Pin Name Function

15

V

CC

Low side FET gate drive power bypass connection and boost diode anode connection. Tie a

2.2µF capacitor between VCC and VEE.

16 BST High side "synchronous" FET drive bootstrap rail.

17 HO High side "synchronous" FET gate drive output. Pulled to HS in shutdown.

18 HS Switching node and high side "synchronous" FET gate drive return.

19 DIMR LED dimming FET gate drive return. Tie to LED cathode.

20 DIMO LED dimming FET gate drive output. DIMO is a driver that switches between DIMR and BST2.

21 BST2 DIMO high side drive supply pin. Tie a 0.1µF between BST2 and CGND.

22 NC No internal connection. Tie to VEE or leave open.

23 CSN Current sense amplifier inverting input. Connect to current sense resistor negative terminal.

24 CSP Current sense amplifier non-inverting input. Connect to current sense resistor positive terminal.

EP

V

EE

Exposed Pad on the underside of the device. Connect this pad to a PC board plane connected
to VEE.

Block Diagram

LM3433

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

LM3433

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

VIN, EN, DIM, ADJ to CGND

COMP, SS to V

BST to HS -0.3V to +7V
VCC to V

CGND, DIMR, CSP, CSN,
TON to V

HS to VEE (Note 2)

LS to V

EE

HO output HS-0.3V to BST+0.3V
DIMO to DIMR -0.3V to +7V
LO output LS-0.3V to VCC +0.3V

BST2 to V

Maximum Junction

EE

EE

EE

EE

-0.3V to +7.5V

-0.3V to +16V

-0.3V to +16V

-0.3V to +0.3V

-0.3V to 22.0V

-0.3V to +7V

-0.3V to +7V

150°C

Power Dissipation(Note 3) Internally Limited
ESD Susceptibility

(Note 4)
Human Body Model 2kV
Machine Model 200V
Charge Device Model 1kV

Operating Conditions

Operating Junction
Temperature Range (Note 5) −40°C to +125°C

Storage Temperature −65°C to +150°C
Input Voltage VIN w.r.t. CGND 3.0V to 5.8V

Input Voltage VEE w.r.t. CGND -9V to -14V

ADJ Input Voltage Range to
CGND

CSP, CSN Common Mode
Range With Respect to CGND

Temperature

Electrical Characteristics

Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating Temperature
Range ( TJ = −40°C to +125°C). Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical

values represent the most likely parametric norm at TJ = +25ºC, and are provided for reference purposes only. Unless otherwise
stated the following conditions apply: VEE = -12.0V and VIN = +3.3V with respect to CGND.

Symbol Parameter Conditions

SUPPLY CURRENT

IINV

EE

VEE Quiescent Current EN = CGND 3 19 µA

EN = VIN, Not Switching 1.0 mA

IINV

IN

VIN Quiescent Current EN = VIN, Not Switching 300

EN = CGND 35 71

OUTPUT CURRENT CONTROL

V

CS

G

ADJ

I

CSN

I

CSP

Gm CS to COMP

Current sense target voltage;
VCS = V

I

ADJ

(V

CNP-VCSN

– V

CSP

Gain = (V

)

CSN

-CGND)/

ADJ

Isense Input Current V

Isense Input Current V

V

= V

ADJ

IN

VIN = 3.3V, V

ADJ

w.r.t. CGND

= 1V w.r.t. CGND -50

ADJ

V

= V

ADJ

IN

= V

ADJ

IN

V

= 1V w.r.t. CGND 1

ADJ

Transconductance; Gm =
I

/ (V

– V

- V

COMP

CSP

CSN

ADJ

/

16.67)

ON TIME CONTROL

T

ONTH

On time threshold V

- VEE at terminate ON time

T

ON

event

GATE DRIVE AND INTERNAL REGULATOR

V

CCOUT

V

CCILIM

R

OLH

R

OHH

R

OLL

R

OHL

VCC output regulation w.r.t. VEEICC = 0mA to 20mA

VCC current limit VCC = V

EE

HO output low resistance I = 50mA source

HO output high resistance I = 50mA sink

LO output low resistance I = 50mA source

LO output high resistance I = 50mA sink

= 0.5V or 1.5V

Min(Note 5) Typ(Note 6) Max(Note 5)

57 60 63 mV

15 16.67 18 V/V

10

60

0.6 1.3 2.2 mS

230 287 334 mV

6.3 6.75 7.1 V

33 53 mA

2

3

2

3

0V to V

-6V to 0V

Units

µA

µA

µA

Ω

Ω

IN

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LM3433

Symbol Parameter Conditions

R

OLP

R

OHP

DIMO output low resistance I = 5mA source

DIMO output high resistance I = 5mA sink

FUNCTIONAL CONTROL

V

INUVLO

V

CCUVLO

V

EN

R

EN

V

DIM

VIN undervoltage lockout With respect to CGND 1.4 V

VCC - VEE undervoltage lockout
thresholds

Enable threshold, with respect
to CGND

On Threshold 6.0 6.6 7.0

Off threshold 4.9 5.4 5.8

Device on w.r.t. CGND 1.6

Device off w.r.t. CGND 0.6

Enable pin pullup resistor 100

DIM logic input threshold DIM rising threshold w.r.t.

CGND

DIM falling threshold w.r.t.
CGND

R

I

I

R

DIM

ADJ

SS

SS

DIM pin pulldown resistor 100

ADJ pin current -1.0

SS pin source current

SS pin pulldown resistance EN = CGND

AC SPECIFICATIONS

T

DTD

LO and HO dead time LO falling to HO rising dead

time

HO falling to LO rising dead
time

T

PDIM

DIM to DIMO propagation
delay

DIM rising to DIMO rising delay 68 124

DIM falling to DIMO falling
delay

THERMAL SPECIFICATIONS

T

JLIM

Junction temperature thermal
limit

T

JLIM(hyst)

θ

JA

Thermal limit hysteresis 20

LLP-24 package thermal

JEDEC 4 layer board

resistance

Min(Note 5) Typ(Note 6) Max(Note 5)

20

30

1.6

0.6

10

1.0

26

28

58 160

175 °C

39 °C/W

Units

Ω

V

V

kΩ

V

kΩ

1.0 µA

µA

kΩ

ns

ns

°C

Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended
to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: The HS pin can go to -6V with respect to VEE for 30ns and +22V with respect to VEE for 50ns without sustaining damage.

Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance,

θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (T
θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal

shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=175°C (typ.) and disengages at TJ=155°C (typ).

Note 4: Human Body Model, applicable std. JESD22-A114-C. Machine Model, applicable std. JESD22-A115-A. Field Induced Charge Device Model, applicable
std. JESD22-C101-C.

Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%
production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used
to calculate Average Outgoing Quality Level (AOQL).

Note 6: Typical numbers are at 25°C and represent the most likely norm.

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J(MAX)

− TA)/