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LM3310
Step-up PWM DC/DC Converter with Integrated Op-Amp
and Gate Pulse Modulation Switch
August 2005
LM3310 Step-up PWM DC/DC Converter with Integrated Op-Amp and Gate Pulse Modulation
Switch
General Description
The LM3310 is a step-up DC/DC converter integrated with
an Operational Amplifier and a gate pulse modulation switch.
The boost (step-up) converter is used to generate an adjustable output voltage and features a low R
for maximum efficiency. The operating frequency is selectable between 660kHz and 1.28MHz allowing for the use of
small external components. An external soft-start pin enables the user to tailor the soft-start time to a specific application and limit the inrush current. The Op-Amp is capable of
sourcing/sinking 135mA of current (typical). The gate pulse
modulation switch can operate with a VGH voltage of 5V to
30V. The LM3310 is available in a low profile 24-lead LLP
package.
internal switch
DSON
Typical Application Circuit
Features
n Boost converter with a 2A, 0.18Ω switch
n Boost output voltage adjustable up to 20V
n Operating voltage range of 2.5V to 7V
n 660kHz/1.28MHz pin selectable switching frequency
n Adjustable soft-start function
n Input undervoltage protection
n Over temperature protection
n Integrated Op-Amp
n Integrated gate pulse modulation (GPM) switch
n 24-Lead LLP package
Applications
n TFT Bias Supplies
n Portable Applications
20133331
© 2005 National Semiconductor Corporation DS201333 www.national.com
Connection Diagram
LM3310
LLP-24 (Top View)
=37˚C/W
θ
JA
20133304
Ordering Information
Order Number Spec. Package
Type
LM3310SQ LLP-24 SQA24A 1000 units/reel
LM3310SQX LLP-24 SQA24A 4500 units/reel
LM3310SQ NOPB LLP-24 SQA24A 1000 units/reel
LM3310SQX NOPB LLP-24 SQA24A 4500 units/reel
NSC Package Drawing Supplied As
tape and reel
tape and reel
tape and reel
tape and reel
Pin Descriptions
Pin Name Function
1 NC Not internally connected. Leave pin open.
2 VGHM Output of GPM circuit. This output directly drives the supply for the gate driver circuits.
3 VFLK Determines when the TFT LCD is on or off. This is controlled by the timing controller in
the LCD module.
4 VDPM VDPM pin is the enable signal for the GPM block. Pulling this pin high enables the GPM
while pulling this pin low disables it. VDPM is used for timing sequence control.
5V
6AV
7 OUT Output of the Op-Amp.
8 NEG Negative input terminal of the Op-Amp.
9 POS Positive input terminal of the Op-Amp.
10 AGND Analog ground for the step-up regulator, LDO, and Op-Amp. Connect directly to DAP and
11 NC Not internally connected. Leave pin open.
12 NC Not internally connected. Leave pin open.
DD
IN
Reference input for gate pulse modulation (GPM) circuit. The voltage at VDDis used to set
the lower VGHM voltage.
Op-Amp analog power input.
PGND beneath the device.
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Pin Descriptions (Continued)
Pin Name Function
13 NC Not internally connected. Leave pin open.
14 SS Boost converter soft start pin.
15 V
16 FREQ Switching frequency select input. Connect this pin to VINfor 1.28MHz operation and
17 V
18 SW Boost power switch input. Switch connected between SW pin and PGND pin.
19 SHDN
20 FB Boost output voltage feedback input.
21 PGND Power Ground. Source connection of the step-up regulator NMOS switch and ground for
22 CE Connect capacitor from this pin to AGND.
23 RE Connect a resistor between RE and PGND.
24 VGH GPM power supply input. VGH range is 5V to 30V.
DAP Die Attach Pad. Internally connected to GND. Connect AGND and PGND pins directly to
C
IN
Boost compensation network connection. Connected to the output of the voltage error
amplifier.
AGND for 660kHz operation.
Boost converter and GPM power input.
Shutdown pin. Active low, pulling this pin low disable the LM3310.
the GPM circuit. Connect AGND and PGND directly to the DAP beneath the device.
this pad beneath the device.
Block Diagrams
LM3310
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Block Diagrams (Continued)
LM3310
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20133358
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LM3310
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
IN
SW Voltage 21V
FB Voltage V
VCVoltage (Note 2) 1.265V±0.3V
SHDN Voltage
FREQ V
AV
IN
Amplifier Inputs/Output Rail-to-Rail
VGH Voltage 31V
VGHM Voltage VGH
VFLK, VDPM, V
Voltage 7.5V
DD
CE Voltage (Note 2) 1.265 + 0.3V
7.5V
IN
7.5V
IN
12V
Power Dissipation(Note 3) Internally Limited
Lead Temperature 300˚C
Vapor Phase (60 sec.) 215˚C
Infrared (15 sec.) 220˚C
ESD Susceptibility (Note 4)
Human Body Model 2kV
Operating Conditions
Operating Junction
Temperature Range (Note 5) −40˚C to +125˚C
Storage Temperature −65˚C to +150˚C
Supply Voltage 2.5V to 7V
Maximum SW Voltage 20V
VGH Voltage Range 5V to 30V
Op-Amp Supply, AV
IN
4V to 12V
RE Voltage VGH
Maximum Junction
150˚C
Temperature
Electrical Characteristics VIN=2.5V and IL=0A
Specifications in standard type face are for TJ= 25˚C and those with boldface type apply over the full Operating Temperature Range (T
Symbol Parameter Conditions Min(Note 5) Typ(Note 6) Max(Note 5) Units
I
Q
V
FB
%V
/∆VINFeedback Voltage Line
FB
I
CL
I
B
I
SS
V
SS
V
IN
g
m
A
V
D
MAX
f
S
I
SHDN
I
L
R
DSON
Th
SHDN
UVP Undervoltage Protection
= −40˚C to +125˚C). Unless otherwise specified, VIN=2.5V and IL= 0A.
J
Quiescent Current FB = 2V (Not Switching) 690 1100
V
SHDN
=0V
0.04
0.5
8.5
660kHz Switching 2.1 2.8
1.28MHz Switching 3.1 4.0
Feedback Voltage 1.231 1.263 1.287 V
2.5V ≤ VIN≤ 7V -0.26 0.089 0.42 %/V
Regulation
Switch Current Limit (Note 7) (Note 8) 2.0 2.6 A
FB Pin Bias Current (Note 9) 27 160 nA
SS Pin Current 8.5 11 13.5 µA
SS Pin Voltage 1.20 1.24 1.28 V
Input Voltage Range 2.5 7 V
Error Amp Transconductance ∆I = 5µA 26 74 133 µmho
Error Amp Voltage Gain 69 V/V
Maximum Duty Cycle fS= 660kHz 80 91
f
= 1.28MHz 80 89
S
Switching Frequency FREQ = Ground 440 660 760 kHz
Shutdown Pin Current V
FREQ = V
SHDN
V
SHDN
IN
= 2.5V 8 13.5 µA
= 0.3V 1 2
1.0 1.28 1.5 MHz
Switch Leakage Current VSW= 20V 0.03 5 µA
Switch R
DSON
SHDN Threshold Output High, VIN= 2.5V to
ISW= 500mA 0.18 0.35 Ω
7V
Output Low, V
= 2.5V to 7V 0.4
IN
1.4
On Threshold (Switch On) 2.5 2.4
Threshold
Off Threshold (Switch Off) 2.3 2.1
µA
mA
%
V
V
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Electrical Characteristics VIN=2.5V and IL=0A (Continued)
Specifications in standard type face are for TJ= 25˚C and those with boldface type apply over the full Operating Tempera-
LM3310
ture Range (T
= −40˚C to +125˚C). Unless otherwise specified, VIN=2.5V and IL= 0A.
J
Symbol Parameter Conditions Min(Note 5) Typ(Note 6) Max(Note 5) Units
I
FREQ
FREQ Pin Current FREQ = VIN= 2.5V 2.7 13.5 µA
Electrical Characteristics VIN=2.5V and AVIN=8V
Specifications in standard type face are for TJ= 25˚C and those with boldface type apply over the full Operating Temperature Range (T
= −40˚C to +125˚C). Unless otherwise specified VIN=2.5V and AVIN= 8V.
J
Operational Amplifier
Symbol Parameter Conditions Min(Note 5) Typ(Note 6) Max(Note 5) Units
V
OS
I
B
V
Swing Buffer, RL=2kΩ,VOmin. 0.001 0.03
OUT
AV
IN
Is+ Supply Current Buffer, V
I
OUT
Input Offset Voltage Buffer configuration, VO=
/2, no load
AV
IN
Input Bias Current (POS Pin) Buffer configuration, VO=
/2, no load (Note 9)
AV
IN
Buffer, R
=2kΩ,VOmax. 7.9 7.97
L
5.7 15 mV
200 550 nA
Supply Voltage 412V
=AVIN/2, No Load 1.5 7.8 mA
O
Output Current Source 90 138 195
Sink 105 135 175
Electrical Characteristics VIN=2.5V
Specifications in standard type face are for TJ= 25˚C and those with boldface type apply over the full Operating Temperature Range (T
Gate Pulse Modulation
Symbol Parameter Conditions Min(Note 5) Typ(Note 6) Max(Note 5) Units
VFLK VFLK Voltage Levels Rising edge threshold 1.4
VDPM VDPM Voltage Levels Rising edge threshold 1.4
V
DD(TH)
I
VFLK
I
VDPM
I
VGH
R
VGH-VGHM
R
VGHM-RE
R
VGHM(OFF)
I
CE
V
CE(TH)
Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to
be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Under normal operation the V
the pin, however the V
Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T
and the ambient temperature, T
at any ambient temperature is calculated using: P
temperature, and the regulator will go into thermal shutdown.
Note 4: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin per JEDEC standard JESD22-A114.
= −40˚C to +125˚C). Unless otherwise specified VIN=2.5V.
J
Falling edge threshold 0.4
Falling edge threshold 0.4
VDDThreshold VGHM = 30V 2.8 3 3.3
VGHM = 5V 0.4 0.5 0.7
VFLK Current VFLK = 1.5V 4.8 11
VFLK = 0.3V 1.1 2.5
VDPM Current VDPM = 1.5V 4.8 11
VDPM = 0.3V 1.1 2.5
VGH Bias Current VGH = 30V, VFLK High 59 300
VGH = 30V, VFLK Low 11 35.5
VGH to VGHM Resistance 20mA Current, VGH = 30V 14 28.5
VGHM to RE Resistance 20mA Current, VGH = VGHM
= 30V
27 55
VGH Resistance VDPM is Low, VGHM = 2V 1.2 1.7 kΩ
CE Current CE = 0V 7 11 16 µA
CE Voltage Threshold 1.16 1.22 1.34 V
and CE pins may go to voltages above this value. The maximum rating is for the possibility of a voltage being applied to
and CE pins should never have a voltage directly applied to them.
C
C
(MAX), the junction-to-ambient thermal resistance, θJA,
. See the Electrical Characteristics table for the thermal resistance of various layouts. The maximum allowable power dissipation
A
(MAX) = (T
D
J(MAX)−TA
)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die
J
V
mA
V
V
V
µA
µA
µA
Ω
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Electrical Characteristics VIN=2.5V (Continued)
Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%
production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to
calculate Average Outgoing Quality Level (AOQL).
Note 6: Typical numbers are at 25˚C and represent the most likely norm.
Note 7: Duty cycle affects current limit due to ramp generator.
Note 8: Current limit at 0% duty cycle. See TYPICAL PERFORMANCE section for Switch Current Limit vs. V
Note 9: Bias current flows into pin.
IN
Typical Performance Characteristics
SHDN Pin Current vs. SHDN Pin Voltage SS Pin Current vs. Input Voltage
LM3310
20133361
FREQ Pin Current vs. Input Voltage FB Pin Current vs. Temperature
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20133362
20133364
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Typical Performance Characteristics (Continued)
LM3310
CE Pin Current vs. Input Voltage VDPM Pin Current vs. VDPM Pin Voltage
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20133365
VFLK Pin Current vs. VFLK Pin Voltage 660kHz Switching Quiescent Current vs. Input Voltage
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1.28MHz Switching Quiescent Current vs. Input Voltage 660kHz Switching Quiescent Current vs. Temperature
20133367
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20133387
20133388
Typical Performance Characteristics (Continued)
1.28MHz Switching Quiescent Current vs. Temperature 660kHz Switching Frequency vs. Temperature
LM3310
20133368
1.28MHz Switching Frequency vs. Temperature Switch Current Limit vs. Input Voltage
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Non-Switching Quiescent Current vs. Input Voltage
GPM Disabled
Non-Switching Quiescent Current vs. Input Voltage
GPM Enabled
20133389
20133319
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Typical Performance Characteristics (Continued)
LM3310
Non-Switching Quiescent Current vs. Temperature
GPM Disabled
20133373 20133374
Power NMOS R
vs. Input Voltage 660kHz Max. Duty Cycle vs. Input Voltage
DSON
Non-Switching Quiescent Current vs. Temperature
GPM Enabled
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1.28MHz Max. Duty Cycle vs. Input Voltage 660kHz Max. Duty Cycle vs. Temperature
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20133391
20133390
Typical Performance Characteristics (Continued)
1.28MHz Max. Duty Cycle vs. Temperature 1.28MHz Application Efficiency
LM3310
20133376
1.28MHz Application Efficiency VGH Pin Bias Current vs. VGH Pin Voltage
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VGH Pin Bias Current vs. VGH Pin Voltage VGH-VGHM PMOS R
vs. VGH Pin Voltage
DSON
20133382
20133377
20133378
20133379
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Typical Performance Characteristics (Continued)
LM3310
VGHM-RE PMOS R
DSON
Op-Amp Source Current vs. AV
vs. VGHM Pin Voltage VGHM OFF Resistance vs. Temperature
20133380
IN
Op-Amp Sink Current vs. AV
20133381
IN
20133396
Op-Amp Quiescent Current vs. AV
IN
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20133397
Op-Amp Offset Voltage vs. AVIN(No Load)
Typical Performance Characteristics (Continued)
Op-Amp Offset Voltage vs. Load Current 1.28MHz, 8.5V Application Boost Load Step
LM3310
V
= 8.5V, VIN= 3.3V, C
OUT
, 200mV/div, AC
1) V
OUT
, 200mA/div, DC
3) I
LOAD
OUT
= 20µF
20133351
T = 200µs/div
20133318
1.28MHz, 8.5V Application Boost Startup Waveform 1.28MHz, 8.5V Application Boost Startup Waveform
V
= 8.5V, VIN= 3.3V, C
OUT
, 2V/div, DC
1) V
SHDN
, 5V/div, DC
2) V
OUT
, 500mA/div, DC
3) I
IN
T = 200µs/div
OUT
= 20µF, R
=20Ω,CSS= 10nF
LOAD
20133352
V
= 8.5V, VIN= 3.3V, C
OUT
, 2V/div, DC
1) V
SHDN
, 5V/div, DC
2) V
OUT
, 500mA/div, DC
3) I
IN
T = 1ms/div
OUT
= 20µF, R
LOAD
20133353
=20Ω,CSS= 100nF
1.28MHz, 8.5V Application Boost Startup Waveform
V
= 8.5V, VIN= 3.3V, C
OUT
, 2V/div, DC
1) V
SHDN
, 5V/div, DC
2) V
OUT
, 1A/div, DC
3) I
IN
T = 40µs/div
OUT
= 20µF, R
=20Ω,CSS= open
LOAD
20133354
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Operation
LM3310
20133302
FIGURE 1. Simplified Boost Converter Diagram
(a) First Cycle of Operation (b) Second Cycle Of Operation
CONTINUOUS CONDUCTION MODE
The LM3310 contains a current-mode, PWM boost regulator.
A boost regulator steps the input voltage up to a higher
output voltage. In continuous conduction mode (when the
inductor current never reaches zero at steady state), the
boost regulator operates in two cycles.
In the first cycle of operation, shown in Figure 1 (a), the
transistor is closed and the diode is reverse biased. Energy
is collected in the inductor and the load current is supplied by
.
C
OUT
The second cycle is shown in Figure 1 (b). During this cycle,
the transistor is open and the diode is forward biased. The
energy stored in the inductor is transferred to the load and
output capacitor.
The ratio of these two cycles determines the output voltage.
The output voltage is defined approximately as:
where D is the duty cycle of the switch, D and D' will be
required for design calculations.
SETTING THE OUTPUT VOLTAGE (BOOST
CONVERTER)
The output voltage is set using the feedback pin and a
resistor divider connected to the output as shown in the
typical operating circuit. The feedback pin voltage is 1.263V,
so the ratio of the feedback resistors sets the output voltage
according to the following equation:
SOFT-START CAPACITOR
The LM3310 has a soft-start pin that can be used to limit the
inductor inrush current on start-up. The external SS pin is
used to tailor the soft-start for a specific application but is not
required for all applications and can be left open when not
needed. When used a current source charges the external
soft-start capacitor C
voltage, V
. The soft-start time can be estimated as:
SS
until it reaches its typical clamp
SS
T
SS=CSS*VSS/ISS
THERMAL SHUTDOWN
The LM3310 includes thermal shutdown. If the die temperature reaches 145˚C the device will shut down until it cools to
a safe temperature at which point the device will resume
operation. If the adverse condition that is heating the device
is not removed (ambient temperature too high, short circuit
conditions, etc...) the device will continue to cycle on and off
to keep the die temperature below 145˚C. The thermal shutdown has approximately 20˚C of hysteresis. When in thermal shutdown the boost regulator, Op-Amp, and GPM blocks
will all be disabled.
INPUT UNDER-VOLTAGE PROTECTION
The LM3310 includes input under-voltage protection (UVP).
The purpose of the UVP is to protect the device both during
start-up and during normal operation from trying to operate
with insufficient input voltage. During start-up using a ramping input voltage the UVP circuitry ensures that the device
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Operation (Continued)
does not begin switching until the input voltage reaches the
UVP On threshold. If the input voltage is present and the
shutdown pin is pulled high the UVP circuitry will prevent the
device from switching if the input voltage present is lower
than the UVP On threshold. During normal operation the
UVP circuitry will disable the device if the input voltage falls
below the UVP Off threshold for any reason. In this case the
device will not turn back on until the UVP On threshold
voltage is exceeded.
OPERATIONAL AMPLIFIER
Compensation:
The architecture used for the amplifier in the LM3310 requires external compensation on the output. Depending on
the equivalent resistive and capacitive distributed load of the
TFT-LCD panel, external components at the amplifier outputs may or may not be necessary. If the capacitance presented by the load is equal to or greater than an equivalent
distibutive load of 50Ω in series with 4.7nF no external
components are needed as the TFT-LCD panel will act as
compensation itself. Distributed resistive and capacitive
loads enhance stability and increase performance of the
amplifiers. If the capacitance and resistance presented by
the load is less than 50Ω in series with 4.7nF, external
components will be required as the load itself will not ensure
stability. No external compensation in this case will lead to
oscillation of the amplifier and an increase in power consumption. A good choice for compensation in this case is to
adda50Ω in series with a 4.7nF capacitor from the output of
the amplifier to ground. This allows for driving zero to infinite
capacitance loads with no oscillations, minimal overshoot,
and a higher slew rate than using a single large capacitor.
The high phase margin created by the external compensation will guarantee stability and good performance for all
conditions.
Layout and Filtering considerations:
When the power supply for the amplifiers (AV
nected to the output of the switching regulator, the output
ripple of the regulator will produce ripple at the output of the
amplifiers. This can be minimized by directly bypassing the
pin to ground with a low ESR ceramic capacitor. For
AV
IN
best noise reduction a resistor on the order of 5Ω to 20Ω
from the supply being used to the AV
pin will create and RC
IN
filter and give you a cleaner supply to the amplifier. The
bypass capacitor should be placed as close to the AV
as possible and connected directly to the AGND plane.
For best noise immunity all bias and feedback resistors
should be in the low kΩ range due to the high input impedance of the amplifier. It is good practice to use a small
capacitance at the high impedance input terminals as well to
reduce noise susceptibility. All resistors and capacitors
should be placed as close to the input pins as possible.
Special care should also be taken in routing of the PCB
traces. All traces should be as short and direct as possible.
The output pin trace must never be routed near any trace
going to the positive input. If this happens cross talk from the
output trace to the positive input trace will cause the circuit to
oscillate.
The op-amp is not a three terminal device it has 5 terminals:
positive voltage power pin, AGND, positive input, negative
input, and the output. The op-amp "routes" current from the
power input pin and AGND to the output pin. So in effect an
opamp has not two inputs but four, all of which must be kept
noise free relative to the external circuits which are being
) is con-
IN
pin
IN
driven by the op-amp. The current from the power pins goes
through the output pin and into the load and feedback loop.
The current exiting the load and feedback loops then must
have a return path back to the op-amp power supply pins.
Ideally this return path must follow the same path as the
output pin trace to the load. Any deviation that makes the
loop area larger between the output current path and the
return current path adds to the probability of noise pick up.
GATE PULSE MODULATION
The Gate Pulse Modulation (GPM) block is designed to
provide a modulated voltage to the gate driver circuitry of a
TFT LCD display. Operation is best understood by referring
to the GPM block diagram in the Block Diagrams section, the
drawing in Figure 2 and the transient waveforms in Figure 3
and Figure 4.
There are two control signals in the GPM block, VDPM and
VFLK. VDPM is the enable pin for the GPM block. If VDPM
is high, the GPM block is active and will respond to the VFLK
drive signal from the timing controller. However, if VDPM is
low, the GPM block will be disabled and both PMOS
switches P2 and P3 will be turned off. The VGHM node will
be discharged through a 1kΩ resistor and the NMOS switch
N2.
When VDPM is high, typical waveforms for the GPM block
can be seen in Figure 2. The pin VGH is typically driven by
a 2x or 3x charge pump. In most cases, the 2x or 3x charge
pump is a discrete solution driven from the SW pin and the
output of the boost switching regulator. When VFLK is high,
the PMOS switch P2 is turned on and the PMOS switch P3
is turned off. With P2 on, the VGHM pin is pulled to the same
voltage applied to the VGH pin. This provides a high gate
drive voltage, VGHM
, and can source current to the gate
MAX
drive circuitry. When VFLK is high, NMOS switch N3 is on
which discharges the capacitor CE.
20133384
FIGURE 2.
When VFLK is low, the NMOS switch N3 is turned off which
allows current to charge the C
delay, t
, given by the following equations:
DELAY
t
) 1.265V(CE+ 7pF)/I
DELAY
capacitor. This creates a
E
CE
When the voltage on CE reaches about 1.265V and the
VFLK signal is low, the PMOS switch P2 will turn off and the
PMOS switch P3 will turn on connecting resistor R3 to the
VGHM pin through P3. This will discharge the voltage at
VGHM at some rate determined by R3 creating a slope, M
as shown in Figure 2. The VGHM pin is no longer a current
source, it is now sinking current from the gate drive circuitry.
R
LM3310
,
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Operation (Continued)
As VGHM is discharged through R3, the comparator con-
LM3310
nected to the pin V
switch P3 will turn off when the following is true:
VGHM
where V
on pin V
is some voltage connected to the resistor divider
X
DD.VX
boost switching regulator. When PMOS switch P3 turns off,
VGHM will be high impedance until the VFLK pin is high
again.
Figure 3 and Figure 4 give typical transient waveforms for
the GPM block. Waveform (1) is the VGHM pin, (2) is the
VFLK and (3) is the VDPM. The output of the boost switching
regulator is operating at 8.5V and there is a 3x discrete
charge pump (~23.5V) supplying the VGH pin. In Figure 3
and Figure 4, the VGHM pin is driving a purely capacitive
load, 4.7nF. The value of resistor R1 is 15kohm, R2 is 1.1kΩ
and R3 is 750Ω. In both transient plots, there is no C
capacitor.
monitors the VGHM voltage. PMOS
DD
) 10VXR2/(R1 + R2)
MIN
is typically connected to the output of the
E
delay
20133386
FIGURE 4.
In the GPM block diagram, a signal called “Reset” is shown.
This signal is generated from the V
thermal shutdown, or the SHDN pin. If the V
under-voltage lockout,
IN
supply voltage
IN
drops below 2.3V, typically, then the GPM block will be
disabled and the VGHM pin will discharge through NMOS
switch N2 and the 1kΩ resistor. This applies also if the
junction temperature of the device exceeds 145˚C or if the
SHDN signal is low. As shown in the block diagram, both
VDPM and VFLK have internal 350kΩ pull down resistors.
This puts both VDPM and VFLK in normally “off” states.
Typical VDPM and VFLK pin currents can be found in the
Typical Performance Characteristics section.
FIGURE 3.
INTRODUCTION TO COMPENSATION (BOOST
CONVERTER)
20133385
20133305
FIGURE 5. (a) Inductor current. (b) Diode current.
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Operation (Continued)
The LM3310 is a current mode PWM boost converter. The
signal flow of this control scheme has two feedback loops,
one that senses switch current and one that senses output
voltage.
To keep a current programmed control converter stable
above duty cycles of 50%, the inductor must meet certain
criteria. The inductor, along with input and output voltage,
will determine the slope of the current through the inductor
(see Figure 5 (a)). If the slope of the inductor current is too
great, the circuit will be unstable above duty cycles of 50%.
A 10µH inductor is recommended for most 660 kHz applications, while a 4.7µH inductor may be used for most 1.28 MHz
applications. If the duty cycle is approaching the maximum of
85%, it may be necessary to increase the inductance by as
much as 2X. See Inductor and Diode Selection for more
detailed inductor sizing.
The LM3310 provides a compensation pin (V
the voltage loop feedback. It is recommended that a series
combination of R
and CCbe used for the compensation
C
network, as shown in the typical application circuit. For any
given application, there exists a unique combination of R
and CCthat will optimize the performance of the LM3310
circuit in terms of its transient response. The series combination of R
and CCintroduces a pole-zero pair according to
C
the following equations:
) to customize
C
LM3310
where fs is the switching frequency, D is the duty cycle, and
is the ON resistance of the internal switch taken from
R
DSON
the graph "R
acteristics section. This equation is only good for duty cycles
greater than 50% (D
recommended values may be used. The value given by this
equation is the inductance necessary to supress subharmonic oscillations. In some cases the value given by this
equation may be too small for a given application. In this
case the average inductor current and the inductor current
ripple must be considered.
The corresponding inductor current ripple, average inductor
current, and peak inductor current as shown in Figure 5 (a) is
given by:
C
vs. VIN"intheTypical Performance Char-
DSON
>
0.5), for duty cycles less than 50% the
where ROis the output impedance of the error amplifier,
approximately 900kΩ. For most applications, performance
can be optimized by choosing values within the range 5kΩ≤
≤ 100kΩ (RCcan be up to 200kΩ if CC2is used, see High
R
C
Output Capacitor ESR Compensation) and 68pF ≤ C
C
4.7nF. Refer to the Applications Information section for recommended values for specific circuits and conditions. Refer
to the Compensation section for other design requirement.
COMPENSATION
This section will present a general design procedure to help
insure a stable and operational circuit. The designs in this
datasheet are optimized for particular requirements. If different conversions are required, some of the components may
need to be changed to ensure stability. Below is a set of
general guidelines in designing a stable circuit for continuous conduction operation, in most all cases this will provide
for stability during discontinuous operation as well. The
power components and their effects will be determined first,
then the compensation components will be chosen to produce stability.
INDUCTOR AND DIODE SELECTION
Although the inductor sizes mentioned earlier are fine for
most applications, a more exact value can be calculated. To
ensure stability at duty cycles above 50%, the inductor must
have some minimum value determined by the minimum
input voltage and the maximum output voltage. This equation is:
Continuous conduction mode occurs when ∆iLis less than
the average inductor current and discontinuous conduction
mode occurs when ∆i
is greater than the average inductor
L
current. Care must be taken to make sure that the switch will
not reach its current limit during normal operation. The inductor must also be sized accordingly. It should have a
saturation current rating higher than the peak inductor current expected. The output voltage ripple is also affected by
≤
the total ripple current.
The output diode for a boost regulator must be chosen
correctly depending on the output voltage and the output
current. The typical current waveform for the diode in continuous conduction mode is shown in Figure 5 (b). The diode
must be rated for a reverse voltage equal to or greater than
the output voltage used. The average current rating must be
greater than the maximum load current expected, and the
peak current rating must be greater than the peak inductor
current. During short circuit testing, or if short circuit conditions are possible in the application, the diode current rating
must exceed the switch current limit. Using Schottky diodes
with lower forward voltage drop will decrease power dissipation and increase efficiency.
DC GAIN AND OPEN-LOOP GAIN
Since the control stage of the converter forms a complete
feedback loop with the power components, it forms a closedloop system that must be stabilized to avoid positive feedback and instability. A value for open-loop DC gain will be
required, from which you can calculate, or place, poles and
zeros to determine the crossover frequency and the phase
margin. A high phase margin (greater than 45˚) is desired for
the best stability and transient response. For the purpose of
stabilizing the LM3310, choosing a crossover point well below where the right half plane zero is located will ensure
sufficient phase margin.
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Operation (Continued)
To ensure a bandwidth of
LM3310
RHP zero, calculate the open-loop DC gain, A
value is known, you can calculate the crossover visually by
placing a −20dB/decade slope at each pole, and a +20dB/
decade slope for each zero. The point at which the gain plot
crosses unity gain, or 0dB, is the crossover frequency. If the
crossover frequency is less than
margin should be high enough for stability. The phase margin can also be improved by adding C
this section. The equation for A
tional equations required for the calculation:
where RLis the minimum load resistance, VINis the minimum input voltage, g
tance found in the Electrical Characteristics table, and R
is the value chosen from the graph "NMOS R
SON
Input Voltage" in the Typical Performance Characteristics
section.
1
⁄2or less of the frequency of the
1
⁄2the RHP zero, the phase
as discussed later in
C2
is given below with addi-
DC
mc ) 0.072fs (in V/s)
is the error amplifier transconduc-
m
. After this
DC
DSON
vs.
ESR is also important because it determines the peak to
peak output voltage ripple according to the approximate
equation:
∆V
OUT
) 2∆iLR
ESR
(in Volts)
A minimum value of 10µF is recommended and may be
increased to a larger value. After choosing the output capacitor you can determine a pole-zero pair introduced into the
control loop by the following equations:
Where RLis the minimum load resistance corresponding to
the maximum load current. The zero created by the ESR of
the output capacitor is generally very high frequency if the
ESR is small. If low ESR capacitors are used it can be
neglected. If higher ESR capacitors are used see the High
Output Capacitor ESR Compensation section. Some suitable capacitor vendors include Vishay, Taiyo-Yuden, and
TDK.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right
half plane zero (RHP zero). This zero has the effect of a zero
in the gain plot, causing an imposed +20dB/decade on the
rolloff, but has the effect of a pole in the phase, subtracting
another 90˚ in the phase plot. This can cause undesirable
effects if the control loop is influenced by this zero. To ensure
the RHP zero does not cause instability issues, the control
loop should be designed to have a bandwidth of less than
1
⁄
2
the frequency of the RHP zero. This zero occurs at a fre-
-
D
quency of:
INPUT AND OUTPUT CAPACITOR SELECTION
The switching action of a boost regulator causes a triangular
voltage waveform at the input. A capacitor is required to
reduce the input ripple and noise for proper operation of the
regulator. The size used is dependant on the application and
board layout. If the regulator will be loaded uniformly, with
very little load changes, and at lower current outputs, the
input capacitor size can often be reduced. The size can also
be reduced if the input of the regulator is very close to the
source output. The size will generally need to be larger for
applications where the regulator is supplying nearly the
maximum rated output or if large load steps are expected. A
minimum value of 10µF should be used for the less stressful
condtions while a 22µF to 47µF capacitor may be required
for higher power and dynamic loads. Larger values and/or
lower ESR may be needed if the application requires very
low ripple on the input source voltage.
The choice of output capacitors is also somewhat arbitrary
and depends on the design requirements for output voltage
ripple. It is recommended that low ESR (Equivalent Series
Resistance, denoted R
) capacitors be used such as
ESR
ceramic, polymer electrolytic, or low ESR tantalum. Higher
ESR capacitors may be used but will require more compensation which will be explained later on in the section. The
www.national.com 18
where I
is the maximum load current.
LOAD
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components R
and CCis to set a dominant low frequency pole in the control
loop. Simply choose values for R
and CCwithin the ranges
C
given in the Introduction to Compensation section to set this
pole in the area of 10Hz to 500Hz. The frequency of the pole
created is determined by the equation:
where ROis the output impedance of the error amplifier,
approximately 900kΩ. Since R
, it does not have much effect on the above equation and
R
O
can be neglected until a value is chosen to set the zero f
is created to cancel out the pole created by the output
f
ZC
capacitor, f
. The output capacitor pole will shift with differ-
P1
is generally much less than
C
ZC
ent load currents as shown by the equation, so setting the
zero is not exact. Determine the range of f
pected loads and then set the zero f
ZC
over the ex-
P1
to a point approximately in the middle. The frequency of this zero is determined by:
C
.
Operation (Continued)
Now RCcan be chosen with the selected value for CC.
Check to make sure that the pole f
500Hz range, change each value slightly if needed to ensure
both component values are in the recommended range.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or
just to improve the overall phase margin of the control loop,
another pole may be introduced to cancel the zero created
by the ESR. This is accomplished by adding another capaci-
, directly from the compensation pin VCto ground, in
tor, C
C2
parallel with the series combination of R
should be placed at the same frequency as f
zero. The equation for this pole follows:
To ensure this equation is valid, and that CC2can be used
without negatively impacting the effects of R
must be greater than 10fZC.
CHECKING THE DESIGN
With all the poles and zeros calculated the crossover frequency can be checked as described in the section DC Gain
and Open-loop Gain. The compensation values can be
changed a little more to optimize performance if desired.
This is best done in the lab on a bench, checking the load
step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of R
should be chosen. This will improve the overall bandwidth
which makes the regulator respond more quickly to tran-
is still in the 10Hz to
PC
and CC. The pole
C
, the ESR
Z1
and CC,f
C
PC2
LM3310
sients. If more detail is required, or the most optimum performance is desired, refer to a more in depth discussion of
compensating current mode DC/DC switching regulators.
POWER DISSIPATION
The output power of the LM3310 is limited by its maximum
power dissipation. The maximum power dissipation is determined by the formula
P
=(T
D
jmax-TA
where T
(125˚C), T
is the maximum specified junction temperature
jmax
is the ambient temperature, and θJAis the ther-
A
mal resistance of the package.
LAYOUT CONSIDERATIONS
The input bypass capacitor C
operating circuit, must be placed close to the IC. This will
reduce copper trace resistance which effects input voltage
ripple of the IC. For additional input voltage filtering, a 100nF
bypass capacitor can be placed in parallel with C
pin, to shunt any high frequency noise to ground. The
the V
IN
output capacitor, C
, should also be placed close to the
OUT
IC. Any copper trace connections for the C
increase the series resistance, which directly effects output
voltage ripple. The feedback network, resistors R
, should be kept close to the FB pin, and away from the
R
FB2
inductor, to minimize copper trace connections that can inject noise into the system. R
the RE and CE pins to minimize noise in the GPM circuitry.
Trace connections made to the inductor and schottky diode
should be minimized to reduce power dissipation and increase overall efficiency. For more detail on switching power
supply layout considerations see Application Note AN-1149:
Layout Guidelines for Switching Power Supplies.
For Op-Amp layout please refer to the Operational Amplifier
section.
Figure 6, Figure 7, and Figure 8 in the Application Informa-
C
tion section following show the schematic and an example of
a good layout as used in the LM3310/11 evaluation board.
)/θ
JA
, as shown in the typical
IN
, close to
IN
capacitor can
OUT
FB1
and CEshould also be close to
E
and
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Application Information
LM3310
FIGURE 6. Evaluation Board Schematic
20133323
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Application Information (Continued)
LM3310
FIGURE 7. Evaluation Board Layout (top layer)
20133324
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Application Information (Continued)
LM3310
FIGURE 8. Evaluation Board Layout (bottom layer)
20133325
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Application Information (Continued)
LM3310
FIGURE 9. Li-Ion to 8V, 1.28MHz Application
20133329
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Application Information (Continued)
LM3310
FIGURE 10. 5V to 10.5V, 1.28MHz Application
Some recommended Inductors (others may be used)
Manufacturer Inductor Contact Information
Coilcraft DO3316 and DT3316 series www.coilcraft.com
800-3222645
TDK SLF10145 series www.component.tdk.com
847-803-6100
Pulse P0751 and P0762 series www.pulseeng.com
Sumida CDRH8D28 and CDRH8D43 series www.sumida.com
Some recommended Input and Output Capacitors (others may be used)
Manufacturer Capacitor Contact Information
Vishay Sprague 293D, 592D, and 595D series tantalum www.vishay.com
407-324-4140
Taiyo Yuden High capacitance MLCC ceramic www.t-yuden.com
408-573-4150
Cornell Dubilier
Panasonic
ESRD seriec Polymer Aluminum Electrolytic
SPV and AFK series V-chip series
High capacitance MLCC ceramic
EEJ-L series tantalum
www.cde.com
www.panasonic.com
20133330
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Physical Dimensions inches (millimeters) unless otherwise noted
LM3310 Step-up PWM DC/DC Converter with Integrated Op-Amp and Gate Pulse Modulation
Switch
LLP-24 Pin Package (SQA)
For Ordering, Refer to Ordering Information Table
NS Package Number SQA24A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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