National Semiconductor LM3224 Technical data

LM3224
615kHz/1.25MHz Step-up PWM DC/DC Converter

LM3224 615kHz/1.25MHz Step-up PWM DC/DC Converter

December 2004

General Description

The LM3224 is a step-up DC/DC converter with a 0.15Ω
(typ.), 2.45A (typ.) internal switch and pin selectable operat­ing frequency. With the ability to convert 3.3V to multiple
outputs of 8V, -8V, and 23V, the LM3224 is an ideal part for
biasing TFT displays. With the high current switch it is also
ideal for driving high current white LEDs for flash applica­tions. The LM3224 can be operated at switching frequencies
of 615kHz and 1.25MHz allowing for easy filtering and low
noise. An external compensation pin gives the user flexibility
in setting frequency compensation, which makes possible
the use of small, low ESR ceramic capacitors at the output.
An external soft-start pin allows the user to control the
amount of inrush current during start up. The LM3224 is
available in a low profile 8-lead MSOP package.

Typical Application Circuit

Features

n Operating voltage range of 2.7V to 7V
n 615kHz/1.25MHz pin selectable frequency operation
n Over temperature protection
n Optional soft-start function
n 8-Lead MSOP package

Applications

n TFT Bias Supplies
n Handheld Devices
n Portable Applications
n GSM/CDMA Phones
n Digital Cameras
n White LED Flash/Torch Applications

20097631

© 2004 National Semiconductor Corporation DS200976 www.national.com

Connection Diagram

LM3224

Top View

8-Lead Plastic MSOP

NS Package Number MUA08A

20097604

Ordering Information

Order Number Spec. Package

Type

LM3224MM-ADJ MSOP-8 MUA08A 1000 Units, Tape and

LM3224MMX-ADJ MSOP-8 MUA08A 3500 Units, Tape and

LM3224MM-ADJ NOPB MSOP-8 MUA08A 1000 Units, Tape and

LM3224MMX-ADJ NOPB MSOP-8 MUA08A 3500 Units, Tape and

NSC Package

Drawing

Supplied As Package Top Mark

Reel

Reel

Reel

Reel

Pin Description

Pin Name Function

1V

2 FB Output voltage feedback input.

3 SHDN

4 GND Analog and power ground.

5 SW Power switch input. Switch connected between SW pin and GND pin.

6V

7 FSLCT Switching frequency select input. V

8 SS Soft-start Pin.

C

IN

Compensation network connection. Connected to the output of the voltage error amplifier.

Shutdown control input, active low. This pin has an internal pulldown resistor so the
default condition is off. The pin must be pulled high to turn on the device.

Analog power input.

= 1.25MHz. Ground = 615kHz.

IN

SEKB

SEKB

SEKB

SEKB

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Block Diagram

LM3224

General Description

The LM3224 utilizes a PWM control scheme to regulate the
output voltage over all load conditions. The operation can
best be understood referring to the block diagram and Figure
1 of the Operation section. At the start of each cycle, the
oscillator sets the driver logic and turns on the NMOS power
device conducting current through the inductor, cycle 1 of
Figure 1 (a). During this cycle, the voltage at the V
controls the peak inductor current. The V

voltage will in-

C

crease with larger loads and decrease with smaller. This
voltage is compared with the summation of the SW voltage
and the ramp compensation. The ramp compensation is
used in PWM architectures to eliminate the sub-harmonic
oscillations that occur during duty cycles greater than 50%.
Once the summation of the ramp compensation and switch
voltage equals the V

voltage, the PWM comparator resets

C

the driver logic turning off the NMOS power device. The

pin

C

20097603

inductor current then flows through the schottky diode to the
load and output capacitor, cycle 2 of Figure 1 (b). The NMOS
power device is then set by the oscillator at the end of the
period and current flows through the NMOS power device
once again.

The LM3224 has dedicated protection circuitry running dur­ing normal operation to protect the IC. The Thermal Shut­down circuitry turns off the NMOS power device when the
die temperature reaches excessive levels. The UVP com­parator protects the NMOS power device during supply
power startup and shutdown to prevent operation at voltages
less than the minimum input voltage. The OVP comparator is
used to prevent the output voltage from rising at no loads
allowing full PWM operation over all load conditions. The
LM3224 also features a shutdown mode decreasing the
supply current to 0.1µA (typ.).

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

LM3224

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

V

IN

SW Voltage 21V

7.5V

Vapor Phase (60 sec.) 215˚C

Infrared (15 sec.) 220˚C

ESD Susceptibility
(Note 5)

Human Body Model 2kV

Machine Model 200V

FB Voltage (Note 2) 7V

V

Voltage (Note 3) 1.26V±0.3V

C

SHDN Voltage

7.5V

FSLCT 7.5V

Maximum Junction

150˚C

Temperature

Power Dissipation(Note 4) Internally Limited

Lead Temperature 300˚C

Operating Conditions

Operating Junction
Temperature Range (Note 6) −40˚C to +125˚C

Storage Temperature −65˚C to +150˚C

Supply Voltage 2.7V to 7V

Maximum Output Voltage 20V

Electrical Characteristics

Specifications in standard type face are for TJ= 25˚C and those with boldface type apply over the full Operating Tempera­ture Range (T

Symbol Parameter Conditions

I

Q

V

FB

I

(Note 8) Switch Current Limit VIN= 2.7V (Note 9) 2.45

CL

%V

/∆VINFeedback Voltage Line

FB

I

B

I

SS

V

SS

V

IN

g

m

A

V

D

MAX

f

S

I

SHDN

I

L

R

DSON

Th

SHDN

UVP On Threshold 2.3 2.5 V

Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to
be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: The FB pin should never exceed V

Note 3: Under normal operation the V

however the V

Note 4: The maximum allowable power dissipation is a function of the maximum junction temperature, T
and the ambient temperature, T
Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.

= −40˚C to +125˚C). VIN= 2.7V, FSLCT = SHDN = VIN, and IL= 0A, unless otherwise specified.

J

Min

(Note 6)

Typ

(Note 7)

Max

(Note 6)

Quiescent Current FB = 2V (Not Switching) 1.3 2.0 mA

V

= 0V 0.1 2.0 µA

SHDN

Feedback Voltage 1.2285 1.26 1.2915 V

Regulation

FB Pin Bias Current (Note

10)

= 3V, V

IN

V

= 3V, V

IN

2.7V ≤ VIN≤ 7V

= 8V 2.1

OUT

= 5V 2.2

OUT

0.085 0.15 %/V

35 250 nA

SS Pin Current 7.5 11 13 µA

SS Pin Voltage 1.2090 1.2430 1.2622

Input Voltage Range 2.7 7 V

Error Amp Transconductance ∆I = 5µA 40 87 135 µmho

Error Amp Voltage Gain 78 V/V

Maximum Duty Cycle 85 92.5 %

Switching Frequency FSLCT = Ground 450 615 750 kHz

Shutdown Pin Current V

FSLCT = V

SHDN

V

SHDN

IN

= 2.7V 2.4 5.0 µA

= 0.3V 0.3 1.2

0.9 1.25 1.5 MHz

Switch Leakage Current VSW= 20V 0.2 8.0 µA

Switch R

DSON

VIN= 2.7V, ISW= 1A 0.15 0.4 Ω

Shutdown Threshold Output High 1.2 0.8 V

Output Low 0.8 0.3 V

Off Threshold 2.6 2.7 V

.

IN

pin may go to voltages above this value. This maximum rating is for the possibility of a voltage being applied to the pin,

pin should never have a voltage directly applied to it.

C

C

(MAX), the junction-to-ambient thermal resistance, θJA,

. The maximum allowable power dissipation at any ambient temperature is calculated using: PD(MAX) = (T

A

J

J(MAX)−TA

Units

AV

)/θJA.

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Electrical Characteristics (Continued)

Note 5: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged

directly into each pin.

Note 6: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%
production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to
calculate Average Outgoing Quality Level (AOQL).

Note 7: Typical numbers are at 25˚C and represent the most likely norm.

Note 8: Duty cycle affects current limit due to ramp generator.

Note 9: Current limit at 0% duty cycle. See TYPICAL PERFORMANCE section for Switch Current Limit vs. V

Note 10: Bias current flows into FB pin.

IN

Typical Performance Characteristics

SHDN Pin Current vs. SHDN Pin Voltage SS Pin Current vs. Temperature

LM3224

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FSLCT Pin Current vs. FSLCT Pin Voltage FB Pin Current vs. Temperature

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20097619

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Typical Performance Characteristics (Continued)

LM3224

NMOS R

vs. Input Voltage 615kHz Non-switching IQvs. Input Voltage

DSON

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1.25MHz Non-switching IQvs. Input Voltage 615kHz Switching IQvs. Input Voltage

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1.25MHz Switching IQvs. Input Voltage 615kHz Switching IQvs. Temperature

20097624 20097625

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Typical Performance Characteristics (Continued)

LM3224

1.25MHz Switching I

vs. Temperature 615kHz Switching Frequency vs. Temperature

Q

20097626

20097627

1.25MHz Switching Frequency vs. Temperature 615kHz Maximum Duty Cycle vs. Temperature

20097628

1.25MHz Maximum Duty Cycle vs. Temperature Switch Current Limit vs. V

20097651

20097629

IN

20097660

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Typical Performance Characteristics (Continued)

LM3224

Switch Current Limit vs. Temperature Switch Current Limit vs. Temperature

20097652

20097662

1.25MHz Efficiency vs. Load Current

20097653

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Operation

LM3224

20097602

FIGURE 1. Simplified Boost Converter Diagram

(a) First Cycle of Operation (b) Second Cycle Of Operation

CONTINUOUS CONDUCTION MODE

The LM3224 is a current-mode, PWM boost regulator. A
boost regulator steps the input voltage up to a higher output
voltage. In continuous conduction mode (when the inductor
current never reaches zero at steady state), the boost regu­lator operates in two cycles.

In the first cycle of operation, shown in Figure 1 (a), the
transistor is closed and the diode is reverse biased. Energy
is collected in the inductor and the load current is supplied by

.

C

OUT

The second cycle is shown in Figure 1 (b). During this cycle,
the transistor is open and the diode is forward biased. The
energy stored in the inductor is transferred to the load and
output capacitor.

The ratio of these two cycles determines the output voltage.
The output voltage is defined approximately as:

where D is the duty cycle of the switch, D and D' will be
required for design calculations.

SETTING THE OUTPUT VOLTAGE

The output voltage is set using the feedback pin and a
resistor divider connected to the output as shown in the
typical operating circuit. The feedback pin voltage is 1.26V,
so the ratio of the feedback resistors sets the output voltage
according to the following equation:

SOFT-START CAPACITOR

The LM3224 has a soft-start pin that can be used to limit the
inductor inrush current on start-up. The external SS pin is
used to tailor the soft-start for a specific application but is not
required for all applications and can be left open when not
needed. When used, a current source charges the external
soft-start capacitor, Css. The soft-start time can be estimated
as:

Tss = Css*1.24V/Iss

THERMAL SHUTDOWN

The LM3224 includes thermal shutdown protection. If the die
temperature exceeds 140˚C the regulator will shut off the
power switch, significantly reducing power dissipation in the
device. The switch will remain off until the die temperature is
reduced to approximately 120˚C. If the cause of the excess
heating is not removed (excessive ambient temperature,
excessive power dissipation, or both) the device will con­tinue to cycle on and off in this manner to protect from
damage.

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Operation (Continued)

INTRODUCTION TO COMPENSATION

LM3224

FIGURE 2. (a) Inductor current. (b) Diode current.

20097605

Output Capacitor ESR Compensation) and 680pF ≤ C

C

10nF. Refer to the Applications Information section for rec­ommended values for specific circuits and conditions. Refer
to the Compensation section for other design requirement.

COMPENSATION

This section will present a general design procedure to help
insure a stable and operational circuit. The designs in this
datasheet are optimized for particular requirements. If differ­ent conversions are required, some of the components may
need to be changed to ensure stability. Below is a set of
general guidelines in designing a stable circuit for continu­ous conduction operation, in most all cases this will provide
for stability during discontinuous operation as well. The
power components and their effects will be determined first,
then the compensation components will be chosen to pro­duce stability.

INDUCTOR AND DIODE SELECTION

Although the inductor sizes mentioned earlier are fine for
most applications, a more exact value can be calculated. To
ensure stability at duty cycles above 50%, the inductor must
have some minimum value determined by the minimum
input voltage and the maximum output voltage. This equa­tion is:

≤

The LM3224 is a current mode PWM boost converter. The
signal flow of this control scheme has two feedback loops,
one that senses switch current and one that senses output
voltage.

To keep a current programmed control converter stable
above duty cycles of 50%, the inductor must meet certain
criteria. The inductor, along with input and output voltage,
will determine the slope of the current through the inductor
(see Figure 2 (a)). If the slope of the inductor current is too
great, the circuit will be unstable above duty cycles of 50%.
A 10µH to 15µH inductor is recommended for most 615 kHz
applications, while a 4.7µH to 10µH inductor may be used for
most 1.25 MHz applications. If the duty cycle is approaching
the maximum of 85%, it may be necessary to increase the
inductance by as much as 2X. See Inductor and Diode
Selection for more detailed inductor sizing.

The LM3224 provides a compensation pin (V

) to customize

C

the voltage loop feedback. It is recommended that a series
combination of R

and CCbe used for the compensation

C

network, as shown in the typical application circuit. For any
given application, there exists a unique combination of R
and CCthat will optimize the performance of the LM3224
circuit in terms of its transient response. The series combi­nation of R

and CCintroduces a pole-zero pair according to

C

the following equations:

where ROis the output impedance of the error amplifier,
approximately 900kΩ. For most applications, performance
can be optimized by choosing values within the range 5kΩ≤

≤ 100kΩ (RCcan be up to 200kΩ if CC2is used, see High

R

C

where fs is the switching frequency, D is the duty cycle, and

is the ON resistance of the internal switch taken from

R

DSON

the graph "NMOS R

vs. Input Voltage" in the Typical

DSON

Performance Characteristics section. This equation is only

>

good for duty cycles greater than 50% (D

0.5), for duty
cycles less than 50% the recommended values may be
used. The corresponding inductor current ripple as shown in
Figure 2 (a) is given by:

The inductor ripple current is important for a few reasons.
One reason is because the peak switch current will be the
average inductor current (input current or I

/D’) plus ∆iL.

LOAD

As a side note, discontinuous operation occurs when the
inductor current falls to zero during a switching cycle, or ∆i

L

is greater than the average inductor current. Therefore, con-

C

tinuous conduction mode occurs when ∆i

is less than the

L

average inductor current. Care must be taken to make sure
that the switch will not reach its current limit during normal
operation. The inductor must also be sized accordingly. It
should have a saturation current rating higher than the peak
inductor current expected. The output voltage ripple is also
affected by the total ripple current.

The output diode for a boost regulator must be chosen
correctly depending on the output voltage and the output
current. The typical current waveform for the diode in con­tinuous conduction mode is shown in Figure 2 (b). The diode
must be rated for a reverse voltage equal to or greater than
the output voltage used. The average current rating must be
greater than the maximum load current expected, and the
peak current rating must be greater than the peak inductor
current. During short circuit testing, or if short circuit condi­tions are possible in the application, the diode current rating

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Operation (Continued)

must exceed the switch current limit. Using Schottky diodes
with lower forward voltage drop will decrease power dissipa­tion and increase efficiency.

DC GAIN AND OPEN-LOOP GAIN

Since the control stage of the converter forms a complete
feedback loop with the power components, it forms a closed­loop system that must be stabilized to avoid positive feed­back and instability. A value for open-loop DC gain will be
required, from which you can calculate, or place, poles and
zeros to determine the crossover frequency and the phase
margin. A high phase margin (greater than 45˚) is desired for
the best stability and transient response. For the purpose of
stabilizing the LM3224, choosing a crossover point well be­low where the right half plane zero is located will ensure
sufficient phase margin.

1

To ensure a bandwidth of
RHP zero, calculate the open-loop DC gain, A
value is known, you can calculate the crossover visually by
placing a −20dB/decade slope at each pole, and a +20dB/
decade slope for each zero. The point at which the gain plot
crosses unity gain, or 0dB, is the crossover frequency. If the
crossover frequency is less than
margin should be high enough for stability. The phase mar­gin can also be improved by adding C
this section. The equation for A
tional equations required for the calculation:

⁄2or less of the frequency of the

. After this

DC

1

⁄2the RHP zero, the phase

as discussed later in

C2

is given below with addi-

DC

source output. The size will generally need to be larger for
applications where the regulator is supplying nearly the
maximum rated output or if large load steps are expected. A
minimum value of 10µF should be used for the less stressful
condtions while a 22µF to 47µF capacitor may be required
for higher power and dynamic loads. Larger values and/or
lower ESR may be needed if the application requires very
low ripple on the input source voltage.

The choice of output capacitors is also somewhat arbitrary
and depends on the design requirements for output voltage
ripple. It is recommended that low ESR (Equivalent Series
Resistance, denoted R

) capacitors be used such as

ESR

ceramic, polymer electrolytic, or low ESR tantalum. Higher
ESR capacitors may be used but will require more compen­sation which will be explained later on in the section. The
ESR is also important because it determines the peak to
peak output voltage ripple according to the approximate
equation:

∆V

OUT

) 2∆iLR

ESR

(in Volts)

A minimum value of 10µF is recommended and may be
increased to a larger value. After choosing the output capaci­tor you can determine a pole-zero pair introduced into the
control loop by the following equations:

LM3224

mc ) 0.072fs (in V/s)

where RLis the minimum load resistance, VINis the mini­mum input voltage, g

is the error amplifier transconduc-

m

tance found in the Electrical Characteristics table, and R

is the value chosen from the graph "NMOS R

SON

DSON

vs.
Input Voltage" in the Typical Performance Characteristics
section.

INPUT AND OUTPUT CAPACITOR SELECTION

The switching action of a boost regulator causes a triangular
voltage waveform at the input. A capacitor is required to
reduce the input ripple and noise for proper operation of the
regulator. The size used is dependant on the application and
board layout. If the regulator will be loaded uniformly, with
very little load changes, and at lower current outputs, the
input capacitor size can often be reduced. The size can also
be reduced if the input of the regulator is very close to the

Where RLis the minimum load resistance corresponding to
the maximum load current. The zero created by the ESR of
the output capacitor is generally very high frequency if the
ESR is small. If low ESR capacitors are used it can be
neglected. If higher ESR capacitors are used see the High
Output Capacitor ESR Compensation section. Some suit­able capacitor vendors include Vishay, Taiyo-Yuden, and
TDK.

RIGHT HALF PLANE ZERO

A current mode control boost regulator has an inherent right
half plane zero (RHP zero). This zero has the effect of a zero
in the gain plot, causing an imposed +20dB/decade on the
rolloff, but has the effect of a pole in the phase, subtracting
another 90˚ in the phase plot. This can cause undesirable
effects if the control loop is influenced by this zero. To ensure
the RHP zero does not cause instability issues, the control
loop should be designed to have a bandwidth of less than

1

⁄

2

the frequency of the RHP zero. This zero occurs at a fre­quency of:

-

D

where I

is the maximum load current.

LOAD

SELECTING THE COMPENSATION COMPONENTS

The first step in selecting the compensation components R

C

and CCis to set a dominant low frequency pole in the control
loop. Simply choose values for R

and CCwithin the ranges

C

given in the Introduction to Compensation section to set this
pole in the area of 10Hz to 500Hz. The frequency of the pole
created is determined by the equation:

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Operation (Continued)

LM3224

where ROis the output impedance of the error amplifier,
approximately 900kΩ. Since R

, it does not have much effect on the above equation and

R

O

can be neglected until a value is chosen to set the zero f

is created to cancel out the pole created by the output

f

ZC

capacitor, f

. The output capacitor pole will shift with differ-

P1

ent load currents as shown by the equation, so setting the
zero is not exact. Determine the range of f
pected loads and then set the zero f
mately in the middle. The frequency of this zero is deter­mined by:

Now RCcan be chosen with the selected value for CC.
Check to make sure that the pole f
500Hz range, change each value slightly if needed to ensure
both component values are in the recommended range.

HIGH OUTPUT CAPACITOR ESR COMPENSATION

When using an output capacitor with a high ESR value, or
just to improve the overall phase margin of the control loop,
another pole may be introduced to cancel the zero created
by the ESR. This is accomplished by adding another capaci-

, directly from the compensation pin VCto ground, in

tor, C

C2

parallel with the series combination of R
should be placed at the same frequency as f
zero. The equation for this pole follows:

To ensure this equation is valid, and that CC2can be used
without negatively impacting the effects of R
must be greater than 10fZC.

is generally much less than

C

P1

to a point approxi-

ZC

is still in the 10Hz to

PC

and CC. The pole

C

C

ZC

over the ex-

, the ESR

Z1

and CC,f

PC2

changed a little more to optimize performance if desired.
This is best done in the lab on a bench, checking the load
step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of R

C

should be chosen. This will improve the overall bandwidth
which makes the regulator respond more quickly to tran­sients. If more detail is required, or the most optimum per-

.

formance is desired, refer to a more in depth discussion of
compensating current mode DC/DC switching regulators.

POWER DISSIPATION

The output power of the LM3224 is limited by its maximum
power dissipation. The maximum power dissipation is deter­mined by the formula

where T

jmax

(125˚C), T

=(T

P

D

jmax-TA

is the maximum specidfied junction temperature

is the ambient temperature, and θJAis the ther-

A

)/θ

JA

mal resistance of the package.

LAYOUT CONSIDERATIONS

The input bypass capacitor C

, as shown in the typical

IN

operating circuit, must be placed close to the IC. This will
reduce copper trace resistance which effects input voltage
ripple of the IC. For additional input voltage filtering, a 100nF
bypass capacitor can be placed in parallel with C

pin, to shunt any high frequency noise to ground. The

the V

IN

output capacitor, C
IC. Any copper trace connections for the C

, should also be placed close to the

OUT

OUT

, close to

IN

capacitor can
increase the series resistance, which directly effects output
voltage ripple. The feedback network, resistors R

, should be kept close to the FB pin, and away from the

R

FB2

FB1

and

inductor, to minimize copper trace connections that can in­ject noise into the system. Trace connections made to the
inductor and schottky diode should be minimized to reduce
power dissipation and increase overall efficiency. For more
detail on switching power supply layout considerations see
Application Note AN-1149: Layout Guidelines for Switching
Power Supplies.

CHECKING THE DESIGN

With all the poles and zeros calculated the crossover fre­quency can be checked as described in the section DC Gain
and Open-loop Gain. The compensation values can be

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Application Information

LM3224

FIGURE 3. Triple Output TFT Bias (615 kHz operation)

TRIPLE OUTPUT TFT BIAS

The circuit in Figure 3 shows how the LM3224 can be
configured to provide outputs of 8V, −8V, and 23V, conve­nient for biasing TFT displays. The 8V output is regulated,
while the −8V and 23V outputs are unregulated.

The 8V output is generated by a typical boost topology. The
basic operation of the boost converter is described in the
OPERATION section. The output voltage is set with R
and R

FB2

by:

FB1

The compensation network of RCand CCare chosen to
optimally stabilize the converter. The inductor also affects
the stability. When operating at 615 kHz, a 10uH inductor is
recommended to insure the converter is stable at duty cycles
greater than 50%. Refer to the COMPENSATION section for
more information.

The -8V output is derived from a diode inverter. During the
second cycle, when the transistor is open, D2 conducts and

20097608

C1 charges to 8V minus a diode drop ()0.4V if using a
Schottky). When the transistor opens in the first cycle, D3
conducts and C1’s polarity is reversed with respect to the
output at C2, producing -8V.

The 23V output is realized with a series of capacitor charge
pumps. It consists of four stages: the first stage includes C4,
D4, and the LM3224 switch; the second stage uses C5, D5,
and D1; the third stage includes C6, D6, and the LM3224
switch; the final stage is C7 and D7. In the first stage, C4
charges to 8V when the LM3224 switch is closed, which
causes D5 to conduct when the switch is open. In the second
stage, the voltage across C5 is VC4 + VD1 - VD5 = VC4 )
8V when the switch is open. However, because C5 is refer­enced to the 8V output, the voltage at C5 is 16V when
referenced to ground. In the third stage, the 16V at C5
appears across C6 when the switch is closed. When the
switch opens, C6 is referenced to the 8V output minus a
diode drop, which raises the voltage at C6 with respect to
ground to about 24V. Hence, in the fourth stage, C7 is
charged to 24V when the switch is open. From the first stage

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Application Information (Continued)

to the last, there are three diode drops that make the output

LM3224

voltage closer to 24 - 3xVDIODE (about 22.8V if a 0.4V
forward drop is assumed).

FIGURE 4. PWM White LED Flash/Torch Driver

20097649

FIGURE 5. Continuously Operating White LED Flash/Torch Driver

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20097650

Application Information (Continued)

The LM3224 can be configured to drive high current white
LEDs for the flash and torch functions of a digital camera,
camera phone, or any other similar light source. The flash/
torch can be set up with the circuit in Figure 4 by using the
resistor R
flow through the LED using the equation:

If the flash and torch modes will both be used the resistor

can be chosen for the higher current flash value. To

R

SET

flash the circuit pull the SHDN high for the time duration
needed for the flash. To enable a lower current torch mode a
PWM signal can be applied to the SHDN pin. The torch
current would then be approximately the percent ON time of
the PWM signal multiplied by the flash (or maximum) cur­rent. The optional disconnect FET can be used to eliminate
leakage current through the LEDs when the part is off and
also to disconnect the LED when the input voltage exceeds
the forward voltage drop of the LED. The maximum output
current the LM3224 can supply in this configuration is shown
in Table 1.

Figure 5 is another method of driving a high current white
LED. This circuit has a higher component count but allows
the switcher to remain on continuously for torch mode reduc­ing stress on the supply. The two FETs also double for a
disconnect function as described above. In this circuit the
device and the torch enable FET are turned on setting a
lower current through the LED. When flash is needed the

to determine the amount of current that will

SET

I

LED=VFB/RSET

flash enable FET is turned on to increase the current for the
amount of time desired. The minimum guaranteed maximum
output current for this circuit is the same as for Figure 4.

TABLE 1. Maximum LED Drive current

=1.25MHz, L=4.7µH, LED V

(F

SW

V

IN

LED Drive Current (mA)

FMAX

=4V (V

OUT

=5.26V)

4.2 1077

4.1 1047

4.0 1017

3.9 987

3.8 958

3.7 929

3.6 900

3.5 871

3.4 842

3.3 814

3.2 785

3.1 757

3.0 729

2.9 701

2.8 673

2.7 646

LM3224

FIGURE 6. 1.25MHz, 5V Output

20097661

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Application Information (Continued)

LM3224

FIGURE 7. 1.25MHz, 8V Output

20097663

FIGURE 8. 1.25MHz, 12V Output

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20097664

Application Information (Continued)

LM3224

FIGURE 9. 1.25MHz, 15V Output

20097665

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Physical Dimensions inches (millimeters)

unless otherwise noted

LM3224 615kHz/1.25MHz Step-up PWM DC/DC Converter

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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